High availability arrayed usb device management system and method

Abstract

The application discloses a high-availability array type USB device management system and method. The system comprises an embedded control surface module, a data surface cascade module and a power surface independent control module; the data surface cascade module comprises a hub controller and a plurality of USB physical ports; the power surface independent control module comprises a load switch for independent power supply of the ports and an analog-to-digital converter for collecting power supply current characteristics; a host computer end is configured with a virtual host controller interface driver; the embedded control surface module obtains characteristic quantity to calculate a deadlock state evaluation factor, controls power supply reset when the evaluation factor is over a threshold value, intercepts a request block, encapsulates a custom topology header and sends the custom topology header to the host computer end to build a virtual topology tree in a kernel. The application can accurately identify a bottom-layer hardware deadlock and apply hard isolation, isolate system device enumeration disorder caused by peripheral reset and ensure that an automatic control instruction has absolute physical certainty.

Description

Technical Field

[0001] This application relates to the field of data communication interface management, and specifically to a high-availability array-type USB device management system and method. Background Technology

[0002] In large-scale automated group control data center scenarios, a single host machine often needs to connect to dozens or more terminal devices. Under high-density access, terminal devices frequently experience system failures that cause the downlink data bus to hang. In such cases, software-level reset commands issued by the operating system cannot be responded to, requiring manual physical plugging and unplugging for recovery, resulting in low operational efficiency. Existing technologies use hubs with port power control to perform physical power-off resets. However, when the terminal is powered on again for enumeration, the operating system is highly susceptible to assigning entirely new instance paths to the device due to missing device serial numbers or timing disturbances. This port drift causes the upper-layer business logic to lose its static mapping association with specific physical ports, resulting in a technical defect where the lower-layer recovers while the upper-layer services remain interrupted. Summary of the Invention

[0003] This application provides a high-availability array-type USB device management system and method, which solves the problem that terminal devices cannot be recovered by software when they physically freeze in high-density USB access environments, and causes disordered device topology mapping at the underlying operating system level.

[0004] In a first aspect, embodiments of this application provide a high-availability array-type USB device management system, including an embedded control plane module, a data plane cascade module, and a power plane independent control module; the data plane cascade module includes a hub controller and multiple USB physical ports, the multiple USB physical ports being cascaded through the hub controller and connected to the embedded control plane module; the power plane independent control module includes a load switch that independently supplies power to each of the USB physical ports, and an analog-to-digital converter (ADC) for acquiring power supply current characteristics, the enable terminal of the load switch and the output terminal of the ADC being connected to the embedded control plane module; the embedded control plane module is used to acquire the real-time current characteristics returned by the ADC to... The embedded control plane module is also used to calculate the deadlock state evaluation factor by considering the error message characteristics of the communication protocol stack; the embedded control plane module is also used to control the corresponding load switch to perform a power supply reset in response to the deadlock state evaluation factor exceeding a set threshold; the embedded control plane module is also used to intercept the Universal Serial Bus Request Block of the USB physical port, and encapsulate a custom topology header containing the physical port identifier of the corresponding USB physical port in the message header, and send it to the host machine through the network interface; the host machine is configured with a Virtual Host Controller Interface Driver, which is used to parse the physical port identifier in the custom topology header and build a virtual topology tree statically mapped to the USB physical port in the system kernel.

[0005] Secondly, embodiments of this application provide a high-availability array-type USB device management method, applied to the high-availability array-type USB device management system provided in the first aspect above. The method connects peripheral devices through multiple USB physical ports of a data plane cascade module, and independently supplies power to each USB physical port through a load switch of a power plane independent control module. It acquires real-time current characteristics returned by the analog-to-digital converter and error message characteristics of the communication protocol stack through an embedded control plane module, and calculates a deadlock state evaluation factor. In response to the deadlock state evaluation factor exceeding a set threshold, the embedded control plane module controls the corresponding load switch to perform a power supply reset. The embedded control plane module intercepts the Universal Serial Bus Request (USB Request) block of the USB physical port and encapsulates a custom topology header containing the physical port identifier of the corresponding USB physical port in the message header. The encapsulated custom topology header is sent to the host machine through a network interface, so that the virtual host controller interface driver configured on the host machine parses the physical port identifier in the custom topology header and constructs a virtual topology tree statically mapped to the USB physical port in the system kernel.

[0006] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor; the memory is used to store a computer program; the processor is coupled to the memory; when the processor executes the computer program, it implements the high-availability array-type USB device management method described in the second aspect above.

[0007] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the high-availability array-type USB device management method described in the second aspect above.

[0008] By adopting the above scheme, this application can accurately identify underlying hardware deadlocks and apply hard isolation through multi-dimensional parameter fusion. Through network transmission isolation header encapsulation and kernel-level virtual port anchoring mechanism, the system isolates the device enumeration sorting disorder of the host operating system driver layer caused by frequent peripheral resets and hot-plugging, thereby ensuring that the instruction addresses issued by the automated group control execution script have absolute physical determinism. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the overall structure of a high-availability array-type USB device management system provided in an embodiment of the present invention.

[0011] Figure 2 This is a flowchart of a high-availability array-type USB device management method provided in an embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures:

[0013] 101-Embedded control plane module, 102-Data plane cascade module, 103-Power plane independent control module, 104-Host side, 1021-Hub controller, 1022-USB physical port, 1031-Load switch, 1032-Analog-to-digital converter, 1033-Serial shift register, 1041-Virtual host controller interface driver. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. The terminology used in this application is merely for the purpose of describing specific embodiments and is not intended to limit the application.

[0015] Figure 1 This is a schematic diagram of the overall structure of a high-availability array-type USB device management system provided in an embodiment of this application. Figure 1 As shown, this high-availability array-type USB device management system is mainly divided into a cooperating control plane, data plane, and power plane at the hardware architecture level. Specifically, the system includes an embedded control plane module 101, a data plane cascade module 102, a power plane independent control module 103, and a remote host terminal 104.

[0016] The data plane cascade module 102 forms a data bridge between the system and a large number of peripheral devices under test. This data plane cascade module 102 includes a hub controller 1021 and multiple USB physical ports 1022. In this embodiment, 56 USB 3.0 physical ports 1022 are arranged in a matrix on the system panel side. These 56 USB physical ports 1022 are aggregated on the data plane through a tree-like topology cascaded structure composed of eight 7-port industrial-grade hub control chips. The uplink port of the hub controller 1021 is directly connected to the device interface configured inside the embedded control plane module 101, thereby constructing a broadband data aggregation channel.

[0017] The power plane independent control module 103 is responsible for precisely controlling and monitoring the electrical status of each physical access link. This power plane independent control module 103 includes load switches 1031 that independently power the voltage bus pins of each USB physical port 1022. As a preferred hardware implementation, the load switches 1031 employ load switch chips with programmable current limiting and analog current output indication signals. The power plane independent control module 103 also includes an analog-to-digital converter 1032 for acquiring power supply current characteristics. The analog current output indication pins of the 56 load switches 1031 are grouped and connected to four 16-channel, 12-bit resolution analog-to-digital converter chips. The enable terminals of the load switches 1031 and the output terminals of the analog-to-digital converters 1032 are both electrically connected to the embedded control plane module 101. In the specific control link, in order to save control plane pins, the enable terminals of 56 load switches 1031 are connected to multiple sets of serial shift registers 1033. The embedded control plane module 101 outputs general input / output array control signals to the serial shift registers 1033. At the same time, the digital level signal data collected by the analog-to-digital converter 1032 is transmitted back to the embedded control plane module 101 in real time via the serial peripheral interface bus at a sampling rate of 1MHz for current state matrix analysis.

[0018] The embedded control plane module 101 is the core scheduling and diagnostic hub of the entire system. This embedded control plane module 101 contains a microprocessor based on an Advanced Reduced Instruction Set Machine (ARSI) architecture. In this embodiment, the core control hub uses a microprocessor chip with a dual-core processor. As a basic closed-loop support for the hardware base, the peripheral circuitry of the embedded control plane module 101 also includes necessary power conversion networks, a clock crystal oscillator to provide the system clock pulse, a reset circuit to ensure correct chip startup, and a physical layer network communication chip and isolation transformer responsible for physical layer network communication. These peripheral components together ensure the efficient and stable operation of the microprocessor.

[0019] To accurately diagnose the health status of each physical link and prevent misjudgments caused by software-level deadlocks, the embedded control plane module 101 is internally configured with current sampling logic and fusion diagnostic logic. This embedded control plane module 101 is configured to acquire real-time current characteristics returned by the analog-to-digital converter 1032, as well as error message characteristics extracted from the internal communication protocol stack, and calculate a deadlock state evaluation factor accordingly. Specifically, the real-time current characteristics include the transient current change rate of the USB physical port 1022, and the error message characteristics include the number of communication timeouts within a first preset time window. The current sampling logic drives the analog-to-digital converter 1032 to acquire this transient current change rate at a preset high-frequency sampling rate of 1MHz.

[0020] In implementing the computational logic, to achieve deep coupling between the physical parameters of the analog layer and the logical parameters of the data link layer, the system eliminates deadlock judgment logic based on a single fixed threshold. For a specific i-th physical port, the calculation of the deadlock state evaluation factor follows a specific nonlinear combination relationship. Specifically, the system performs a superposition calculation based on the product of the transient current change rate and the first weighting coefficient, and the product of the number of communication timeouts and the second weighting coefficient, and adds an bias to determine the deadlock state evaluation factor. The above computational logic is specifically implemented through the following formula:

[0021]

[0022] Here, the variable 'i' represents the specific physical port number, with a value ranging from 1 to 56. The real-time sampling current magnitude is represented by a variable in amperes. Represents the absolute value of the rate of change of transient current. This reflects the volatility of the current waveform. The first preset time window for observation. In this embodiment, the reference value is 500ms. First weighting coefficient Used to adjust the weight of the effect of the rate of change of current on the final factor. An offset to prevent the denominator from approaching zero. This also represents the system's baseline noise compensation value under no-load conditions, which is set to 0.001 A / s in this embodiment. The total number of polling transactions N sent by the system to this port within the time window. total (i), and the number of communication timeouts N when the device does not respond. timeout (i) The number of error messages N such as packet cyclic redundancy check failure error (i) together constitute the failure rate in the total number of polling transactions. The deadlock status evaluation factor is composed of It is feasible to use an equivalent mathematical model that can reflect the near-stagnation of current differentiation and the surge in message errors.

[0023] Based on the aforementioned fusion diagnostic algorithm, when a persistently high communication error rate is detected in a peripheral device connected to a specific port, and the current waveform returned by the analog-to-digital converter 1032 remains at a stable high level without any operational pulse fluctuations, the embedded control plane module 101 will calculate a maximum deadlock state evaluation factor. When this deadlock state evaluation factor continuously exceeds the system's preset threshold within a second preset time window, the system determines that the corresponding USB physical port 1022 is in a completely hardware-locked state.

[0024] In response to the hardware lock-up state diagnosed above, the embedded control plane module 101 directly controls the corresponding load switch 1031 to perform a power reset. Specifically, this involves triggering a nanosecond-level hard isolation mechanism to forcibly cut off the data pin signal transmission of the USB physical port 1022 on the physical circuitry, while simultaneously outputting a low power-down reset signal to the enable pin of the corresponding load switch 1031 via the serial shift register 1033. The duration of this power-down discharge action is configured to 2000ms to ensure that the motherboard of the peripheral device connected to the USB physical port 1022 depletes the residual charge in its internal capacitors. Subsequently, the system pulls the enable pin high again to complete a thorough physical layer cold reset. Through this nanosecond-level independent hardware isolation and cold reset mechanism, the limitations of the host operating system can be bypassed, forcing the seemingly frozen device out of the dead loop and achieving low-level port-level self-healing.

[0025] After eliminating the underlying physical deadlock, to prevent cold reset actions from disrupting upper-layer services, the system deployed a static binding protocol between the underlying physical topology and virtual interfaces. The embedded control plane module 101, acting as a server node, is configured to operate in a non-transparent mode during routine communication and reset / re-enumeration phases. It intercepts the Universal Serial Bus request blocks uplinked to the aforementioned 56 USB physical ports 1022 and encapsulates these packets with a custom topology header. This custom topology header strictly adheres to the following structure: synchronization start frame boundary, physical port identifier, and payload data carrying the original USB request block. The custom topology header also includes a transmission rate identifier indicating link bandwidth capability and an endpoint descriptor carrying device characteristics. After encapsulation, the data packet is sent to the host machine 104 via the network interface of the embedded control plane module 101, where the network interface can be connected to a network switch for Ethernet packet delivery.

[0026] On the host machine 104 at the other end, a deeply customized virtual host controller interface driver 1041 is deployed within its operating system. The virtual host controller interface driver 1041 is registered as a virtual host controller in the system kernel mode, used to intercept all low-level device enumeration requests issued by the operating system and return the parsed endpoint descriptors to the operating system. When the virtual host controller interface driver 1041 receives a network packet, its core logic is to construct a virtual topology tree in the system kernel, statically mapping each of the 56 USB physical ports 1022. Specifically, the construction process involves simulating the generation of a virtual root hub node object within the operating system's device manager. Under this virtual root hub, the virtual host controller interface driver 1041 pre-allocates a fixed device instance path for each physical port identifier. This device instance path contains a unique device identifier corresponding to that physical port, and this device identifier is strongly bound to the physical port identifier through a mapping table within the driver.

[0027] Under this architecture, when the load switch 1031 performs a 2000ms power reset, causing a real physical link disconnection, the virtual host controller interface driver 1041 will shield this underlying disconnection event and forcibly maintain the connection state of the device instance path in the operating system kernel as active. Simultaneously, the driver layer will suspend and buffer the input / output request packets sent by the upper-layer application and mounted on the device instance path. After the underlying power reset is complete and the corresponding USB physical port 1022 is powered on again and a physical connection is established, the virtual host controller interface driver 1041 unsuspends the buffered input / output request packets and continues data exchange. Through the strong anchoring of packet interception flags and kernel-level virtual ports, the topology disturbances caused by frequent underlying resets are effectively isolated, the side effects of the self-healing mechanism are mitigated, and the business scripts can continuously issue commands to the fixed instance path, achieving absolute static logical connections.

[0028] Building upon the above embodiments, to alleviate the packet forwarding pressure on the core processor and achieve high efficiency and low latency in network transmission, a dedicated data flow control module can be added to the physical layer link of the data plane concatenation module 102 of this system. Specifically, the data plane concatenation module 102 and the embedded control plane module 101 can be combined with a field-programmable gate array (FPGA) for hardware-level preprocessing of data packets. By introducing this mechanism as a pre-filtering and preprocessing engine, the interrupt response overhead of the microprocessor in the embedded control plane module 101 can be reduced, ensuring non-blocking line-speed forwarding of concurrent data streams of hundreds of megabits per second or higher.

[0029] Figure 2 This is a flowchart of a high-availability array-type USB device management method provided by an embodiment of the present invention. This method is applied to various functional modules of the high-availability array-type USB device management system described in the above embodiments. The execution entity for each step is the corresponding hardware processor or driver kernel configured in the system. For example... Figure 2 As shown, this method specifically includes the following collaborative workflow steps:

[0030] In step S201, peripheral devices are connected via multiple USB physical ports 1022 of the data plane cascading module 102, and each USB physical port 1022 is independently powered by a load switch 1031 of the power plane independent control module 103. During this step, the device management system is powered on and initialized, and the hub controller 1021 enumerates the connected physical port links. The microprocessor of the embedded control plane module 101 drives the enable pins of all load switches 1031 to go high, allocating a standard power supply voltage to each peripheral device.

[0031] In step S202, the embedded control plane module 101 acquires the real-time current characteristics returned by the analog-to-digital converter 1032 and the error message characteristics of the communication protocol stack, and calculates the deadlock state evaluation factor. In this step, the embedded control plane module 101 frequently acquires the transient current change rate of the USB physical port 1022. Simultaneously, it uses the built-in network monitoring service to count the number of communication timeouts within a first preset time window. Subsequently, based on the weighted combination of these two heterogeneous indicators—the transient current change rate and the number of communication timeouts—the deadlock state evaluation factor for the corresponding physical port is continuously updated.

[0032] S203, in response to the deadlock state evaluation factor exceeding a set threshold, the embedded control plane module 101 controls the corresponding load switch 1031 to perform a power reset. The microprocessor continuously compares the deadlock state evaluation factor with the preset set threshold. When it is found that the evaluation factor of a certain link surges and exceeds the set threshold continuously within a second preset time window, the system kernel determines that the corresponding USB physical port 1022 is in a hardware-completely locked state due to system crash or other reasons. At this time, the processor generates a hard isolation instruction for the port in the hardware-locked state. On the one hand, the data pin signal transmission of the USB physical port 1022 is cut off on the physical circuit; on the other hand, the hard isolation instruction is converted into a power-off reset level signal and output to the enable terminal of the corresponding load switch 1031 to start the hardware reset. The low-level holding time window of the reset is strictly configured so that the faulty peripheral device connected to the USB physical port 1022 completely depletes the residual charge in its motherboard capacitor network that maintains the kernel's remaining state, ensuring a deep cold start is completed.

[0033] S204, the embedded control plane module 101 intercepts the Universal Serial Bus Request block of the USB physical port 1022 and encapsulates a custom topology header containing the physical port identifier corresponding to the USB physical port 1022 in the message header. During routine communication of the service device and the re-enumeration negotiation phase after reset, the microprocessor of the front-end control plane does not directly forward the original message. It intercepts the uplink Universal Serial Bus Request block at the driver layer and, according to the protocol format, pushes a unique physical port identifier before the data frame to synthesize the encapsulated custom topology header.

[0034] S205, the encapsulated custom topology header is sent to the host machine 104 via the network interface, so that the virtual host controller interface driver 1041 configured on the host machine 104 parses the physical port identifier in the custom topology header and constructs a virtual topology tree statically mapped to the USB physical port 1022 in the system kernel. The front-end system delivers data frames with physical anchors to the back-end host machine 104 via the local area network. After the virtual host controller interface driver 1041 embedded in the host machine 104 intercepts the network data packets, extracts the physical port identifier, and assigns a permanent fixed device instance path to each identifier under the virtual root hub node of the operating system. When a discharge reset causes the physical link to be disconnected and reconnected, the virtual host controller interface driver 1041 keeps the connection state of the device instance path active in the operating system, and suspends all input / output request packets sent from the upper layer to the device instance path in the kernel queue. After the data packet for re-establishing the connection from the front end arrives, the driver layer automatically unsuspends these input / output request packets. This hardware-software co-processing ensures that the lower-level power outage isolation action has no impact on the upper-level management software, maintaining a smooth business experience.

[0035] The system and method provided in this application, through a cross-boundary fusion probe mechanism of the front-end microprocessor between the physical circuit layer and the logic protocol layer, compensates for the lack of intelligent hardware self-healing logic in traditional commercial hubs. Simultaneously, by utilizing custom network protocol encapsulation and kernel-level device virtual tree reconstruction technology on the host machine, a robust buffer is established between physical entity plug-and-play actions and the plug-and-play enumerator of the operating system device. This enables non-intrusive in-situ recovery from hardware failures and continuous operation of upper-layer automated control scripts, reducing the costs of large-scale automated testing and manual maintenance in cloud equipment rooms, as well as the risk of business interruption.

[0036] This application also provides an electronic device for running the control logic and driver programs described in the above embodiments. The electronic device includes a memory and a processor; the memory stores a computer program; the processor is electrically coupled to the memory. When the processor reads and executes the computer program code, it can invoke a hardware interface to implement all steps and business logic of the high-availability array-type USB device management method described above. The memory may contain a non-volatile storage medium or a volatile random access memory. The processor may be a general-purpose central processing unit, a digital signal processor, or other application-specific integrated circuits (ASICs) with logic operation and instruction execution capabilities.

[0037] This application also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements all the steps and business logic of the high-availability array-type USB device management method described above. The computer-readable storage medium may include a non-volatile storage medium, such as a read-only memory or flash memory, or it may include a volatile random access memory.

[0038] It should be noted that the above description is merely a preferred embodiment of this application and does not limit the scope of patent protection of this application. For those skilled in the art, the architectural concept of this application can be modified and varied in various equivalent ways. Any modifications, equivalent substitutions, or partial improvements made within the inventive concept and principles of this application should be included within the scope of protection of this application.

Claims

1. A high-availability array-type USB device management system, characterized in that, It includes an embedded control plane module, a data plane cascade module, and a power plane independent control module; the data plane cascade module includes a hub controller and multiple USB physical ports, which are cascaded through the hub controller and connected to the embedded control plane module; The power plane independent control module includes a load switch that independently supplies power to each of the USB physical ports, and an analog-to-digital converter (ADC) for acquiring power supply current characteristics. The enable terminal of the load switch and the output terminal of the ADC are both connected to the embedded control plane module. The embedded control plane module is used to acquire the real-time current characteristics returned by the ADC and the error message characteristics of the communication protocol stack, and calculate a deadlock state evaluation factor. The embedded control plane module is also used to control the corresponding load switch to perform a power supply reset in response to the deadlock state evaluation factor exceeding a set threshold. The embedded control plane module is also used to intercept the Universal Serial Bus Request (USB Request) block of the USB physical port, and encapsulate a custom topology header containing the physical port identifier of the corresponding USB physical port in the message header, and send it to the host machine through the network interface. The host machine is configured with a Virtual Host Controller Interface (VHController) driver, which is used to parse the physical port identifier in the custom topology header and construct a virtual topology tree statically mapped to the USB physical port in the system kernel.

2. The high-availability array-type USB device management system as described in claim 1, characterized in that, The real-time current characteristic includes the transient current change rate of the USB physical port, and the error message characteristic includes the number of communication timeouts within a first preset time window; the embedded control plane module is configured with current sampling logic, which is used to drive the analog-to-digital converter to obtain the transient current change rate at a preset high-frequency sampling rate.

3. The high-availability array-type USB device management system as described in claim 2, characterized in that, The embedded control plane module is configured with fusion diagnostic logic; the fusion diagnostic logic is configured to calculate the deadlock state evaluation factor by superimposing the product of the transient current change rate and the first weighting coefficient, and the product of the number of communication timeouts and the second weighting coefficient, and adding an offset; when the deadlock state evaluation factor exceeds the set threshold continuously within a second preset time window, the corresponding USB physical port is determined to be in a hardware deadlock state; in response to the hardware deadlock state, nanosecond-level hard isolation is triggered and a power-off reset level signal is output to the enable terminal of the corresponding load switch; the nanosecond-level hard isolation is configured to cut off the data pin signal transmission of the USB physical port on the physical circuit; the offset represents the basic noise floor compensation value of the system in the no-load state.

4. The high-availability array-type USB device management system as described in claim 1, characterized in that, The custom topology header also includes a transmission rate identifier and an endpoint descriptor; the virtual host controller interface driver is registered as a virtual host controller in kernel mode to intercept device enumeration requests issued by the operating system and return the parsed endpoint descriptor to the operating system.

5. The high-availability array-type USB device management system as described in claim 4, characterized in that, The logical configuration of the system kernel to build a virtual topology tree that is statically mapped to the USB physical port is as follows: under the virtual root hub, a fixed device instance path is assigned to each physical port identifier. The device instance path contains a unique device identifier, and the device identifier and the physical port identifier are permanently bound through a mapping table. In response to the physical link disconnection caused by the power reset performed by the load switch, the virtual host controller interface driver keeps the connection state of the device instance path active and suspends the input / output request packets mounted on the device instance path; and after the power reset is completed and the corresponding USB physical port re-establishes the physical connection, it unsuspends the input / output request packets.

6. A high-availability array-type USB device management method, characterized in that, Applied to the high-availability array-type USB device management system as described in claim 1, the method connects peripheral devices through multiple USB physical ports of the data plane cascade module, and independently supplies power to each of the USB physical ports through the load switch of the power plane independent control module; it obtains the real-time current characteristics returned by the analog-to-digital converter and the error message characteristics of the communication protocol stack through the embedded control plane module, and calculates the deadlock state evaluation factor; in response to the deadlock state evaluation factor exceeding a set threshold, it controls the corresponding load switch to perform a power supply reset through the embedded control plane module. The embedded control plane module intercepts the Universal Serial Bus Request block of the USB physical port and encapsulates a custom topology header containing the physical port identifier corresponding to the USB physical port in the message header. The encapsulated custom topology header is sent to the host machine via the network interface, so that the virtual host controller interface driver configured on the host machine can parse the physical port identifier in the custom topology header and build a virtual topology tree statically mapped to the USB physical port in the system kernel.

7. The high-availability array-type USB device management method as described in claim 6, characterized in that, When calculating the deadlock state evaluation factor, the transient current change rate of the USB physical port and the number of communication timeouts within a first preset time window are obtained, and the deadlock state evaluation factor is updated based on the weighted combination of the transient current change rate and the number of communication timeouts.

8. The high-availability array-type USB device management method as described in claim 7, characterized in that, When performing a power reset, the deadlock state evaluation factor is compared with the set threshold. When the deadlock state evaluation factor exceeds the set threshold continuously within a second preset time window, the corresponding USB physical port is determined to be in a hardware deadlock state, and a hard isolation instruction is generated for the port in the hardware deadlock state. The data pin signal transmission of the USB physical port is cut off on the physical circuit. Then, the hard isolation instruction is converted into a power-off reset level signal and output to the enable terminal of the corresponding load switch to perform a hardware reset. The time width of the hardware reset is configured to be greater than the preset time for the internal capacitor of the peripheral device to deplete its charge.

9. An electronic device, characterized in that, It includes a memory and a processor; the memory is used to store a computer program; the processor is coupled to the memory; when the processor executes the computer program, it implements the high-availability array-type USB device management method as described in claim 6.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the high-availability array-type USB device management method as described in claim 6.

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