A control circuit and method of an interleaved three-phase rectifier, charging pile

Abstract

The application relates to the technical field of circuit control, in particular to a control circuit and method of an interleaved parallel three-phase rectifier and a charging pile. The control circuit comprises a signal processing module, a phase-locked loop, a loop control module, a comparator module and a pulse generation module. The comparator module is used for outputting six zero-crossing signals based on six inductance currents of a main phase and a slave phase and built-in programmable thresholds. The pulse generation module is used for generating main-slave staggered carriers with a phase difference of 180 degrees based on the main phase zero-crossing signal, and generating and outputting 12 driving pulses based on the main-slave staggered carriers, a three-phase modulation signal, an angle and the six zero-crossing signals. The conduction of the driving pulses is triggered by the zero-crossing signal to clear the carrier counter, and the turn-off is generated when the carrier count value reaches the turn-off threshold corresponding to the three-phase modulation signal. In conclusion, the technical scheme provided by the application can realize CRM control of the interleaved parallel three-phase rectifier and improve the current control stability.

Description

[0001] This application claims priority to Chinese patent applications filed on September 30, 2025, with application number 202511430142.6 and entitled "A Power Supply System", and filed on November 20, 2025, with application number 202511714931.2 and entitled "A Control Chip", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of circuit control technology, and in particular to a control circuit and method for an interleaved parallel three-phase rectifier, and a charging pile. Background Technology

[0003] CRM (Critical Conduction Mode) offers advantages such as no reverse recovery in diodes, lower switching losses, and less device stress, making it primarily suitable for low- to medium-power applications. When the converter operates in CRM mode, a current transformer is typically used to detect the inductor current, or the inductor current is obtained by detecting the voltage across the auxiliary winding of the inductor. This generates a zero-crossing signal for the inductor current, which is then used to achieve critical conduction control of the converter.

[0004] However, the current control stability of this control mode is poor. Specifically, after the inductor current drops to zero, the inductor will resonate with the parasitic capacitance of the power transistor, causing the inductor current to drop further, or even the current to flow in reverse. This will lower the average value of the inductor current and cause distortion of the input current waveform. Summary of the Invention

[0005] This application is made in view of the above-mentioned problems. This application provides a control circuit and method for an interleaved parallel three-phase rectifier, and a charging pile, which are at least used to realize CRM control of the interleaved parallel three-phase rectifier and improve the stability of current control.

[0006] According to one aspect of this application, a control circuit for an interleaved parallel three-phase rectifier is provided, comprising: a signal processing module, a phase-locked loop (PLL), a loop control module, a comparator module, and a pulse generation module; wherein, the signal processing module is used to acquire the three-phase inductor current, three-phase line voltage, and output voltage of the main phase; the PLL, connected to the signal processing module, is used to determine the angle based on the three-phase line voltage; the loop control module, connected to the signal processing module and the PLL, is used to determine the three-phase modulation signal based on the three-phase inductor current, output voltage, and angle; and the comparator module... The system is used to output six zero-crossing signals based on the six inductor currents of the master and slave phases and the built-in programmable threshold. The pulse generation module, connected to the loop control module, phase-locked loop and comparator module, is used to generate master-slave interleaved carriers with a phase difference of 180° based on the master phase zero-crossing signal, and to generate and output 12 drive pulses based on the master-slave interleaved carriers, three-phase modulation signals, angle and six zero-crossing signals. The drive pulses are turned on by the zero-crossing signal triggering the carrier counter to be cleared, and turned off by the carrier count value reaching the turn-off threshold corresponding to the three-phase modulation signal.

[0007] Furthermore, according to one embodiment of one aspect of this application, the pulse generation module includes: a sector determination submodule, a carrier generation submodule, a pulse generation submodule, and a pulse output submodule; wherein, the sector determination submodule is used to determine the current sector based on an angle; the carrier generation submodule is used to generate a master-slave interleaved carrier with a phase difference of 180° based on the master phase zero-crossing signal and the current sector; the pulse generation submodule, connected to the carrier generation submodule and the sector determination submodule, is used to generate 12 driving pulses based on the master-slave interleaved carrier, the current sector, the three-phase modulation signal, and six zero-crossing signals; and the pulse output submodule, connected to the pulse generation submodule, is used to dynamically output 12 driving pulses based on the current sector and the current polarity, so that the 12 driving pulses are matched with the current direction.

[0008] Furthermore, in one embodiment of one aspect of this application, the conduction of the drive pulse is generated by a delay after the carrier counter is cleared by a zero-crossing signal. The delay is the dead time of the rising edge of the switching transistor, which is used to prevent the upper and lower transistors of the same bridge arm from shoot-through.

[0009] Furthermore, according to one embodiment of one aspect of this application, the carrier generation submodule is specifically configured to: clear the main carrier counter to zero and generate the main carrier at the rising edge of the main phase zero-crossing signal, and record the main carrier period; and generate the slave carrier using half of the main carrier period as the initial value of the slave carrier counter.

[0010] Furthermore, according to one embodiment of one aspect of this application, the pulse output submodule is specifically used to: determine the main and auxiliary pulses of the 12 drive pulses by looking up a table based on the current sector and current polarity, and output them dynamically; when the inductor current is positive, define the lower switch drive pulse of the corresponding bridge arm as the main pulse and output it directly; when the inductor current is negative, define the upper switch drive pulse of the corresponding bridge arm as the main pulse and switch the drive channel output.

[0011] Furthermore, according to one embodiment of one aspect of this application, the pulse generation module further includes: a pulse blocking submodule, used to block the driving pulse of the corresponding phase when the zero-crossing signal triggers conduction, until the next carrier cycle.

[0012] Furthermore, according to one embodiment of one aspect of this application, the pulse generation module further includes: a clamping processing submodule, used to compare the three-phase modulation signal with the carrier maximum value of the corresponding phase, and when the modulation signal of a certain phase is greater than the corresponding carrier maximum value, to control the corresponding switch to remain on according to the current polarity to achieve clamping; wherein, if the polarity of the inductor current is positive, the corresponding switch is the lower switch of the corresponding bridge arm; if the polarity of the inductor current is negative, the corresponding switch is the upper switch of the corresponding bridge arm.

[0013] Furthermore, according to one embodiment of one aspect of this application, the comparator module is specifically configured to: perform analog low-pass filtering on the six inductor currents of the master phase and slave phase to obtain six filtered currents; perform analog-to-digital conversion on the six filtered currents to obtain six current data; compare the six current data with a built-in programmable threshold to obtain digital level signals; wherein, if the current data is greater than the built-in programmable threshold, the digital level signal of the corresponding channel is low; if the current data is less than the built-in programmable threshold, the digital level signal of the corresponding channel is high; and perform digital filtering on the digital level signals to obtain six zero-crossing signals.

[0014] Furthermore, according to one embodiment of one aspect of this application, the signal processing module includes: an analog filtering submodule and a sampling processing submodule; wherein, the analog filtering submodule is used to acquire three-phase inductor current and perform analog filtering processing on the three-phase inductor current; the sampling processing submodule is used to sample the output voltage, the three-phase line voltage and the filtered three-phase inductor current.

[0015] Furthermore, according to one embodiment of one aspect of this application, the loop control module includes: a voltage loop submodule, a current generation submodule, and a current loop submodule; wherein, the voltage loop submodule is used to determine a reference value for the three-phase peak current based on the difference between the output voltage and the voltage target value; the current generation submodule is used to generate a three-phase current reference signal with a phase difference of 120° based on the angle and the reference value; and the current loop submodule is used to generate and output a three-phase modulation signal based on the difference between the current reference signal and the three-phase inductor current.

[0016] According to another aspect of this application, a control method for an interleaved parallel three-phase rectifier is provided, comprising: acquiring the three-phase inductor current, three-phase line voltage, and output voltage of the main phase; determining the angle based on the three-phase line voltage; determining the three-phase modulation signal based on the three-phase inductor current, output voltage, and angle; outputting six zero-crossing signals based on the six inductor currents of the main and slave phases and a built-in programmable threshold; generating a master-slave interleaved carrier wave with a phase difference of 180° based on the master-slave interleaved carrier wave, the three-phase modulation signal, the angle, and the six zero-crossing signals; wherein the conduction of the drive pulse is generated by the zero-crossing signal triggering the carrier counter to be cleared, and the turn-off is generated by the carrier count value reaching the turn-off threshold corresponding to the three-phase modulation signal.

[0017] In addition, according to another aspect of this application, the method further includes: after the chip is powered on, configuring the pre-configuration parameters of each module register, the pre-configuration parameters including one or more of the following: analog filter module enable state, voltage loop sub-module parameters, current loop module parameters, dead time, built-in programmable threshold, and voltage target value.

[0018] According to another aspect of this application, a charging pile is provided, comprising: an AC filter, a control circuit of any of the above embodiments, a rectifier bridge, a bus capacitor, and a DC-DC converter; wherein, the AC filter is connected to the power grid input and is used to filter the input AC power; the control circuit of any of the above embodiments is used to control the rectification process; the rectifier bridge is connected to the AC filter and the control circuit and is used to convert the filtered AC power into DC power; the bus capacitor is connected to the rectifier bridge and is used to stabilize the DC bus voltage; and the DC-DC converter is connected to the bus capacitor and is used to output DC power.

[0019] According to another aspect of this application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method described in any of the above embodiments.

[0020] According to another aspect of this application, a computer-readable storage medium is provided that stores a computer program / instructions thereon, which, when executed by a processor, implements the methods described in any of the above embodiments.

[0021] According to another aspect of this application, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the methods described in any of the above embodiments.

[0022] As will be described in detail below, a control circuit and method for an interleaved parallel three-phase rectifier, and a charging pile according to embodiments of this application, are described. The signal processing module acquires the three-phase inductor current, three-phase line voltage, and output voltage of the main phase. The phase-locked loop (PLL) determines the current phase angle based on these signals. The loop control module generates a three-phase modulation signal by combining the three-phase inductor current, output voltage, and phase angle. The comparator module directly outputs six zero-crossing signals based on the comparison results of the six inductor currents of the main and slave phases with the built-in programmable thresholds. This application abandons the traditional CRM control method that uses the inductor current returning to zero as the trigger condition, and instead... When the inductor current reaches a programmable threshold, a zero-crossing signal is triggered, thereby initiating CRM control. This prevents inductor current reversal at its source. Furthermore, the pulse generation module generates a master-slave interleaved carrier wave with a 180° phase difference based on the primary phase zero-crossing signal, and outputs 12 drive pulses in conjunction with relevant signals. The drive pulses employ a control logic of "zero-crossing signal triggers counter reset to achieve conduction, and count value reaches set threshold to turn off," ensuring that the inductor current operates stably in the critical conduction state, effectively suppressing current backflow, realizing CRM control of the interleaved parallel three-phase rectifier, and significantly improving the stability of current control.

[0023] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0024] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0025] Figure 1 This is a schematic diagram of the control circuit architecture of an interleaved parallel three-phase rectifier provided in an embodiment of this application.

[0026] Figure 2 This is a schematic diagram of an interleaved parallel three-phase rectifier provided in an embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the architecture of a pulse generation module provided in an embodiment of this application.

[0028] Figure 4 This is a schematic diagram illustrating the working principle of a carrier generation submodule provided in an embodiment of this application.

[0029] Figure 5 This is a schematic diagram of one working mode of the pulse output submodule provided in an embodiment of this application.

[0030] Figure 6 This is a schematic diagram of another operating mode of the pulse output submodule provided in the embodiments of this application.

[0031] Figure 7 This is a schematic diagram of the working status of each sector within a power frequency cycle, provided for an embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the architecture of a comparator module provided in an embodiment of this application.

[0033] Figure 9 This is a schematic diagram illustrating the comparison principle of a comparator module provided in an embodiment of this application.

[0034] Figure 10 This is a schematic diagram of a loop control module provided in an embodiment of this application.

[0035] Figure 11 This is a flowchart illustrating a control method for an interleaved parallel three-phase rectifier provided in an embodiment of this application.

[0036] Figure 12 This is a schematic diagram of the architecture of a charging pile provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0038] To address the issues of complex circuitry and poor current control stability in related technologies that rely on additional detection circuits for inductor current zero-crossing detection and CRM control, this disclosure provides a novel design concept: eliminating the need for an additional inductor current zero-crossing detection circuit and using inductor current zero-crossing as the trigger condition for CRM control, instead triggering the generation of a zero-crossing signal when the inductor current reaches a programmable threshold, thereby initiating CRM control. This fundamentally prevents inductor current reversal. Furthermore, during CRM control, the drive pulse employs a control logic of "zero-crossing signal triggers counter reset and conduction, count value reaches threshold and then turns off," ensuring the inductor current operates stably in a critical conduction state, suppressing current reverse flow, and achieving CRM control of the interleaved parallel three-phase rectifier, significantly improving current control stability.

[0039] The following is a detailed explanation.

[0040] This application provides a control circuit for an interleaved parallel three-phase rectifier. Please refer to... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the control circuit architecture for an interleaved parallel three-phase rectifier provided in an embodiment of this application. Figure 2 This is a schematic diagram of an interleaved parallel three-phase rectifier provided in an embodiment of this application.

[0041] To facilitate understanding, let's first combine... Figure 2 Briefly describe the system architecture of an interleaved parallel three-phase rectifier. For example... Figure 2 As shown, the interleaved parallel three-phase rectifier adopts a master-slave phase structure with two sets of three-phase bridge arms connected in parallel. The master phase bridge arm consists of switching transistors Q1~Q6, and the slave phase bridge arm consists of switching transistors Q7~Q12. The two sets of bridge arms are connected by inductors (i.e.,...) L 1a , L 1b , L 1c and L 2a , L 2b , L 2c It is connected to the three-phase AC input side. The AC side is equipped with a filter inductor (i.e., L ga , L gb , L gc ) and filter capacitor (i.e. C gThe filter structure, composed of [missing information], is called an AC filter (also known as an LCL filter). The AC filter is connected to a rectifier bridge, which consists of two sets of bridge arms corresponding to the main and slave phases. The output terminals of the two sets of bridge arms are respectively connected to the bus capacitor (i.e., [missing information]). C 1. C 2) Finally, the current flows to the DC side bus capacitor (i.e. C O Output DC bus voltage (also known as output voltage, i.e.) V dc ).in, a , b , c The three phases used to distinguish between the primary and secondary phases are: 1 represents the primary phase, and 2 represents the secondary phase. Furthermore, U ab , U bc , U ca This indicates the three-phase line voltage (also known as the three-phase grid voltage). i a1 , i b1 , i c1 This indicates the corresponding three-phase inductor current; i a2 , i b2 , i c2 This indicates the current from the corresponding three-phase inductor. It should be understood that... Figure 2 This is merely an example; in real-world scenarios, interleaved three-phase rectifiers may have more or fewer devices or architectures, and this disclosure does not impose any particular limitations on this.

[0042] like Figure 1 As shown, the control circuit 100 of the interleaved parallel three-phase rectifier provided in this embodiment includes: a signal processing module 110, a phase-locked loop 120, a loop control module 130, a comparator module 140, and a pulse generation module 150. This control circuit 100 can be used for... Figure 2 The interleaved parallel three-phase rectifier shown can be connected between the AC filter and the rectifier bridge. It can output 12 drive pulses to achieve coordinated control of the switching transistors Q1~Q12 of the main phase / slave phase bridge arm, thereby realizing the power factor correction and voltage regulation control functions of the interleaved parallel three-phase rectifier.

[0043] The signal processing module 110 is used to acquire the three-phase inductor current, three-phase line voltage, and output voltage of the main phase. The signal processing module 110 is at least used to acquire the inductor current signal, the inductor voltage signal, and the output voltage of the main phase in an interleaved parallel three-phase rectifier. The output voltage (i.e.,V dc This refers to the output voltage of an interleaved parallel three-phase rectifier, also known as the bus output voltage or DC bus voltage. In a specific scenario, the signal processing module 110 must at least have sampling capability, meaning it can sample at least the three-phase line voltage, the main phase three-phase inductor current, and the bus voltage. In one exemplary embodiment, Figure 1 The signal processing module 110 shown includes an analog filtering submodule 111 and a sampling processing submodule 112, which will be described in detail later. Other implementation methods are also possible in actual scenarios, and this application is not limited thereto. In other embodiments, for example, the signal processing module 110 can also be used to collect the three-phase inductor current of the slave phase, etc., which will not be elaborated here.

[0044] Phase-locked loop 120, connected to signal processing module 110, is used to determine the angle based on the three-phase line voltage. Phase-locked loop 120 can determine the angle, i.e., the current phase angle (which can be denoted as...), based on the three-phase line voltage of the main phase. Thetα The angle can be used to determine the three-phase modulation signal. Specifically, the angle can be input into the loop control module 130 so that the loop control module 130 can determine the three-phase current reference signal with a 120° phase difference (which can be denoted as...). I a_ref , I b_ref , I c_ref The current reference signal can be used to determine the three-phase modulation signal. Furthermore, the angle can also be used to indicate the current sector; specifically, the angle can be input into the pulse generation module 150 so that the pulse generation module 150 can determine the current sector and generate a drive pulse adapted to the current sector, as explained later. In practical scenarios, the phase-locked loop 120 has no dependence on or special limitations on external hardware circuits; for example, it can be implemented purely in software through embedded algorithm logic.

[0045] The loop control module 130, connected to the signal processing module 110 and the phase-locked loop 120, is used to determine the three-phase modulation signal based on the three-phase inductor current, three-phase line voltage, and angle. Specifically, the loop control module 130 can output the voltage (i.e., V dc ) and the target voltage value (denoted as V dc_ref The reference value for determining the three-phase peak current (which can be denoted as ) is used as the control object. I peak_ref Based on the angle and reference value determined by the phase-locked loop 120, a three-phase current reference signal with a phase difference of 120° is generated. Then, based on the three-phase inductor current and the current reference signal, the final three-phase modulation signal (which can be denoted as...) is determined. T a , T b, T c In real-world scenarios, the loop control module 130 has no dependence on or special restrictions on external hardware circuits; for example, it can be implemented in pure software through embedded algorithm logic.

[0046] Comparator module 140 is used to output six zero-crossing signals based on the six inductor currents of the master and slave phases and the built-in programmable threshold. For example... Figure 1 As shown, the input to comparator module 140 is the main phase inductor current ( i a1 , i b1 , i c1 ) and from the phase inductor current ( i a2 , i b2 , i c2 The system outputs six inductor current signals. Furthermore, the comparator module 140 independently compares each inductor current signal with a built-in programmable threshold, outputting the corresponding zero-crossing signals for each of the three main phases and the three slave phases. It should be understood that the six zero-crossing signals mentioned here refer to the independent zero-crossing signals corresponding to each of the six inductor current signals, not a unified output of six signals.

[0047] The zero-crossing signal can at least be used to trigger the CRM carrier zeroing event of the corresponding path (or bridge arm). Specifically, the built-in programmable threshold can be customized based on the actual scenario. The built-in programmable threshold can be a positive value above zero potential. In this way, the comparator module 140 can output the zero-crossing signal before the inductor current drops to 0, thereby triggering the CRM carrier zeroing in advance and avoiding current reverse transmission. Compared with the traditional CRM control method that requires additional inductor current zero-crossing detection to use inductor current zero-crossing as the trigger condition in related technologies, this application can trigger the generation of the zero-crossing signal when the inductor current reaches the programmable threshold, thereby starting CRM control in advance. This can fundamentally prevent inductor current reverse transmission, making the inductor current operate stably in the critical conduction state and greatly improving the stability of current control. In addition, the zero-crossing signal can also have other applications. For example, in some embodiments, the zero-crossing signal can be used to trigger the pulse blocking event of the DCM phase, which will be detailed later.

[0048] The pulse generation module 150, connected to the loop control module 130, the phase-locked loop 120, and the comparator module 140, is used to generate master-slave interleaved carriers with a phase difference of 180° based on the master phase zero-crossing signal. Based on the master-slave interleaved carriers, the three-phase modulation signal, the angle, and the six zero-crossing signals, it generates and outputs 12 drive pulses. The drive pulses are turned on by the zero-crossing signal triggering the carrier counter to reset, and turned off by the carrier counter reaching the turn-off threshold corresponding to the three-phase modulation signal. The turn-off threshold corresponding to the three-phase modulation signal can specifically be the value of the three-phase modulation signal, i.e. T a , T b , T c .

[0049] like Figure 1 As shown, the inputs of the pulse generation module 150 include: the three-phase modulation signal output by the loop control module 130, the angle output by the phase-locked loop 120, and the zero-crossing signal output by the comparator module 140; its output is 12 drive pulses, which are used to drive and control the upper and lower switching transistors (denoted as Q1~Q12) corresponding to the six bridge arms in the interleaved parallel three-phase rectifier.

[0050] For any one of the 12 drive pulses, this application employs a control logic of "zero-crossing signal triggering counter reset and conduction, count value reaching threshold and turn off". Specifically, each switch in the interleaved parallel three-phase rectifier can correspond to an independent carrier counter. The carrier counter is forcibly reset to zero upon receiving a zero-crossing signal. Simultaneously with its reset, the drive pulse is turned on (e.g., the drive pulse is set to a high level), and the switch is turned on. After the switch is turned on, the carrier counter increments from zero. When the count value of the carrier counter reaches the turn-off threshold corresponding to the three-phase modulation signal, the drive pulse is turned off (e.g., the drive pulse is set to a low level), i.e., the switch is turned off. In this process, whether the switch is turned on depends on whether the inductor current reaches the built-in programmable threshold; while whether the switch is turned off depends on whether the three-phase modulation signal reaches the turn-off threshold. Based on this mechanism, this application can realize CRM control of interleaved parallel three-phase rectifiers and make the inductor current work stably in the critical conduction state, effectively suppressing the reverse current flow, avoiding the average value of the inductor current being pulled down, and also avoiding the distortion of the input current waveform, thus ensuring the stability of current control.

[0051] In one exemplary embodiment, the comparator module 140 is specifically configured to: perform analog low-pass filtering on the six inductor currents of the master phase and slave phase to obtain six filtered currents; compare the six filtered currents with a built-in programmable threshold to obtain digital level signals; wherein, if the filtered current is greater than the built-in programmable threshold, the digital level signal of the corresponding channel is low; if the filtered current is less than the built-in programmable threshold, the digital level signal of the corresponding channel is high; and perform digital filtering on the digital level signals to obtain six zero-crossing signals.

[0052] You can refer to this. Figure 3 , Figure 3 This is a schematic diagram of the architecture of a comparator module provided in an embodiment of this application. Figure 3 As shown, the comparator module 140 may include three sub-modules: an analog low-pass filter sub-module 141, a comparison sub-module 142, and a digital filter sub-module 143. The analog low-pass filter module can be implemented using an analog low-pass filter circuit, which is specifically used to filter out high-frequency noise. In some embodiments, prior to threshold comparison, additional digital filtering (e.g., using a triple moving average filter) can be performed to further stabilize the signal.

[0053] Furthermore, the comparator module 140 may have a built-in programmable threshold or a built-in memory (any hardware or software structure that can be used to store the programmable threshold, such as...). Figure 3 The module register 144 shown (the name is not limited in this application) may have a built-in communication structure (e.g., a wired or wireless communication unit) that can be connected to the memory through the communication structure to obtain the built-in programmable threshold. As mentioned earlier, the programmable threshold can be configured through registers to meet the zero-crossing detection requirements of different current amplitude scenarios. This disclosure does not impose any particular limitations on the range and accuracy of the programmable threshold; for example, it can be a range of 0-2V with an accuracy of 10mV. This is neither exhaustive nor limited.

[0054] The comparison submodule 142 compares the preprocessed current signal (i.e., the six-channel filtered current) with a programmable threshold. If the current signal (i.e., the six-channel filtered current) is greater than the programmable threshold, a low level is output; if the current signal (i.e., the six-channel filtered current) is less than the programmable threshold, a high level is output. In this way, six digital level signals can be output, which, after processing by the digital filtering submodule 143, yield six zero-crossing signals. These six zero-crossing signals can be used as CRM carrier zero-crossing trigger events and DCM (Discontinuous Conduction Mode) pulse blocking trigger events, respectively, as described above.

[0055] For example, refer to Figure 4 , Figure 4This is a schematic diagram illustrating the comparison principle of a comparator module provided in an embodiment of this application. Figure 4 As shown, the programmable threshold can be set to a positive value above zero potential. In this embodiment, the inductor current of the main phase A is used. i a1 For example, when the inductor current i a1 When the current exceeds the programmable threshold, the comparator module 140 outputs a low-level digital level signal for the main phase A; when the inductor current... i a1 When the current is less than the programmable threshold, the comparator module 140 outputs a high-level digital level signal for the main phase A. Specifically, in the inductor current... i a1 When the voltage drops to the programmable threshold, the output signal of comparator module 140 transitions from low to high, generating a rising edge. This application uses this as the trigger event for carrier zeroing in CRM mode. This design allows CRM to be triggered before the inductor current reaches zero potential, enabling the switching transistor to turn on earlier. The inductor current can then smoothly freewheel at zero, avoiding current reversal and dead-time distortion, thus ensuring efficient and stable operation in CRM mode. It should be understood that... Figure 4 This is merely an example; the control principle for the inductor current of other master-slave three-phase inductors is the same and will not be repeated here.

[0056] It should be understood that the rising and falling edges of the zero-crossing signal defined in this application are based on the premise that the comparator module 140 outputs a high level as an effective state (i.e., a zero-crossing signal). In actual circuit design, the output of the comparator module 140 can also be reversed as needed, in which case the high / low level transition direction and the correspondence between rising and falling edges in this application are reversed accordingly. For example, with Figure 4 Based on this, if the comparator module 140 outputs a low level as the active state (i.e., reverse design), the original rising edge will become a falling edge, and the original falling edge will become a rising edge. At this time, the falling edge of the zero-crossing signal is used to trigger the CRM phase carrier to clear zero. Further details are omitted.

[0057] In one exemplary embodiment, reference may be made to Figure 5 , Figure 5 This is a schematic diagram of the architecture of a pulse generation module provided in an embodiment of this application. Figure 5As shown, the pulse generation module 150 includes: a sector determination submodule 151, a carrier generation submodule 152, a pulse generation submodule 153, and a pulse output submodule 154. Specifically, the sector determination submodule 151 is used to determine the current sector based on an angle; the carrier generation submodule 152 is used to generate a master-slave interleaved carrier with a phase difference of 180° based on the master-phase zero-crossing signal and the current sector; the pulse generation submodule 153, connected to the carrier generation submodule 152, is used to generate 12 drive pulses based on the master-slave interleaved carrier, a three-phase modulation signal, and six zero-crossing signals; and the pulse output submodule 154, connected to the pulse generation submodule 153 and the sector determination submodule 151, is used to dynamically output 12 drive pulses based on the current sector and current polarity, so that the 12 drive pulses match the current direction.

[0058] Specifically, this application divides the 360° power frequency cycle into 12 equal 30° sectors, thus obtaining: Sector 1 (0°≤ α <30°), Sector 2 (30°≤ α <60°), ..., Sector 12 (330°≤ α <360°). Thus, for the sector determination submodule 151, based on the angle determined by the phase-locked loop 120, the sector to which the angle belongs can be determined, and the sector number (1-12) is output to the carrier generation submodule 152, the pulse generation submodule 153 and the pulse output submodule 154.

[0059] A master-slave interleaved carrier with a 180° phase difference means that there is a 180° phase difference between the master phase carrier and the slave phase carrier. The carrier generation submodule 152 can use half of the master carrier period as the starting point for slave carrier generation. In specific implementation, the master-slave interleaved carrier can be generated based on a carrier counter (unlimited number of bits, such as 16 bits; unlimited clock frequency, such as 1MHz).

[0060] In one exemplary embodiment, reference can be made to Figure 6 , Figure 6 This is a schematic diagram illustrating the working principle of a carrier generation submodule provided in an embodiment of this application. Figure 6 In the illustrated embodiment, the carrier generation submodule 152 is specifically used to: clear the main carrier counter and generate the main carrier at the rising edge of the main phase zero-crossing signal, and record the main carrier period; and generate the slave carrier using half of the main carrier period as the initial value of the slave carrier counter. Figure 6 As shown, the main carrier counter can be cleared based on the zero-crossing signal output by comparator module 140. This clearing event can occur at the rising edge of the zero-crossing signal of the current sector CRM phase inductor current (e.g., ...). Figure 4Triggered by the primary carrier counter (as shown), this application generates a primary carrier and records its period (denoted as PRD) while performing a zeroing process. It should be understood that PRD is the count value corresponding to the time it takes for the primary carrier counter to count from 0 to its maximum value, and its value changes dynamically with frequency. Furthermore, while clearing the primary carrier counter, this application sets the slave carrier count value to PRD / 2 and the period value to PRD, and generates a slave carrier accordingly. The generated slave carrier naturally has a 180° phase difference with the primary carrier. In this embodiment, the master-slave interleaved carriers can be implemented based on the same counter hardware, eliminating the need for additional synchronization logic or alignment processing, thus simplifying hardware design and improving carrier synchronization accuracy.

[0061] The inputs to the pulse generation submodule 153 include: master-slave interleaved carrier (i.e., master carrier and slave carrier), and tri-phase modulation signal (i.e., ... T a , T b , T c ) and six zero-crossing signals (denoted as ocp_i a1 , ocp_i b1 , ocp_i c1 , ocp_i a2 , ocp_i b2 , ocp_i c2 The output includes 12 drive pulses, namely the drive signals for Q1~Q12 (which can be denoted as...). Q1~ Q12).

[0062] As mentioned earlier, the drive pulse uses a control logic of "zero-crossing signal triggers counter reset to achieve conduction, and the count value turns off when it reaches a set threshold," such as... Figure 5 As shown, Q1~Q6 correspond to the control of the main phase, and Q7~Q12 correspond to the control of the slave phase. It should be understood that the upper and lower switches of the same bridge arm cannot be turned on simultaneously; when one is turned on, the other switch of the same bridge arm must be turned off. Therefore, complementary drive control is adopted for the upper and lower switches of the same bridge arm. The drive on and drive off described in this application refer to the main switch (which can be customized) in the same bridge arm; complementary control of the other switch in the same bridge arm is sufficient.

[0063] Specifically, the pulse generation submodule 153 uses six zero-crossing signals to control the conduction of the master-slave carrier drive pulse. Taking the following switching transistors as the master switching transistors for pulse driving and pulse turning off as an example, the implementation can be as follows: When the master phase zero-crossing signal output by the comparator module 140 is received (equivalent to the master phase carrier zeroing moment, which is triggered in advance in this application and is not the actual zeroing moment, so it will not be elaborated), the drive signals of the lower switching transistors Q2, Q4, and Q6 corresponding to the master phase bridge arm (i.e., ...) are... Q2 Q4 Q6) is pulled high (for illustrative purposes only, not to limit the implementation), to turn on the lower switches Q2, Q4, and Q6; at the same time, the drive signals of the upper switches Q1, Q3, and Q5 corresponding to the main phase bridge arm (i.e., Q1 Q3 Q5) is pulled low to turn off the upper switches Q1, Q3, and Q5. And / or, upon receiving the zero-crossing signal of the slave phase output from comparator module 140 (which is also equivalent to the zero-crossing moment of the slave phase carrier, triggered in advance, not elaborated here), the drive signals of the lower switches Q8, Q10, and Q12 corresponding to the slave phase bridge arm are pulled low. Q8 Q10 Q12 is pulled high to turn on the lower switches Q8, Q10, and Q12; simultaneously, the drive signals of the upper switches Q7, Q9, and Q11 corresponding to the main phase bridge arm (i.e., Q12) are also turned high. Q7 Q9 Q11) is pulled low to turn off the upper switching transistors Q7, Q9, and Q11. It should be understood that in this application, pulling high means setting the drive signal to a high level, and pulling low means setting the drive signal to a low level; pulling the drive signal high corresponds to the switching transistor being turned on, and pulling it low corresponds to the switching transistor being turned off; the above correspondence between the level and the switching state is only an exemplary setting, and can be flexibly adjusted according to the hardware circuit and device type in actual applications.

[0064] Specifically, the pulse generation submodule 153, based on the master-slave interleaved carrier and the three-phase modulation signal, realizes the turn-off control of the master-slave carrier drive pulse. This can be implemented as follows: After the master / slave phase pulse is turned on, the carrier count value is determined based on the master-slave interleaved carrier. If the carrier count value of any phase (phase A, phase B, phase C) reaches the corresponding modulation signal value (as a turn-off threshold, i.e., ...), ... T a , T b , T c When the main switch is turned off, the drive pulse of the main switch is cut off. Taking the following switch as the main switch for pulse drive and pulse turn-off as an example, after the main phase / slave phase pulse is turned on, if the carrier count value of phase A reaches... Ta Then turn off the corresponding lower switches Q2 and Q8 of A (e.g., pull the drive signal low). Q2 Q8), and simultaneously turn on the upper switching transistors Q1 and Q7 (e.g., pull up the drive signal). Q1 Q7); If the B-phase carrier count reaches... T b Then turn off the corresponding lower switching transistors Q4 and Q10 of B (e.g., pull the drive signal low). Q4 Q10), and simultaneously turn on the upper switching transistors Q3 and Q9 (e.g., to pull up the drive signal). Q3 Q9); If the C-phase carrier count reaches... T c Then turn off the corresponding lower switching transistors Q6 and Q12 of C (e.g., pull the drive signal low). Q6 Q12), and simultaneously turn on the upper switching transistors Q5 and Q11 (e.g., to pull the drive signal high). Q5 Q11).

[0065] Furthermore, in one embodiment of this application, the pulse generation submodule 153 also supports dead-time insertion during pulse generation to avoid the risk of power device shoot-through, such as short circuits caused by shoot-through of the upper and lower transistors in the same bridge arm. This dead-time insertion method can be implemented by inserting a dead time at the switching edges (including rising and / or falling edges) of all or some of the switching transistors. The dead time can be flexibly configured through a register, with no limit to the adjustment range, for example, it can be 10ns to 1μs.

[0066] Taking dead-time insertion on the rising edge as an example. In one exemplary embodiment, the drive pulse is activated by a delay after the carrier counter is reset by a zero-crossing signal. This delay is the dead time of the rising edge of the switching transistor, used to prevent shoot-through between the upper and lower transistors of the same bridge arm. In this embodiment, after the carrier counter is reset by the zero-crossing signal, the drive signal is not immediately output. Instead, a preset dead time is delayed before the rising edge of the drive pulse is generated (equivalent to pulling the pulse high to activate the preset switching transistor), so that the rising edge of the drive signal appears with a set dead time delay relative to the ideal switching time. Through this rising edge delay processing, the timing of the upper and lower transistors of the same bridge arm can be effectively staggered, completely avoiding the risk of shoot-through short circuit between the upper and lower transistors, and achieving dead-time protection.

[0067] In an interleaved parallel three-phase rectifier, the direction of inductor current flow differs for different sectors. For example, if the inductor currents of phases A and C are in the positive half-cycle in sector 1 (0~30°), then for phases A and C, the lower switch transistors of the same bridge arm (e.g., Q2, Q8 corresponding to A; Q6, Q12 corresponding to C) are the main switches, corresponding to the main pulse (conducting), while the upper switch transistors of the same bridge arm (e.g., Q1, Q7 corresponding to A; Q5, Q11 corresponding to C) are the auxiliary switches, corresponding to the auxiliary pulse (turning off). However, in sector C (180°~210°), the inductor currents of phases A and C are in the negative half-cycle. At this time, the upper switch transistors of the same bridge arm (e.g., Q1, Q7 corresponding to A; Q5, Q11 corresponding to C) are the main switches, corresponding to the main pulse (conducting), while the lower switch transistors of the same bridge arm (e.g., Q2, Q8 corresponding to A; Q6, Q12 corresponding to C) are the auxiliary switches, corresponding to the auxiliary pulse (turning off). In this case, the present application uses the pulse output submodule 154 to dynamically output a set of drive signals corresponding to each bridge arm, in combination with the current operating sector of the rectifier and the polarity of the inductor current, so as to ensure that the drive pulse matches the current direction and ensures the stable and orderly operation of the rectifier circuit.

[0068] like Figure 5 As shown, the pulse output submodule 154 can have multiple sub-units, each corresponding to a bridge arm, used to distribute a set of drive signals to the corresponding switching transistor of that bridge arm. For example, Figure 5 The pulse output submodule 154 in the middle can be used to output pulse signals. Q1 and Q2 is assigned to the upper and lower switching transistors Q1 and Q2 corresponding to the same bridge arm, which is used to realize the distribution of pulse signals within the bridge arm.

[0069] In a specific scenario, the pulse output submodule 154 can have a built-in 12×2-dimensional lookup table (i.e., a lookup table) between 12 sectors and two current polarities. This table can pre-set the correspondence between sectors, current polarities, and main and auxiliary pulses. Therefore, the pulse output submodule 154 can determine the main and auxiliary pulses by looking up the table and dynamically output them. In one exemplary embodiment, the pulse output submodule 154 is specifically used to: determine the main and auxiliary pulses of the 12 drive pulses based on the current sector and current polarity, and dynamically output them.

[0070] For easier understanding, please refer to the following: Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of one operating mode of the pulse output submodule provided in an embodiment of this application. Figure 8 This is a schematic diagram illustrating another operating mode of the pulse output submodule provided in an embodiment of this application. For example... Figure 7As shown, when the inductor current is positive, the drive pulse of the lower switch transistor in the corresponding bridge arm is defined as the main pulse and directly output. At this time, the main pulse acts on the lower bridge arm switch transistor, and the drive current flows along the positive half-cycle path. No additional processing is required; the drive pulse can be directly output according to the corresponding switch transistor. For example... Figure 8 As shown, when the inductor current is negative, the drive pulse of the upper switch transistor of the corresponding bridge arm is defined as the main pulse, and the drive channel output is switched. If the main pulse definition used when the current is positive were still applied, the drive pulses of the upper and lower switches of the bridge arm would not match the current direction. Therefore, the output channel of the drive signal needs to be switched to ensure that the drive pulses of the master-slave phase switches Q1~Q12 are strictly matched with the current direction, guaranteeing that the rectifier can operate stably and orderly during both the positive and negative half-cycles of the current. Based on this working mechanism, the pulse output submodule 154 can also be called the pulse commutation submodule; there are no particular restrictions on the name.

[0071] In addition, in one possible embodiment, the pulse generation module 150 provided in this application may also include, but is not limited to: a clamping processing submodule, used to compare the three-phase modulation signal with the carrier maximum value of the corresponding phase, and when the modulation signal of a certain phase is greater than the corresponding carrier maximum value, to control the corresponding switch to remain on according to the current polarity to achieve clamping; wherein, if the polarity of the inductor current is positive, the corresponding switch is the lower switch of the corresponding bridge arm; if the polarity of the inductor current is negative, the corresponding switch is the upper switch of the corresponding bridge arm.

[0072] In this context, clamping refers to the process where, when the amplitude of the modulated signal exceeds (i.e., is greater than) the maximum carrier value (PRD), conventional carrier modulation is no longer performed. Instead, the on / off state of the corresponding switch is locked based on the current polarity, ensuring that the corresponding switch remains either on or off (its state remains unchanged). Specifically, if the inductor current is positive (i.e., the positive half-cycle), the lower switch of the corresponding bridge arm remains on; if the inductor current is negative (i.e., the negative half-cycle), the upper switch of the corresponding bridge arm remains on. This clamping protection ensures stable output voltage and guarantees smooth rectifier operation.

[0073] In addition, in one possible embodiment, the pulse generation module 150 provided in this application may also include, but is not limited to, a pulse blocking submodule, used to block the driving pulse of the corresponding phase when the zero-crossing signal triggers conduction, until the next carrier cycle.

[0074] In this application, the six zero-crossing signals output by the comparator module 140 can be used for CRM control and DCM control. As mentioned above. Figure 4As shown, this application sets the programmable threshold (also called the comparison threshold) to a positive value higher than zero potential; thus, when the inductor current drops to the threshold, the comparator module 140 undergoes a low-level to high-level transition, forming a rising edge of the zero-crossing signal. This signal serves as the trigger signal for clearing the CRM phase carrier, which triggers the normal conduction of the switching transistor to realize the CRM control function described above, which will not be repeated here.

[0075] Furthermore, since the programmable threshold is generally set to a positive value close to zero, when the comparator module 140 outputs a zero-crossing signal (rising edge), it means that the inductor current is already very close to zero and is continuously decreasing. In DCM mode, this poses a risk of reverse current flow. If the switching transistor remains on at this time, the inductor current will cross the zero potential and become negative, causing current waveform distortion, a decrease in power factor, and voltage oscillations and spikes across the power device, threatening device safety and disrupting normal control timing. Therefore, the pulse blocking submodule in this application will immediately block (i.e., turn off) the drive pulse of the corresponding phase when it detects the rising edge of the zero-crossing signal, regardless of whether the current carrier count value has reached the turn-off threshold corresponding to the three-phase modulation signal, and maintain the blocked state until the start of the next carrier cycle. This turns off the switching transistor in advance before the current completely crosses zero, avoids reverse current generation, and ensures the safe and stable operation of the rectifier in DCM mode.

[0076] Please refer to Figure 9 , Figure 9 This is a schematic diagram illustrating the operating status of each sector within one power frequency cycle, provided as an embodiment of this application. For example... Figure 9 As shown, the inductor current of this three-phase rectifier can be divided into three operating modes within one power frequency cycle: DCM state, CRM state, and clamping state. In the clamping state, the inductor current cannot naturally return to zero. This is based on the three-phase modulation signal (which can be denoted as...). T a , T b , T cIn different sectors of the power frequency cycle, phases A, B, and C operate in DCM, CRM, or clamping states respectively, based on the amplitude and phase relationship of the three-phase modulation signals. The state switching of each phase cycles periodically with the three-phase modulation signals. Based on this, comparator module 140 can independently output corresponding zero-crossing signals for each phase, and each zero-crossing signal can be differentiated according to the real-time operating conditions of each phase. Taking sector 1 as an example, for phase C in CRM state, the rising edge of its zero-crossing signal can trigger the lower switch of the corresponding bridge arm of phase C to turn on, causing the inductor current to rise; while for phase A in DCM state, the rising edge of its zero-crossing signal can trigger pulse blocking of phase A, preventing the current from continuing to decrease. Relying on this differentiation logic, independent control can be performed on different phases within the same sector, adapting to the operating conditions of multi-phase differentiated operation.

[0077] In summary, the pulse generation module 150 provided in this application embodiment can complete functions such as master-slave 180° interleaved carrier generation, 12-sector division, drive pulse generation, and dead-time insertion within the same power frequency cycle, with the current of each phase in each sector exhibiting a different state. Thus, this application, through phase-differentiated control logic, can adapt to different operating modes of each phase, avoid problems such as reverse current and voltage oscillation, optimize output waveform quality, and improve current control stability.

[0078] In one embodiment of this application, such as Figure 1 As shown, the signal processing module 110 may include an analog filtering submodule 111 and a sampling processing submodule 112. The analog filtering submodule 111 is used to acquire three-phase inductor currents and perform analog filtering on the three-phase inductor currents; the sampling processing submodule 112 is used to sample the three-phase line voltages and the filtered three-phase inductor currents.

[0079] In this embodiment, the analog filtering submodule 111 can be implemented using a built-in multi-order RC filter network (e.g., a Sallen-Key active filter network, switched via a chip configuration register depending on the application scenario). This module can be integrated inside the chip, eliminating the need for external filtering circuits and effectively reducing the number of external pins. The analog filtering submodule 111 can be configured with an enable control register (address 0x01, bit0). When this bit is configured as "1", the analog filtering submodule 111 is enabled, performing anti-high-frequency filtering on the six-channel inductor current sampling signals of the main / slave phases, converting pulse current signals containing high-frequency noise into smooth sinusoidal sampling signals, thus avoiding high-frequency noise interference with subsequent AD sampling accuracy. When configured as "0", the analog filtering submodule 111 is bypassed, and the sampling signal directly enters the AD sampling module, adapting to special application scenarios that do not require filtering. For example, this disclosure also provides a possible configuration of filter network parameters: for a 50Hz / 60Hz three-phase power frequency system, the filter cutoff frequency can be set to 1kHz, and the order of the multi-order RC network can be 4th order. In this way, high-frequency interference above 20kHz can be effectively attenuated, ensuring that the distortion of the output sinusoidal sampling signal is ≤1%. It should be understood that this parameter configuration data is not intended to limit this application.

[0080] The sampling processing submodule 112 can first receive six analog inductor current signals, three analog output voltage signals, and three analog three-phase line voltage signals processed by the analog filtering submodule 111. Then, through analog-to-digital conversion, the above analog signals are converted into digital signals (conversion accuracy is unlimited, for example, it can be less than or equal to ±1 LSB). Finally, the converted digital signals are sent to the loop control module 130 and the phase-locked loop 120 respectively via the internal data bus for subsequent processing, as described above. In practical scenarios, the sampling processing submodule 112 can be implemented using a 12-bit successive approximation AD converter (sampling rate is unlimited, for example, it can be 1 MHz), without exhaustive or limited options.

[0081] In one embodiment of this application, the phase-locked loop 120 is used to determine the angle based on the three-phase line voltage. This module can be designed using a pure algorithm embedded within the loop, without the need for an external phase-locked loop circuit. First, the three-phase line voltage (i.e., the sampling and processing submodule 112 mentioned above) can be acquired through the AD sampling module (i.e., the sampling and processing submodule 112 mentioned above). U ab , U bc , U caThe analog signal is converted into a digital signal and input into the phase-locked loop 120. The phase-locked loop 120 can perform phase detection and angle calculation based on the extracted phase information to determine the angle in real time (range 0°~360°). Phase detection can be performed using, but is not limited to, a zero-crossing detection algorithm combined with a digital phase-locked loop algorithm to extract the phase of the three-phase line voltage signal, eliminate voltage harmonic interference, and obtain accurate phase information. The phase-locked loop 120 can output the angle to the loop control module 130 (for three-phase modulation signal generation) and the pulse generation module 150 (for sector determination), as described above.

[0082] In one embodiment of this application, the loop control module 130 may include: a voltage loop submodule 131, a current generation submodule 132, and a current loop module 133. The voltage loop submodule 131 is used to determine a reference value for the three-phase peak current based on the difference between the three-phase line voltage and the target voltage value; the current generation submodule 132 is used to generate a current reference signal with a 120° phase difference based on the angle and the reference value; and the current loop module 133 is used to generate and output a three-phase modulation signal based on the difference between the current reference signal and the three-phase inductor current.

[0083] The differences described in this embodiment (such as the difference between the three-phase line voltage and the voltage target value, the difference between the current reference signal and the three-phase inductor current, etc.) can be quantitatively characterized by one or more methods such as voltage difference, phase offset, harmonic distribution difference, and similarity between the two. This application has no particular limitation on this.

[0084] You can refer to this. Figure 10 , Figure 10 This is a schematic diagram illustrating the principle of a loop control module provided in an embodiment of this application. Figure 10 In the illustrated embodiment, the input to the voltage loop submodule 131 is the output voltage. V dc With voltage target value V dc_ref The output voltage can be obtained by acquiring the output voltage of the external power converter through the AD sampling module (i.e., the sampling processing submodule 112 mentioned above); while the target voltage value can be obtained through register configuration, with a typical range of 0~5V and unlimited accuracy, for example, 1mV. The voltage loop submodule 131 will... V dc and V dc_ref The difference is used as the input to the voltage loop PI controller, and after PI calculation, the three-phase peak current reference is obtained. I peak_refIn this disclosure, the internal operational parameters of the voltage loop submodule 131 can be configured through registers and can be dynamically adjusted online. For example, the proportional coefficient Kp can range from 0.1 to 10, and the integral coefficient Ki can range from 0.01 to 1, which will not be elaborated further.

[0085] like Figure 10 As shown, the output of voltage loop submodule 131 (i.e., the three-phase peak current reference) I peak_ref ) can be used for current reference signals (i.e. I a_ref , I b_ref , I c_ref The current generation submodule 132 can receive the angle output from the phase-locked loop 120. Thetα ), so as to be based on Thetα Construct three sinusoidal current reference signals with a phase difference of 120°. The current reference signals, angles, and reference values ​​of the three-phase peak currents can satisfy the following relationship: I a_ref = I peak_ref ×sin( Thetα ), I b_ref = I peak_ref ×sin( Thetα -120°), I c_ref = I peak_ref ×sin( Thetα +120°).

[0086] Finally, the current loop submodule 133 is based on the current reference signal (i.e. I a_ref , I b_ref , I c_ref ) and three-phase inductor current (i.e. i a1 , i b1 , i c1 ), determine the three-phase modulation signal (i.e. T a , T b , T cSpecifically, the current loop submodule 133 can calculate the difference between the corresponding current reference signal and the inductance signal, and use the difference as the input of the current loop PI controller to perform calculations and output a three-phase modulated signal.

[0087] This embodiment supports flexible configuration and switching of control algorithms and control targets. Specifically, through the chip configuration register (address 0x02, bits 1~0), the voltage loop PI and current loop PI can be replaced entirely or partially with various control algorithms such as PR control, hysteresis control, or model predictive control. Furthermore, through the control target selection register (address 0x02, bit 2), the system control target can be changed from output voltage... V dc It switches to output current to adapt to the control requirements of different application scenarios such as constant voltage output and constant current output.

[0088] In summary, this application obtains the three-phase inductor current and three-phase line voltage of the main phase through a signal processing module. The phase-locked loop (PLL) determines the current phase angle based on the above signals. The loop control module generates a three-phase modulation signal by combining the three-phase inductor current, output voltage, and phase angle. The comparator module can directly output six zero-crossing signals by comparing the six inductor currents of the main and slave phases with the built-in programmable threshold. This application abandons the traditional CRM control method that uses the inductor current returning to zero as the trigger condition, and instead triggers the generation of zero-crossing signals when the inductor current reaches the programmable threshold. This initiates CRM control, thus preventing inductor current reversal at its source. Furthermore, the pulse generation module generates master-slave interleaved carriers with a 180° phase difference based on the primary phase zero-crossing signal, and outputs 12 drive pulses in conjunction with relevant signals. The drive pulses employ a control logic of "zero-crossing signal triggers counter clearing to achieve conduction, and count value reaches set threshold to turn off," ensuring that the inductor current operates stably in the critical conduction state, effectively suppressing current backflow, realizing CRM control of the interleaved parallel three-phase rectifier, and significantly improving the stability of current control.

[0089] This application also provides a control chip, which may include the control circuit 100 provided in any of the preceding embodiments of this application, which will not be described in detail here.

[0090] This application also provides a control method for an interleaved parallel three-phase rectifier. Please refer to [reference needed]. Figure 11 , Figure 11 This is a flowchart illustrating a control method for an interleaved parallel three-phase rectifier provided in an embodiment of this application. Figure 11 As shown, the method includes: S1102 obtains the three-phase inductor current, three-phase line voltage and output voltage of the main phase.

[0091] This step can be viewed as a signal acquisition and preprocessing process. In specific scenarios, it can be implemented through the signal processing module 110 and its internal processing logic, as described above.

[0092] S1104 determines the angle based on the three-phase line voltage.

[0093] As mentioned earlier, this step can be implemented using the phase-locked loop 120 and its internal processing logic, which will not be elaborated upon further as previously described.

[0094] S1106 determines the three-phase modulation signal based on the three-phase inductor current, output voltage, and angle.

[0095] As mentioned earlier, this step can be implemented through the loop control module 130 and its internal processing logic, which will not be elaborated upon further as previously stated.

[0096] The S1108 outputs six zero-crossing signals based on the six inductor currents of the master and slave phases and the built-in programmable threshold.

[0097] As mentioned earlier, this step can be implemented through comparator module 140 and its internal processing logic, which will not be repeated here.

[0098] S1110 generates master-slave interleaved carriers with a phase difference of 180° based on the master phase zero-crossing signal.

[0099] As mentioned earlier, this step can be implemented by the carrier generation submodule 152 in the pulse generation module 150 and its internal processing logic, which will not be repeated here.

[0100] S1112 generates and outputs 12 drive pulses based on master-slave interleaved carriers, three-phase modulation signals, angles, and six zero-crossing signals. The drive pulses are turned on by the zero-crossing signal triggering the carrier counter to be cleared, and turned off by the carrier count value reaching the turn-off threshold corresponding to the three-phase modulation signal.

[0101] As mentioned earlier, this step can be implemented by the pulse generation module 150. For example, the pulse generation submodule 153 and the pulse output submodule 154 can work together to implement the control logic of "zero-crossing signal triggers counter to clear and conduct, count value reaches threshold and turns off", so that the inductor current works stably in the critical conduction state, effectively suppressing reverse current flow and ensuring the stability of current control. This can also be referred to in the previous text and will not be repeated here.

[0102] In real-world scenarios, the aforementioned control method can detect and adjust in real time. For example, in this application, the signal processing module 110 can continuously acquire signals, and the phase-locked loop 120 updates the angle in real time. The loop control module 130 dynamically adjusts the three-phase modulation signal, the comparator module 140 also works in real time to output six zero-crossing signals, and the pulse generation module 150 optimizes the drive pulse in real time based on the latest signal to ensure that the three-phase inductor current remains in a critical conduction state and prohibits reverse flow, thus ensuring the stability of current control during the CRM process of the interleaved parallel three-phase rectifier.

[0103] In one exemplary embodiment, S1112 can be implemented as follows: determining the current sector based on the angle; generating a master-slave interleaved carrier with a phase difference of 180° based on the master-slave interleaved carrier, the three-phase modulation signal, and the six zero-crossing signals; generating 12 driving pulses based on the master-slave interleaved carrier, the three-phase modulation signal, and the six zero-crossing signals; thereby, dynamically outputting 12 driving pulses based on the current sector and the current polarity, so that the 12 driving pulses match the current direction.

[0104] In one exemplary embodiment, the conduction of the drive pulse can be generated by a delay after the carrier counter is cleared by a zero-crossing signal. This delay is the dead time of the rising edge of the switching transistor, which is used to prevent the upper and lower transistors of the same bridge arm from shoot-through.

[0105] In one exemplary embodiment, the master-slave carrier generation can be implemented as follows: at the rising edge of the master phase zero-crossing signal, the master carrier counter is cleared to zero and the master carrier is generated, and the master carrier period is recorded; half of the master carrier period is used as the initial value of the slave carrier counter to generate the slave carrier.

[0106] In one exemplary embodiment, the dynamic output of 12 drive pulses can be processed as follows: based on the current sector and current polarity, the main and auxiliary pulses of the 12 drive pulses are determined by looking up a table and dynamically output. Thus, when the inductor current is positive, the drive pulse of the lower switch of the corresponding bridge arm is defined as the main pulse and directly output; when the inductor current is negative, the drive pulse of the upper switch of the corresponding bridge arm is defined as the main pulse and the drive channel is switched for output.

[0107] In one exemplary embodiment, the method may further include the following processing: blocking the driving pulse of the corresponding phase when the zero-crossing signal triggers conduction, until the next carrier cycle.

[0108] In one exemplary embodiment, the method may further include the following processing: comparing the three-phase modulation signal with the maximum value of the carrier wave of the corresponding phase, and when the modulation signal of a certain phase is greater than the maximum value of the corresponding carrier wave, controlling the corresponding switch to remain on according to the current polarity to achieve clamping; wherein, if the polarity of the inductor current is positive, the corresponding switch is the lower switch of the corresponding bridge arm; if the polarity of the inductor current is negative, the corresponding switch is the upper switch of the corresponding bridge arm.

[0109] In one exemplary embodiment, S1108 can be implemented as follows: The six inductor currents of the master and slave phases are subjected to analog low-pass filtering to obtain six filtered currents; the six filtered currents are compared with a built-in programmable threshold to obtain digital level signals; wherein, if the filtered current is greater than the built-in programmable threshold, the digital level signal of the corresponding channel is low; if the filtered current is less than the built-in programmable threshold, the digital level signal of the corresponding channel is high; the digital level signals are subjected to digital filtering to obtain six zero-crossing signals.

[0110] In one exemplary embodiment, S1102 can be implemented as follows: acquiring the three-phase inductor current and performing analog filtering on the three-phase inductor current; and sampling the output voltage, the three-phase line voltage and the filtered three-phase inductor current.

[0111] In one exemplary embodiment, S1106 can be implemented as follows: determining a reference value for the three-phase peak current based on the difference between the output voltage and the target voltage value; generating a current reference signal with a phase difference of 120° based on the angle and the reference value; and generating and outputting a three-phase modulation signal based on the difference between the current reference signal and the three-phase inductor current.

[0112] In one exemplary embodiment, the method further includes: after the chip is powered on, configuring pre-configured parameters of each module register, the pre-configured parameters including one or more of the following: analog filter module enable state, voltage loop sub-module parameters, current loop sub-module parameters, dead time, built-in programmable threshold, and voltage target value. In practical scenarios, the configuration process of the pre-configured parameters of each module register can be implemented during the system initialization phase after the chip is powered on.

[0113] Referring to the previous text, I will not repeat it again.

[0114] This application also provides an electronic device. The electronic device according to this application includes at least a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the control method described in any of the above embodiments.

[0115] In one exemplary embodiment, the electronic device may specifically include a central processing unit (CPU), a graphics processing unit (GPU), and memory. These units are interconnected via a bus. The CPU and / or GPU can serve as the processors described above, and the memory can serve as the storage for computer-readable instructions. Furthermore, the electronic device may also include communication units, storage units, output units, input units, and external devices, which are also connected to the bus.

[0116] This application also provides a computer-readable storage medium. The computer-readable storage medium according to this application stores a computer program / instruction (including but not limited to computer-readable instructions). Specifically, the computer-readable storage medium stores computer-readable instructions. When the computer program / instruction is executed by a processor, it implements the control method described in any of the preceding embodiments of this application. The computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0117] This application further provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the control method described in any of the preceding embodiments of this application.

[0118] This application also provides a charging pile. Figure 12 A structural block diagram of a charging pile provided in an embodiment of this application is shown below. Figure 12 As shown, the charging pile 1200 includes: an AC filter 1210, a control circuit 100 of any of the above embodiments, a rectifier bridge 1220, a bus capacitor 1230, and a DC converter 1240.

[0119] Among them, the AC filter 1210 (i.e., LCL filter, which can be referred to in the previous text) Figure 2 (and its description), connected to the power grid input, used to filter the input AC power; the control circuit 100 of any of the above embodiments is used to control the rectification process; the rectifier bridge 1220, connected to the AC filter 1210 and the control circuit 100, is used to convert the filtered AC power into DC power; the bus capacitor 1230, connected to the rectifier bridge 1220, is used to stabilize the DC bus voltage; the DC converter 1240 (which can be referred to as DC-DC), connected to the bus capacitor 1230, is used to output DC power.

[0120] It should be understood that in some embodiments, the control circuit 100 in the charging pile 1200 can also be replaced by a control chip (also called a CRM control chip), which includes the control circuit 100 described in any of the foregoing embodiments of this application, and will not be described in detail here.

[0121] For details not covered, please refer to the preceding text. Figure 1 , Figure 2 For related explanations, please refer to the previous text for the specific implementation scheme of the control circuit 100 / control chip, which will not be repeated here.

[0122] To facilitate understanding, the working mechanism of this charging station is briefly explained below. The charging station can operate in standby mode, constant current charging mode, constant voltage charging mode, and shutdown mode. This is now combined with... Figure 2 and Figure 12 Detailed explanation.

[0123] In the first operating scenario, the charging station can be in standby mode. At this time, the charging station is neither charging nor discharging, and is in a low-power standby state.

[0124] In standby mode, such as Figure 2 As shown, the input of the AC filter 1210 is a three-phase line voltage (380V AC), and its direct input filter inductor (i.e. L ga , L gb , L gc The filter inductor is in an unloaded energized state, with only a small no-load current flowing through it, suppressing instantaneous voltage spikes and background harmonics from the grid side from entering the rectifier side. The filter capacitor (i.e....) C g The voltage across the rectifier bridge stabilizes near the peak voltage of the mains line (approximately 537V), bypassing high-frequency noise from the mains side while providing weak voltage support. Meanwhile, the inductor on the rectifier side (i.e., L 1a , L 1b , L 1c and L 2a , L 2b , L 2c No obvious current flows through it, and it is in standby hibernation mode.

[0125] In standby mode, in control circuit 100, signal processing module 110 acquires the three-phase line voltage (i.e., U ab , U bc , U ca DC bus voltage (i.e.) V dc ), and monitor the inductor current of the master and slave phases of the rectifier bridge ( i a1 , i b1 , i c1 and i a2 , i b2 , i c2At this point, the current is close to zero. The phase-locked loop 120 then calculates the grid voltage phase angle. Thetα The system tracks the grid frequency and phase in real time to prepare for subsequent charging startup. In the pulse control section (implemented by the loop control module 130, comparator module 140, and pulse generation module 150), the output pulse duty cycle is extremely low, maintaining only the minimum drive of the rectifier bridge; simultaneously, it triggers the DCM mode pulse blocking function to prevent inductor current backflow and additional losses. Furthermore, in standby mode, it continuously monitors the bus voltage and current to ensure no faults occur during standby.

[0126] In standby mode, the power devices (SiCMOSFETs / IGBTs) of the master phase (Q1-Q6) and slave phase (Q7-Q12) of the rectifier bridge 1220 are in a low-frequency micro-conduction state, with the switching frequency far below the rated value (e.g., 1kHz vs 20kHz rated). The master-slave phase carrier synchronization logic is also in standby mode, with the carrier period PRD maintained at its maximum value to ensure the lowest possible power device losses.

[0127] At this time, the bus capacitance is 1230, that is... Figure 2 shown C 1. C 2. C O In this state, the capacitor is in a voltage-stabilized energy storage state, maintaining the voltage across its terminals at the lower limit of the rated bus voltage (e.g., 500V). This counteracts the small pulsating DC output of the rectifier bridge and suppresses bus voltage ripple. During this stage, the capacitor leakage current is extremely small, discharging slowly through its internal parasitic resistance. The CRM control chip monitors voltage changes to prevent undervoltage.

[0128] The DC-DC converter 1240 is a bidirectional DC-DC module, which is also in standby lockout mode at this time. The power switching transistors are off, and only the control board is energized. The connection port with the power battery is in a high-impedance state to prevent reverse discharge of the battery. However, the communication module of the DC-DC converter 1240 remains awake to receive charging commands from the charging pile's main control unit.

[0129] In the second operating scenario, the charging pile can be in a constant current charging state. At this time, the charging pile outputs a constant large current, the system works in CRM mode, the energy transmission efficiency is the highest, the power battery is fast charged, and this is also the core power transmission stage of the charging pile.

[0130] Under constant current charging conditions, for AC filter 1210, the filter inductance on the grid side (i.e., L ga , L gb , L gcThis hinders the conduction of high-frequency switching harmonics (20kHz) generated by the rectifier bridge 1220 to the power grid. At high frequencies, it exhibits high impedance, forcing the harmonic current to flow to the filter capacitor (i.e., C g The filter capacitor exhibits low impedance to 20kHz high-frequency harmonics, bypassing most of the harmonic current and dissipating it in the filter (i.e., LC) circuit, preventing it from being injected into the power grid. The inductor on the rectifier side (i.e....) L 1a , L 1b , L 1c and L 2a , L 2b , L 2c The inductor then participates in the charging and discharging of the inductor current in CRM mode. Specifically, when the pulse is turned on, the current rises linearly (energy storage), and when the pulse is turned off, the current drops linearly to zero (energy release), with no discontinuity. Furthermore, the inductor on the rectifier side also smooths the input current waveform of the rectifier bridge, working with the control circuit 100 to ensure that the current is in phase with the grid voltage, achieving a power factor PF ≥ 0.995. In addition, the control circuit 100 / control chip can also detect the filter's resonance characteristics in real time, finely adjust the rectifier bridge switching frequency, avoid the inherent resonant point of the LCL, and prevent current resonance.

[0131] In constant current charging mode, control circuit 100 / control chip can be used to implement master-slave phase interleaving switching, that is, the master phase (Q1-Q6) and slave phase (Q7-Q12) are switched at high frequency (20kHz) according to the pulse timing output by control circuit 100 / control chip, with a switching phase difference of 180° to cancel current ripple. Figure 9 Taking sector 1 as an example, the CRM control mode is briefly explained. Specifically, when the carrier is cleared, Q2 / Q4 / Q6 (i.e., the main phase switching transistors) and Q8 / Q10 / Q12 (the slave phase switching transistors) are turned on, and current flows from the grid through the LCL filter into the rectifier bridge 1220, where the inductor stores energy; when the carrier count reaches the turn-off threshold corresponding to the three-phase modulation signal (i.e., ... T a , T b , T cWhen the current drops to the built-in programmable threshold of the comparator module 140, the lower switch of the master and slave phases is turned off and the upper switch is turned on, the inductor releases energy, and the current flows to the DC bus. When the inductor current drops to the built-in programmable threshold of the comparator module 140, the comparator module 140 outputs a zero-crossing signal, triggering the master phase carrier to be cleared and entering the next switching cycle. In this process, this application also configures protection logic for power devices, such as dead-time insertion (i.e., inserting a dead time to prevent the upper and lower switches from being shot-through short-circuited) and DCM phase pulse blocking (i.e., when there is an overcurrent, the chip immediately blocks the pulse and cuts off the energy transfer).

[0132] In constant current charging mode, the rectifier bridge 1220 outputs pulsating DC (including 20kHz switching ripple and 100Hz power frequency ripple). The bus capacitor 1230 presents low impedance to the ripple, smoothing the bus voltage and achieving ripple suppression with a ripple factor ≤1%. Furthermore, when the output power of the rectifier bridge 1220 fluctuates instantaneously, the bus capacitor 1230 can absorb excess energy or release energy to replenish it, ensuring a stable bus voltage (e.g., 750V), thus achieving voltage stabilization. In addition, the control circuit 100 / control chip can monitor the voltage of the three bus capacitors 1230, ensuring voltage balance through a voltage equalization circuit and preventing damage from overvoltage of a single capacitor.

[0133] During constant current charging, the DC-DC converter 1240 switches to buck mode (if the bus voltage of 750V is higher than the battery voltage of 400V) or boost mode (if the battery voltage is higher than the bus voltage) to achieve precise voltage matching. Furthermore, the DC-DC converter 1240 can also receive a current reference signal from the control circuit 100 / control chip (i.e.,...). I a_ref , I b_ref , I c_ref The inverter adjusts the duty cycle of the power switching transistor through its own current loop PI regulator to output a constant current to the power battery. If V2G (vehicle-to-grid) is supported, it can switch to boost inverter mode at any time to feed battery energy back to the grid, but it is not used during the constant current charging stage, thus achieving bidirectional energy preparation.

[0134] In the third operating scenario, the charging station can be in a constant voltage charging state. During this stage, the battery voltage gradually rises to the rated value, approaching full charge. The charging station maintains a constant output voltage, and the current gradually decreases. The system transitions from CRM mode to DCM mode.

[0135] Under constant voltage charging conditions, for AC filter 1210, the filter inductance on the grid side (i.e., L ga , L gb , L gcThe main function of the inductor on the rectifier side is to suppress grid voltage fluctuations and prevent voltage spikes from impacting the rectifier bridge. L 1a , L 1b , L 1c and L 2a , L 2b , L 2c The current flows intermittently, reducing the charge-discharge time ratio. This enhances the voltage support of the filter capacitor, offsetting voltage fluctuations caused by the reduced current.

[0136] During constant voltage charging, loop control switching occurs in control circuit 100 / control chip, i.e., the voltage loop PI priority is increased to maintain a constant bus voltage; the modulation signal output by the current loop PI (i.e. T a , T b , T c The duty cycle gradually decreases. Furthermore, in this state, a noticeable discontinuity occurs after the inductor current drops to zero. The comparator module 140 triggers a DCM mode pulse blockade, shutting off the corresponding phase's power device drive pulse to prevent current backflow. The phase angle (i.e., Thetα The tracking accuracy remains unchanged, but the carrier period PRD increases as the current decreases, so the switching frequency is reduced to reduce losses.

[0137] Under constant voltage charging conditions, the switching frequency of the master and slave phases of the interleaved parallel rectifier bridge 1220 is reduced (e.g., to 10kHz), and the power devices in some phases enter an intermittent operating state, maintaining only the necessary energy transfer. In DCM mode, the pulse blocking logic takes effect, and the circuit does not immediately turn on after the current crosses zero, reducing switching losses.

[0138] Under constant voltage charging conditions, the voltage of bus capacitor 1230 remains constant, and the ripple coefficient is further reduced; the capacitor charging and discharging frequency decreases as the rectifier bridge switching frequency decreases, thus reducing losses.

[0139] During constant voltage charging, the DC-DC converter 1240 employs constant voltage control, switching to voltage loop PI priority to maintain the output voltage consistent with the battery's rated voltage, while the current decreases as the battery's state of charge (SOC) increases. Furthermore, the DC-DC converter 1240 performs pre-shutdown preparation, i.e., it relays the battery's full charge status to the main control unit via the communication module, awaiting a shutdown command.

[0140] In the fourth operating scenario, the charging station can be in a shutdown state. At this time, charging is complete, and all modules within the charging station are shut down in an orderly manner.

[0141] In the shutdown state, the control circuit 100 / control chip receives the shutdown command from the main control unit and gradually reduces the modulation signal duty cycle to zero. In addition, pulse blocking is implemented, i.e., a full-bridge pulse blocking command is issued to shut down all rectifier bridge power devices; the phase-locked loop 120 stops working and enters standby mode. Furthermore, the control circuit 100 / control chip can continuously monitor the status, i.e., continuously monitor the bus voltage and current, and after ensuring there are no faults, the control board enters a low-power mode.

[0142] In the shutdown state, all power devices in the interleaved parallel rectifier bridge 1220 are turned off, and the AC-DC energy transmission path is cut off. Meanwhile, the filter capacitor of the AC filter 1210 (i.e., C g The voltage gradually drops back to the grid voltage level through the parasitic resistance of the grid-side inductor and the rectifier-side inductor. Bus capacitor 1230 discharges slowly through the bidirectional DC-DC bleeder circuit, reducing the voltage to a safe value (e.g., below 100V). Control circuit 100 / control chip continues to monitor the voltage to prevent overvoltage discharge. DC-DC converter 1240 (i.e., bidirectional DC-DC) disconnects from the power battery and switches to standby lockout mode; if it supports V2G, it can wait for a reverse discharge command; otherwise, it maintains low power consumption.

[0143] In summary, the charging pile provided in this application embodiment, relying on the aforementioned pulse generation and multi-condition collaborative control circuit, can smoothly switch between different operating states such as standby, constant current charging, constant voltage charging, and shutdown. Through the control circuit 100 / control chip, master-slave 180° interleaved carrier, 12-sector partitioning, and DCM / CRM / clamping phase-differentiated control are achieved, enabling precise generation and dead-time insertion of drive pulses. This avoids reverse inductor current flow and voltage spikes, optimizes current waveform quality, and significantly improves power factor and energy conversion efficiency. Furthermore, this application can adapt to multi-phase differentiated operation requirements, reduce device losses and harmonic interference, and ensure the charging pile operates safely, efficiently, and stably under all operating conditions.

[0144] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0145] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0146] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0147] It should also be noted that in the system and method of this application, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of this application.

[0148] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this application is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0149] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0150] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A control circuit for an interleaved parallel three-phase rectifier, characterized in that, include: The signal processing module is used to acquire the three-phase inductor current, three-phase line voltage and output voltage of the main phase; A phase-locked loop, connected to the signal processing module, is used to determine the angle based on the three-phase line voltage; A loop control module, connected to the signal processing module and the phase-locked loop, is used to determine the three-phase modulation signal based on the three-phase inductor current, the output voltage, and the angle. The comparator module is used to output six zero-crossing signals based on the six inductor currents of the master and slave phases and the built-in programmable threshold. The pulse generation module, connected to the loop control module, the phase-locked loop, and the comparator module, is used to generate master-slave interleaved carriers with a phase difference of 180° based on the master-phase zero-crossing signal, and to generate and output 12 drive pulses based on the master-slave interleaved carriers, the three-phase modulation signal, the angle, and the six zero-crossing signals; wherein, the conduction of the drive pulses is generated by the zero-crossing signal triggering the carrier counter to be cleared, and the deactivation is generated by the carrier counter value reaching the deactivation threshold corresponding to the three-phase modulation signal.

2. The control circuit according to claim 1, characterized in that, The pulse generation module includes: The sector determination submodule is used to determine the current sector based on the angle. The carrier generation submodule is used to generate the master-slave interleaved carrier with a phase difference of 180° based on the master phase zero-crossing signal and the current sector; A pulse generation submodule, connected to the carrier generation submodule, is used to generate the 12 drive pulses based on the master-slave interleaved carrier, the three-phase modulation signal, and the six zero-crossing signals; The pulse output submodule, connected to the pulse generation submodule and the sector determination submodule, is used to dynamically output the 12 drive pulses based on the current sector and current polarity, so that the 12 drive pulses match the current direction.

3. The control circuit according to claim 2, characterized in that, The drive pulse is activated by a delay after the carrier counter is reset by the zero-crossing signal. The delay is the dead time of the rising edge of the switching transistor, which is used to prevent shoot-through between the upper and lower transistors of the same bridge arm.

4. The control circuit according to claim 2, characterized in that, The carrier generation submodule is specifically used for: At the rising edge of the primary phase zero-crossing signal, the primary carrier counter is cleared to zero and the primary carrier is generated, and the primary carrier period is recorded; A slave carrier is generated by using half of the master carrier period as the initial value of the slave carrier counter.

5. The control circuit according to claim 2, characterized in that, The pulse output submodule is specifically used to: determine the main and auxiliary pulses of the 12 drive pulses by looking up a table based on the current sector and current polarity, and output them dynamically. When the inductor current is positive, the driving pulse of the lower switch transistor of the corresponding bridge arm is defined as the main pulse and output directly; When the inductor current is negative, the drive pulse of the upper switch transistor of the corresponding bridge arm is defined as the main pulse and the drive channel output is switched.

6. The control circuit according to claim 2, characterized in that, The pulse generation module further includes a pulse blocking submodule, used to block the driving pulse of the corresponding phase when the zero-crossing signal triggers conduction, until the next carrier cycle.

7. The control circuit according to claim 2, characterized in that, The pulse generation module further includes a clamping processing submodule, which is used to compare the three-phase modulation signal with the carrier maximum value of the corresponding phase, and when the modulation signal of a certain phase is greater than the corresponding carrier maximum value, control the corresponding switch to remain on according to the current polarity to achieve clamping; Wherein, if the polarity of the inductor current is positive, the corresponding switch is the lower switch of the corresponding bridge arm; if the polarity of the inductor current is negative, the corresponding switch is the upper switch of the corresponding bridge arm.

8. The control circuit according to claim 1, characterized in that, The comparator module is specifically used for: The six inductor currents of the master phase and slave phase are subjected to simulated low-pass filtering to obtain six filtered currents; The six filtered currents are compared with the built-in programmable threshold to obtain digital level signals; wherein, if the filtered current is greater than the built-in programmable threshold, the digital level signal of the corresponding channel is low; if the filtered current is less than the built-in programmable threshold, the digital level signal of the corresponding channel is high. The digital level signal is digitally filtered to obtain the six zero-crossing signals.

9. The control circuit according to claim 1, characterized in that, The signal processing module includes: The analog filtering submodule is used to collect the three-phase inductor current and perform analog filtering on the three-phase inductor current; The sampling and processing submodule is used to sample and process the output voltage, the three-phase line voltage, and the filtered three-phase inductor current.

10. The control circuit according to claim 1, characterized in that, The loop control module includes: The voltage loop submodule is used to determine the reference value of the three-phase peak current based on the difference between the output voltage and the target voltage value; The current generation submodule is used to generate three current reference signals with a phase difference of 120° based on the angle and the reference value. The current loop module is used to generate and output the three-phase modulation signal based on the difference between the current reference signal and the three-phase inductor current.

11. A control method for an interleaved parallel three-phase rectifier, characterized in that, include: Obtain the three-phase inductor current, three-phase line voltage, and output voltage of the main phase; The angle is determined based on the three-phase line voltage; The three-phase modulation signal is determined based on the three-phase inductor current, the output voltage, and the angle. Based on the six inductor currents of the master and slave phases and the built-in programmable threshold, six zero-crossing signals are output. A master-slave interleaved carrier with a phase difference of 180° is generated based on the primary phase zero-crossing signal; Based on the master-slave interleaved carrier, the three-phase modulation signal, the angle, and the six zero-crossing signals, 12 driving pulses are generated and output; wherein, the driving pulse is turned on by the zero-crossing signal triggering the carrier counter to be cleared, and is turned off by the carrier count value reaching the turn-off threshold corresponding to the three-phase modulation signal.

12. The control method according to claim 11, characterized in that, The method further includes: After the chip is powered on, the pre-configured parameters of each module register are configured. The pre-configured parameters include one or more of the following: analog filter module enable state, voltage loop sub-module parameters, current loop module parameters, dead time, built-in programmable threshold, and voltage target value.

13. A charging pile, characterized in that, include: An AC filter, connected to the mains input, is used to filter the input AC power. The control circuit according to any one of claims 1-10 is used to control the rectification process; The rectifier bridge, connected to the AC filter and the control circuit, is used to convert the filtered AC power into DC power. The bus capacitor, connected to the rectifier bridge, is used to stabilize the DC bus voltage; A DC-DC converter, connected to the bus capacitor, is used to output DC power.

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