A bc battery and a method of manufacturing the same

Abstract

The application provides a BC battery and a preparation method thereof. The BC battery comprises a silicon substrate, the silicon substrate has opposite front and back surfaces, the front surface is provided with a front surface passivation layer, an anti-reflection layer and a patterned protective layer which are sequentially stacked, the patterned protective layer has a discontinuous structure, the back surface is provided with a P region and an N region, and the P region and the N region are provided with metal gate lines. By arranging a patterned protective layer on the front surface of the silicon substrate, the problem of scratch on the front surface of the battery is solved, the reflection of the front surface light is reduced, and the light absorption effect is improved.

Description

Technical Field

[0001] This invention belongs to the field of batteries and relates to a BC (Back Contact) battery and its preparation method. Background Technology

[0002] BC cells have no metal grid lines on the front side, while the PN regions on the back side are arranged in an alternating finger-like pattern. The front side of the BC cell only has a passivation layer and an antireflection layer, without metal electrodes to block the light, maximizing the utilization of incident light and minimizing optical losses. However, during metal grid line printing or cell handling, the front side is easily scratched, damaging the antireflection layer. Damage to the front antireflection layer increases the reflectivity of incident light, reduces light absorption efficiency, and scratches can cause light scattering, preventing some photons from effectively entering the cell to participate in photoelectric conversion. Furthermore, a damaged antireflection layer can increase the surface recombination rate, reduce minority carrier lifetime, and make surface defects more prone to becoming recombination centers, further reducing the cell's open-circuit voltage and fill factor.

[0003] Currently, to prevent scratches on the front side, a layer of UV adhesive is usually printed on the front side of BC solar cells. Although it can form a hard protective film after curing, effectively preventing scratches during transportation, installation and use, UV adhesive is easily affected by ultraviolet rays, temperature and humidity changes during long-term outdoor use, which leads to UV adhesive aging and cracking, thus adversely affecting the light absorption performance of BC cells.

[0004] Therefore, improving the protection effect on the front of the BC battery is crucial for enhancing battery performance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a BC battery and its preparation method. By setting a patterned protective layer on the front side of the silicon substrate, the problem of scratches on the front side of the battery is solved, while reducing the reflection of light from the front side and improving the light absorption effect.

[0006] To achieve this objective, the present invention adopts the following technical solution: In a first aspect, the present invention provides a BC battery, the BC battery comprising a silicon substrate having a front side and a back side opposite to each other, the front side being provided with a front passivation layer, an anti-reflection layer and a patterned protective layer stacked sequentially, the patterned protective layer having a discontinuous structure, the back side being provided with a P region and an N region, the P region and the N region being provided with metal grid lines.

[0007] The present invention provides a patterned protective layer on the anti-reflective layer on the front of the battery to prevent damage to the anti-reflective layer during battery manufacturing or handling. The patterned protective layer has excellent isolation performance and chemical stability, and also reduces the reflection of light from the front, effectively improving the amount of light absorbed from the front.

[0008] As a preferred embodiment of the present invention, the patterned protective layer is an inorganic material layer.

[0009] As a preferred embodiment of the present invention, the material of the patterned protective layer includes at least one of aluminum oxide, silicon oxide, or magnesium fluoride.

[0010] As a preferred embodiment of the present invention, the thickness of the patterned protective layer is 10nm to 80nm, for example, it can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm or 80nm, but is not limited to the listed values, other unlisted values ​​within this range are also applicable.

[0011] As one embodiment of the present invention, the orthogonal projection area of ​​the patterned protective layer on the surface of the antireflection layer is 30% to 60% of the area of ​​the antireflection layer, for example, it can be 30%, 35%, 40%, 45%, 50%, 55% or 60%, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0012] As a preferred embodiment of the present invention, the Mohs hardness of the patterned protective layer is ≥6.

[0013] The refractive index of the patterned protective layer is less than that of the antireflective layer.

[0014] As one embodiment of the present invention, the refractive index of the patterned protective layer is 1.3 to 1.9, for example, it can be 1.30, 1.35, 1.38, 1.40, 1.48, 1.50, 1.55, 1.60, 1.64, 1.67, 1.70, 1.76, 1.78, 1.80, 1.83, 1.85, 1.87 or 1.90, but is not limited to the listed values, other unlisted values ​​within this range are also applicable.

[0015] As a preferred embodiment of the present invention, both the front and back sides of the silicon substrate have a textured surface.

[0016] As one embodiment of the present invention, the front passivation layer includes a silicon oxide layer and / or an aluminum oxide layer.

[0017] In one embodiment of the present invention, the antireflection layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a titanium oxide layer.

[0018] As a preferred embodiment of the present invention, the graphic protective layer is at least one of the following: a grid pattern, a dot matrix pattern, an alternating wave pattern, an alternating strip pattern, and an alternating cross pattern.

[0019] In a second aspect, the present invention provides a method for fabricating the BC battery described in the first aspect. The method includes: sequentially depositing a front passivation layer and an antireflection layer on the front side of a silicon substrate, and then depositing a precursor material on the antireflection layer using a mask to form a patterned protective layer with a discontinuous structure; selectively doping the back side of the silicon substrate to form P-regions and N-regions; and fabricating metal grid lines in the P-regions and N-regions respectively. The formation of the patterned protective layer is performed before or after the fabrication of the metal grid lines.

[0020] As a preferred embodiment of the present invention, when the patterned protective layer is formed before the metal grid lines are fabricated, the precursor material includes alumina; when the patterned protective layer is formed after the metal grid lines are fabricated, the precursor material includes silicon oxide or magnesium fluoride.

[0021] As one embodiment of the present invention, when the patterned protective layer is formed after the metal grid line fabrication process, the preparation method further includes: ozone surface modification of the antireflection layer before depositing the precursor raw material.

[0022] As one embodiment of the present invention, the ozone concentration used for the ozone surface modification is ≥80 mg / m³. 3 .

[0023] The ozone surface modification time is 3 min to 5 min, for example, it can be 3.0 min, 3.5 min, 4.0 min, 4.5 min or 5.0 min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0024] As one embodiment of the present invention, the mask includes a metal mask, a quartz mask, or a polymer mask.

[0025] As one embodiment of the present invention, the deposition method of the patterned protective layer includes atmospheric pressure chemical vapor deposition or low pressure chemical vapor deposition.

[0026] As one embodiment of the present invention, when the patterned protective layer is patterned by atmospheric pressure chemical vapor deposition, the deposition temperature is 650°C to 850°C, for example, it can be 650°C, 680°C, 700°C, 720°C, 750°C, 780°C, 800°C, 830°C or 850°C, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0027] The deposition pressure for atmospheric pressure chemical vapor deposition is 0.5 kPa to 5.0 kPa, for example, it can be 0.5 kPa, 1.0 kPa, 1.5 kPa, 2.0 kPa, 2.5 kPa, 3.0 kPa, 3.5 kPa, 4.0 kPa, 4.5 kPa or 5.0 kPa, but is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0028] The deposition time for atmospheric pressure chemical vapor deposition is 8 min to 20 min, for example, it can be 8 min, 9 min, 10 min, 12 min, 15 min, 16 min, 18 min or 20 min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0029] The flow ratio of the precursor feedstock to the gas source in the atmospheric pressure chemical vapor deposition process is 1:(3~5), for example, it can be 1:3.0, 1:3.5, 1:4.0, 1:4.5 or 1:5.0, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0030] This invention controls the deposition parameters of atmospheric pressure chemical vapor deposition within the above-mentioned range, balancing the deposition rate and film density, and improving the quality of the protective film.

[0031] When using the low-pressure chemical vapor deposition patterned protective layer, the deposition temperature is 600℃~700℃, for example, it can be 600℃, 610℃, 620℃, 630℃, 640℃, 650℃, 660℃, 670℃, 680℃, 690℃ or 700℃, but is not limited to the listed values, other unlisted values ​​within this range are also applicable.

[0032] The deposition pressure of the low-pressure chemical vapor deposition is 5 Pa to 50 Pa, for example, it can be 5 Pa, 10 Pa, 15 Pa, 20 Pa, 25 Pa, 30 Pa, 35 Pa, 40 Pa, 45 Pa or 50 Pa, but is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0033] This invention maintains a low-pressure environment during the deposition of the patterned protective layer, improving the uniformity of the film and ensuring that the thickness deviation is no higher than ±2nm.

[0034] The deposition rate of the low-pressure chemical vapor deposition is 0.5 nm / min to 5.0 nm / min, for example, it can be 0.5 nm / min, 1.0 nm / min, 1.5 nm / min, 2.0 nm / min, 2.5 nm / min, 3.0 nm / min, 3.5 nm / min, 4.0 nm / min, 4.5 nm / min or 5.0 nm / min, but is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0035] This invention achieves the regulation of the deposition rate by controlling the pulse interval time of the precursor between 5 and 10 seconds, thereby stabilizing the deposition rate within the aforementioned range.

[0036] The deposition time for the low-pressure chemical vapor deposition is 12 min to 40 min, for example, it can be 12 min, 15 min, 18 min, 20 min, 22 min, 25 min, 28 min, 30 min, 35 min, 38 min or 40 min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0037] This invention improves the film density to no less than 98% by adjusting the deposition parameters of low-pressure chemical vapor deposition. At the same time, it enhances the interfacial bonding strength between the film and the antireflection layer, making the bonding strength no less than 6MPa. In addition, it reduces the internal stress of the film to no more than 100MPa, which can avoid the problem of protection failure caused by stress cracking during long-term use.

[0038] As a preferred embodiment of the present invention, the preparation method further includes: after completing the deposition of the patterned protective layer and the fabrication of the metal grid lines, annealing is performed to eliminate internal stress, followed by laser cutting for edge isolation to obtain a BC battery.

[0039] As one embodiment of the present invention, the annealing temperature is 400℃~500℃, for example, it can be 400℃, 410℃, 420℃, 430℃, 440℃, 450℃, 460℃, 470℃, 480℃, 490℃ or 500℃, but is not limited to the listed values, other unlisted values ​​within this range are also applicable.

[0040] The annealing time is 30 min to 60 min, for example, it can be 30 min, 35 min, 40 min, 45 min, 50 min, 55 min or 60 min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0041] As one embodiment of the present invention, the power of the laser cutting is 5W to 10W, for example, it can be 5W, 6W, 7W, 8W, 9W or 10W, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0042] The laser cutting speed is 100mm / s to 200mm / s, for example, it can be 100mm / s, 110mm / s, 120mm / s, 130mm / s, 140mm / s, 150mm / s, 160mm / s, 170mm / s, 180mm / s, 190mm / s or 200mm / s, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a BC battery and its preparation method. By adding a patterned protective layer to the antireflective layer on the front of the battery, a protective layer is provided to prevent damage to the antireflective layer during battery manufacturing or handling, which would reduce light absorption and increase surface recombination. At the same time, the patterned protective layer has excellent isolation performance and chemical stability, ensuring long-term battery use. Furthermore, the patterned protective layer reduces the reflection of light from the front, greatly increasing the light absorption effect, making the light absorption efficiency no less than 93%, effectively improving the battery's electrical performance and conversion efficiency. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of a BC battery provided for a specific embodiment of the present invention.

[0045] Figure 2 This is a schematic diagram of the structure of a patterned protective layer for a BC battery according to a specific embodiment of the present invention.

[0046] Wherein, 1-silicon substrate; 101-front side; 102-back side; 2-front passivation layer; 3-antireflection layer; 4-patterning protective layer; 5-N region; 6-P region; 7-metal gate line. Detailed Implementation

[0047] It should be understood that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0048] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0049] In one specific embodiment, the present invention provides a BC battery, which includes a silicon substrate 1 having a front side 101 and a back side 102, wherein the front side 101 is a light-receiving surface and the back side 102 is a backlighting surface. Figure 1 and Figure 2 As shown, the front side 101 is provided with a front passivation layer 2, an anti-reflection layer 3 and a patterned protective layer 4 stacked in sequence. The patterned protective layer 4 has a discontinuous structure. The back side 102 is provided with a P area 6 and an N area 5. Metal grid lines 7 are provided in the P area 6 and the N area 5.

[0050] The silicon substrate 1 includes an N-type monocrystalline silicon wafer or a P-type monocrystalline silicon wafer, with both its front surface 101 and back surface 102 having a textured structure to create a light-trapping effect, enabling uniform distribution of each functional layer, improving interface adhesion strength, and thus enhancing the photoelectric conversion efficiency of the battery. The textured structure can be a pyramidal textured surface.

[0051] The front passivation layer 2 located on the front side 101 of the silicon substrate 1 includes a silicon oxide layer and / or an aluminum oxide layer, forming chemical passivation, which helps to reduce surface recombination, and at the same time has field effect passivation, forming a shielding layer to prevent charge carriers from directly contacting the battery surface.

[0052] The antireflection layer 3 includes at least one of a silicon nitride layer, a silicon oxide layer, and a titanium oxide layer, which can reduce light reflection from the front surface 101. The antireflection layer 3 can be a single-layer structure or a multi-layer structure to reduce the reflectivity of sunlight incident on the front surface 101 to <1%.

[0053] The patterned protective layer 4 is an inorganic material layer that protects the front surface 101 from scratches and reduces light reflection from the front surface 101, further enhancing light absorption on the front surface 101 of the battery. The patterned protective layer 4 is specifically made of at least one of aluminum oxide, silicon oxide, or magnesium fluoride, with a Mohs hardness ≥6, which more effectively resists scratches during printing and transfer. The refractive index of the patterned protective layer 4 is lower than that of the antireflective layer 3, reducing interface reflection loss.

[0054] The thickness of the patterned protective layer 4 is 10nm to 80nm. The thickness refers to the straight line length from the back surface 102 to the front surface 101.

[0055] The discontinuous structure described in this invention refers to a structure where the patterned protective layer 4 does not completely cover the antireflection layer 3, resulting in partial exposure of the antireflection layer 3 on the front side 101 of the silicon substrate 1. The projected area of ​​the patterned protective layer 4 on the surface of the antireflection layer 3 is 30% to 60% of the area of ​​the antireflection layer 3.

[0056] Specifically, the graphic protective layer 4 is at least one of the following: a grid pattern, a dot matrix pattern, an alternating wave pattern, an alternating strip pattern, and an alternating cross pattern. When the graphic protective layer 4 is a grid pattern, the shape of the grid includes, but is not limited to, a circle, an ellipse, a rhombus, a triangle, a quadrilateral, or other polygons.

[0057] The N-region 5 and P-region 6 located on the back surface 102 of the silicon substrate 1 are both multiple and are distributed alternately. A gap is left between the N-region 5 and the P-region 6 to ensure insulation between them, prevent short circuits, and reduce surface recombination. The surface of the silicon substrate 1 within the gap has a textured surface.

[0058] The metal gate line 7 in region N 5 has opposite polarities to the metal gate line 7 in region P 6. The material of the metal gate line 7 includes, but is not limited to, silver, aluminum, copper, and titanium. The metal gate line 7 typically includes multiple main gate lines and multiple fine gate lines, which are perpendicular to each other. The fine gate lines collect charge carriers, while the main gate lines collect the small currents collected by the fine gate lines and transmit them outwards. The number of main gate lines is small, while the number of fine gate lines is large, and the width of the main gate lines is greater than the width of the fine gate lines. The linewidth of the main gate lines is preferably 100~200 μm, and the thickness is preferably 20~30 μm.

[0059] In addition, the N-region 5 and the P-region 6 are also provided with back contact structures of opposite polarity, and metal grid lines 7 are disposed on the back contact structures. The back contact structure includes a stacked tunneling oxide layer and a doped layer, with the tunneling oxide layer disposed close to the silicon substrate 1. Depending on the type of battery, the back contact structure can be composed of a single stacked structure of tunneling oxide layer and doped layer, or it can be composed of a stacked structure of multiple stacked structures of tunneling oxide layer and doped layer. For example, for a single-cell battery, the back contact structure includes a stacked tunneling oxide layer and a doped layer; for a dual-junction battery, the back contact structure includes a first tunneling oxide layer, a first doped layer, a second tunneling oxide layer, and a second doped layer stacked sequentially. The back contact structure is also provided with a back passivation film and a back antireflection layer.

[0060] In another specific embodiment, the present invention provides a method for fabricating a BC battery, specifically including: sequentially depositing a front passivation layer 2 and an antireflection layer 3 on the front side 101 of a silicon substrate 1, and then depositing a precursor material on the antireflection layer 3 using a mask to form a patterned protective layer 4 with a discontinuous structure; selectively doping the back side 102 of the silicon substrate 1 to form P-regions 6 and N-regions 5; and fabricating metal grid lines 7 in the P-regions 6 and N-regions 5 respectively; the formation of the patterned protective layer 4 is performed before or after the fabrication of the metal grid lines 7.

[0061] The present invention polishes the silicon substrate 1 to reduce its weight, so that its weight meets the required requirements.

[0062] The present invention performs texturing on the front side 101 and the back side 102 of the silicon substrate 1, and the processing technology includes, but is not limited to, wet texturing or laser etching. The present invention does not specifically limit the specific operation and process parameters.

[0063] The deposition method of the front passivation layer 2 includes, but is not limited to, chemical vapor deposition, thermal oxidation, atomic layer deposition, low-pressure chemical vapor deposition and solution deposition, etc. The present invention does not specifically limit its specific operation and process parameters.

[0064] The deposition method of the antireflection layer 3 includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (PCVD), atomic layer deposition (ALD), sol-gel method and spray pyrolysis method, etc. The present invention does not specifically limit its specific operation and process parameters.

[0065] The mask, including metal, quartz, or polymer masks, is laser-engraved to form a structure corresponding to the patterned protective layer 4 with an accuracy of ±1μm. The dimensions of the mask are adjusted according to the dimensions of the patterned protective layer 4. Metal masks include, but are not limited to, stainless steel, titanium, and titanium alloys. Polymer masks possess high-temperature resistance and include, but are not limited to, polyimide, polybenzoxazole, and polytetrafluoroethylene.

[0066] The deposition method of the patterned protective layer 4 includes atmospheric pressure chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD).

[0067] When using the atmospheric pressure chemical vapor deposition patterned protective layer 4, ensure that the mask is tightly attached to the surface of the antireflective layer 3 on the front side 101 of the silicon substrate 1, with a bonding gap ≤ 5 μm, to avoid deposition deviation. Simultaneously, control the deposition temperature to 650℃~850℃, the deposition pressure to 0.5kPa~5.0kPa, and the flow ratio of precursor raw material to gas source to 1:(3~5) to balance the deposition rate and film density. The deposition time is 8min~20min to obtain the pattern of the required thickness. Water vapor can be used as the gas source. The small difference between the refractive index of the patterned protective layer 4 and the refractive index of the antireflective layer 3 (1.9~2.1) reduces interface reflection loss, and the Mohs hardness reaches ≥6, which can more effectively resist scratches during preparation or transfer.

[0068] When the low-pressure chemical vapor deposition patterned protective layer 4 is used, the mask is fixed by vacuum adsorption to ensure precise pattern alignment. Simultaneously, the deposition temperature is controlled at 600℃~700℃, and the deposition pressure at 5Pa~50Pa to improve film uniformity, ensuring a thickness deviation of ≤±2nm. By controlling the precursor pulse interval to 5~10s, the deposition rate is adjusted to be stable at 0.5nm / min~5.0nm / min, and the deposition time is 12min~40min, obtaining the desired pattern thickness. The deposited patterned protective layer 4 has a density ≥98%, its interfacial bonding strength with the antireflection layer 3 is ≥6MPa, and the film internal stress is ≤100MPa, preventing protective failure due to stress cracking during long-term use. Furthermore, the refractive index of the patterned protective layer 4 is lower than that of the antireflection layer 3, which forms a gradient refractive index system with the antireflection layer 3 on the front side 101 and the silicon substrate 1, which increases sequentially along the light incident direction on the front side 101. That is, the refractive index of the silicon substrate 1 > the refractive index of the antireflection layer 3 > the refractive index of the patterned protective layer 4, further reducing the incident light reflectivity and improving the light absorption efficiency.

[0069] The raw materials and preparation processes vary depending on the different preparation times in this invention.

[0070] Regarding the raw materials, when the patterned protective layer 4 is formed before the metal grid lines 7 are fabricated, the precursor material includes aluminum oxide; when the patterned protective layer 4 is formed after the metal grid lines 7 are fabricated, the precursor material includes silicon oxide or magnesium fluoride.

[0071] Regarding the fabrication process, regardless of whether the coating treatment is performed before or after the fabrication of the metal grid lines 7, the deposition method of the patterned protective layer 4 is the same, namely, atmospheric pressure chemical vapor deposition or low pressure chemical vapor deposition. The specific operation and process parameters are as described above and will not be repeated here.

[0072] Furthermore, when the patterned protective layer 4 is formed after the metal grid line 7 is fabricated, the antireflection layer 3 needs to be ozone-modified before the precursor material is deposited to increase the number of hydroxyl groups on the surface of the antireflection layer 3 and improve the adhesion between the patterned protective layer 4 and the antireflection layer 3.

[0073] Specifically, the ozone concentration used for the ozone surface modification is ≥80 mg / m³. 3 The time is 3 to 5 minutes, so that the adhesion level between the patterned protective layer 4 and the anti-reflective layer 3 reaches the first level in GB / T9286-1998.

[0074] In some embodiments, after the deposition of the patterned protective layer 4 and the fabrication of the metal grid lines 7 are completed, an annealing process is performed to eliminate internal stress, followed by laser cutting for edge isolation to obtain a BC battery.

[0075] Specifically, the annealing temperature is 400℃~500℃ and the time is 30min~60min; the laser cutting power is 5~10W and the cutting speed is 100~200mm / s to optimize battery performance.

[0076] The selective doping process in this invention includes the following steps: S1: Place the silicon substrate 1 into the LPCVD equipment chamber, evacuate the chamber until the pressure is <10Pa, introduce N2 to purge the chamber, then heat it to the required temperature, and then introduce a mixture of SiH4 and H2 gas to react and obtain the intrinsic silicon wafer. After the reaction is completed, stop the gas supply, allow it to cool naturally to room temperature, remove the intrinsic silicon wafer, and then pattern and define the N region 5 and P region 6 on the back side 102.

[0077] S2: A P-type semiconductor region and a borosilicate glass (BSG) layer are formed on the back side 102 of the silicon substrate 1 by boron diffusion. The silicon substrate 1 is placed in a diffusion furnace and heated to 800℃~1000℃. B2H6 and oxygen are introduced. At high temperature, boron atoms migrate from the gas phase source to the amorphous silicon layer. After diffusion is completed, the temperature is then cooled to room temperature to form a P-type semiconductor region and a BSG layer on the surface of the silicon substrate 1.

[0078] S3: The BSG layer in region 5 is removed by laser processing, followed by alkaline etching to adjust the BSG thickness and the surface morphology of silicon substrate 1.

[0079] S4: The tunneling layer and doped layer are grown by LPCVD.

[0080] S5: An N-type semiconductor region and a silicon phosphosilicate glass (PSG) layer are formed by phosphorus diffusion to form a PN junction with the previously formed P-type semiconductor region.

[0081] S6: The PSG layer in P region 6 is removed by laser processing, and then the spacer between N region 5 and P region 6 is texturized to improve the surface morphology and increase the light absorption efficiency.

[0082] It should be noted that the processes involved in each of the above steps are all well-known to those skilled in the art, and the present invention does not specifically limit the preparation procedures and process parameters.

[0083] This invention produces metal grid lines 7 using a printing process, employing silver paste, copper paste, or aluminum paste as raw materials. The specific operation of the printing process is not limited in this invention. After printing, the grid lines are placed in a sintering furnace and dried sequentially at 800℃~900℃ for 10~15 minutes, followed by sintering for 5~8 minutes to form the metal grid lines 7.

[0084] Example 1 This embodiment provides a BC battery and its fabrication method. The BC battery includes a silicon substrate 1, which has a front side 101 and a back side 102. The front side 101 has a textured surface and is provided with a front passivation layer 2, an anti-reflection layer 3, and a patterned protective layer 4 stacked sequentially. The front passivation layer is an aluminum oxide layer; the anti-reflection layer 3 is a silicon nitride layer; and the patterned protective layer 4 is an aluminum oxide layer. The patterned protective layer 4 has a discontinuous structure, with an alternating wave-like pattern, and its positive projection area on the surface of the anti-reflection layer 3 is 45% of the anti-reflection layer area. The back side 102 is provided with a plurality of P-regions 6 and a plurality of N-regions 5, which are alternately arranged to form an isolation region between the P-regions 6 and N-regions 5. The P-regions 6 and N-regions 5 are also provided with a first metal grid line and a second metal grid line with opposite polarities, respectively.

[0085] The preparation method in this embodiment specifically includes the following steps: (1) Polish the silicon substrate 1 to reduce its weight, and form a micron pyramid textured surface by etching the front side 101 of the silicon substrate 1 with an alkaline solution.

[0086] (2) Place the silicon substrate 1 into the LPCVD equipment chamber, evacuate the chamber until the chamber pressure is <10Pa, introduce N2 to purge the chamber, then heat it to 590℃, and then introduce a mixed gas of SiH4 and H2 to maintain the chamber pressure at 80Pa to carry out the reaction and obtain the intrinsic silicon wafer. After the reaction is completed, stop the gas supply, let it cool naturally to room temperature, take out the intrinsic silicon wafer, and then define the N region 5 and P region 6 on the back side 102 in a pattern.

[0087] (3) The intrinsic silicon wafer is placed in a diffusion furnace and heated to 950°C. B2H6 and oxygen are introduced. At high temperature, boron atoms migrate from the gas phase source to the amorphous silicon layer. After diffusion is completed, the temperature is cooled to room temperature, and a P-type semiconductor region and a BSG layer are formed on the back side 102 of the intrinsic silicon wafer.

[0088] (4) The BSG in the N region 5 is removed by laser treatment, and the back side 102 is etched with alkali to adjust the thickness of the BSG layer and the surface morphology of the sheet to obtain the first sheet.

[0089] (5) Using LPCVD process, SiH4 (containing 20% ​​H2) is used as the gas source, the reaction temperature is controlled at 590℃, the pressure is 80Pa, and N2 with a flow rate of 100sccm is used as the carrier gas. A tunneling layer with a thickness of 1.5nm and an amorphous silicon layer with a thickness of 200nm are formed sequentially on the back side 102 of the first sheet to obtain the second sheet.

[0090] (6) The second sheet is placed in a diffusion furnace and heated to 950°C. POCl3, oxygen and nitrogen are introduced. At high temperature, phosphorus atoms migrate from the gas phase source to the amorphous silicon layer. After diffusion is completed, the temperature is cooled to room temperature. An N-type semiconductor region and a PSG layer are formed on the back side 102 of the second sheet, so that it forms a PN junction with the P-type semiconductor region formed in step (5). The PSG layer of the P region 6 is then removed by laser processing to obtain the third sheet.

[0091] (7) Etching and texturing are performed on the isolation area between the front side 101 and the back side 102 of the third sheet to improve the surface morphology and increase the light absorption efficiency.

[0092] (8) A passivation layer 2 with a thickness of 5 nm is formed by depositing aluminum oxide on the front side 101 using the ALD process. Then, silicon nitride is deposited on the surface of the passivation layer 2 using the PECVD process to form an anti-reflection layer 3 with a thickness of 80 nm on the front side 101 with a refractive index of 2.0. At the same time, silicon nitride is deposited on the back side 102 of the third sheet using the PECVD process to form a back anti-reflection layer with a thickness of 70 nm with a refractive index of 2.2, thus obtaining the fourth sheet.

[0093] (9) Provide a stainless steel mask having a wavy pattern arranged at intervals, the wavy pattern having a wavelength of 100 μm, an amplitude of 10 μm, and a width of 50 μm.

[0094] (10) Place the fourth sheet in the equipment chamber of atmospheric pressure chemical vapor deposition, so that the stainless steel mask is tightly attached to the surface of the front 101 antireflection layer 3, ensuring that the gap between the two is ≤5μm, and then perform atmospheric pressure chemical vapor deposition. The deposition parameters are set as follows: the deposition temperature is 750℃, the gas flow ratio of the introduced alumina precursor to H2O is 1:4, the deposition pressure is 3kPa, the deposition time is 15min, and a patterned protective layer 4 with a thickness of 40nm is formed, with a refractive index of 1.76 and a Mohs hardness of >6.

[0095] (11) The first metal grid line and the second metal grid line of N region 5 and P region 6 are respectively made by printing process and sintered to obtain the battery cell.

[0096] (12) The battery cells are placed in an annealing furnace and annealed at 450°C for 45 minutes to eliminate internal stress. Then, the edges are isolated by laser cutting. The laser cutting power is 8W and the cutting speed is 150mm / s to obtain BC batteries.

[0097] The BC battery prepared in this embodiment has a front scratch rate of 0.6%, a light absorption efficiency (light wavelength range of 300~1100nm) of 93.1%, an open circuit voltage of 745mV, a fill factor of 85.6%, and a conversion efficiency of 27.5%.

[0098] Example 2 This embodiment provides a BC battery and its preparation method. The difference from Embodiment 1 is that the deposition of the patterned protective layer 4 adopts the LPCVD process. Specifically, in step (10), the fourth sheet is placed in the equipment chamber of the low-pressure chemical vapor deposition, so that the stainless steel mask is tightly attached to the surface of the front antireflection layer 3 101, ensuring that the bonding gap is ≤5μm. Then, low-pressure chemical vapor deposition is performed. The deposition parameters are set as follows: the deposition temperature is controlled at 650℃, the deposition pressure is 30Pa, the pulse interval of the precursor is controlled at 8s, the deposition rate is stabilized at 2nm / min, the deposition time is 25min, and a patterned protective layer 4 with a thickness of 50nm is formed. Its refractive index is 1.76 and its Mohs hardness is >6. The remaining preparation steps are the same as those in Embodiment 1.

[0099] The BC battery prepared in this embodiment has a front scratch rate of 0.6%, a light absorption efficiency (light wavelength range of 300~1100nm) of 93.1%, an open circuit voltage of 745mV, a fill factor of 85.6%, and a conversion efficiency of 27.5%.

[0100] Example 3 This embodiment provides a BC battery and its fabrication method. The BC battery includes a silicon substrate 1, which has a front side 101 and a back side 102. The front side 101 has a textured surface and is provided with a front passivation layer 2, an anti-reflection layer 3, and a patterned protective layer 4 stacked sequentially. The front passivation layer 2 is an aluminum oxide layer, the anti-reflection layer 3 is a silicon nitride layer, and the patterned protective layer 4 is a silicon dioxide layer. The patterned protective layer 4 has a discontinuous structure, with an alternating wave-like pattern, and its positive projection area on the surface of the anti-reflection layer 3 is 35% of the anti-reflection layer area. The back side 102 is provided with a plurality of P-regions 6 and a plurality of N-regions 5, which are alternately arranged to form an isolation region between the P-regions 6 and N-regions 5. The P-regions 6 and N-regions 5 are also provided with a first metal grid line and a second metal grid line with opposite polarities, respectively.

[0101] The preparation method in this embodiment specifically includes the following steps: (1) Polish the silicon substrate 1 to reduce its weight, and form a micron pyramid textured surface by etching the front side 101 of the silicon substrate 1 with an alkaline solution.

[0102] (2) Place the silicon substrate 1 into the LPCVD equipment chamber, evacuate the chamber until the chamber pressure is <10Pa, introduce N2 to purge the chamber, then heat it to 590℃, and then introduce a mixed gas of SiH4 and H2 to maintain the chamber pressure at 80Pa to carry out the reaction and obtain the intrinsic silicon wafer. After the reaction is completed, stop the gas supply, let it cool naturally to room temperature, take out the intrinsic silicon wafer, and then define the N region 5 and P region 6 on the back side 102 in a pattern.

[0103] (3) The intrinsic silicon wafer is placed in a diffusion furnace and heated to 950°C. B2H6 and oxygen are introduced. At high temperature, boron atoms migrate from the gas phase source to the amorphous silicon layer. After diffusion is completed, the temperature is cooled to room temperature, and a P-type semiconductor region and a BSG layer are formed on the back side 102 of the intrinsic silicon wafer.

[0104] (4) The BSG in the N region 5 is removed by laser treatment, and the back side 102 is etched with alkali to adjust the thickness of the BSG layer and the surface morphology of the sheet to obtain the first sheet.

[0105] (5) By using the LPCVD process, with SiH4 (20%H2) as the gas source, the reaction temperature is controlled at 590℃ and the pressure at 80Pa. N2 with a flow rate of 100sccm is used as the carrier gas to form a tunneling layer with a thickness of 1.5nm and an amorphous silicon layer with a thickness of 200nm in sequence, and a second sheet is obtained.

[0106] (6) The second sheet is placed in a diffusion furnace and heated to 950°C. POCl3, oxygen and nitrogen are introduced. At high temperature, phosphorus atoms migrate from the gas phase source to the amorphous silicon layer. After diffusion is completed, the temperature is cooled to room temperature. An N-type semiconductor region and a PSG layer are formed on the back side 102 of the second sheet, so that it forms a PN junction with the P-type semiconductor region formed in step (5). The PSG layer of the P region 6 is then removed by laser processing to obtain the third sheet.

[0107] (7) Etching and texturing are performed on the isolation area between the front side 101 and the back side 102 of the third sheet to improve the surface morphology and increase the light absorption efficiency.

[0108] (8) A passivation layer 2 with a thickness of 5 nm is formed by depositing aluminum oxide on the front side 101 using the ALD process. Then, a silicon nitride anti-reflection layer 3 with a thickness of 80 nm is formed by depositing silicon nitride on the front passivation layer 2 using the PECVD process. Its refractive index is 2.0. At the same time, a back anti-reflection layer with a thickness of 70 nm is formed by depositing silicon nitride on the back side 102 of the third sheet using the PECVD process. Its refractive index is 2.2.

[0109] (9) The first metal grid line and the second metal grid line of N area 5 and P area 6 are respectively produced by printing process, and the fourth sheet is obtained by sintering.

[0110] (10) Ozone surface modification is performed on the antireflection layer 3 on the front side 101 of the fourth sheet, and the ozone concentration is controlled at 90 mg / m³. 3 The time was 4 minutes to increase the number of hydroxyl groups on the surface of the front 101 antireflection layer 3.

[0111] (11) Provide a quartz mask having a wavy pattern arranged at intervals, the wavy pattern having a wavelength of 100 μm, an amplitude of 10 μm, and a width of 50 μm.

[0112] (12) Place the fourth sheet in the equipment chamber of atmospheric pressure CVD, so that the quartz mask is tightly attached to the surface of the front antireflection layer 3 of 101, and ensure that the bonding gap is ≤5μm. Then perform atmospheric pressure chemical vapor deposition. The deposition parameters are set as follows: the deposition temperature is 800℃, the gas flow ratio of SiH4 to O2 is 1:4, the deposition pressure is 4kPa, and the deposition time is 12min. A patterned protective layer 4 with a thickness of 35nm is formed, with a refractive index of 1.46 and a Mohs hardness of >6, and the battery cell is obtained.

[0113] (13) The battery cell is placed in an annealing furnace and annealed at 500°C for 30 minutes to eliminate internal stress. Then, it is laser-cut for edge isolation, with a laser cutting power of 10W and a cutting speed of 100mm / s, to obtain the BC battery.

[0114] The BC battery prepared in this embodiment has a front scratch rate of 0.6%, a light absorption efficiency (light wavelength range of 300~1100nm) of 93.1%, an open circuit voltage of 745mV, a fill factor of 85.6%, and a conversion efficiency of 27.5%.

[0115] Example 4 This embodiment provides a BC battery and its preparation method. The difference from embodiment 3 is that the deposition of the patterned protective layer 4 adopts the LPCVD process. Specifically, in step (12), the fourth sheet is placed in the LPCVD equipment chamber, so that the quartz mask is tightly attached to the surface of the front antireflection layer 3 101, ensuring that the bonding gap is ≤5μm. Then, low-pressure chemical vapor deposition is performed. The deposition parameters are set as follows: the deposition temperature is controlled at 700℃, the deposition pressure is 20Pa, the pulse interval of the precursor is controlled at 10s, the deposition rate is stabilized at 5nm / min, the deposition time is 20min, and a patterned protective layer 4 with a thickness of 60nm is formed. Its refractive index is 1.46 and its Mohs hardness is >6. The remaining preparation steps are the same as those in embodiment 3.

[0116] The BC battery prepared in this embodiment has a front scratch rate of 0.6%, a light absorption efficiency (light wavelength range of 300~1100nm) of 93.1%, an open circuit voltage of 745mV, a fill factor of 85.6%, and a conversion efficiency of 27.5%.

[0117] Example 5 This embodiment provides a BC battery and its preparation method. The difference from Embodiment 3 is that the patterned protective layer 4 is a magnesium fluoride layer, and its positive projection area on the surface of the antireflection layer 3 is 50% of the antireflection layer area. In its preparation process, the ozone concentration in step (10) is 80 mg / m³. 3 The deposition time is 5 min; in step (12), the deposition parameters for atmospheric pressure chemical vapor deposition are as follows: the deposition temperature is 850℃, the gas flow ratio of SiH4 to O2 is 1:4, the deposition pressure is 2 kPa, the deposition time is 35 min, and a patterned protective layer 4 with a thickness of 80 nm is formed, the refractive index is 1.38, the Mohs hardness is >6, and the remaining preparation steps are the same as in Example 3.

[0118] The BC battery prepared in this embodiment has a front scratch rate of 0.6%, a light absorption efficiency (light wavelength range of 300~1100nm) of 93.1%, an open circuit voltage of 745mV, a fill factor of 85.6%, and a conversion efficiency of 27.5%.

[0119] Example 6 This embodiment provides a BC battery and its preparation method. The difference from Embodiment 4 is that the patterned protective layer 4 is a magnesium fluoride layer, and in its preparation process, the ozone concentration in step (10) is 80 mg / m³. 3 The deposition time was 3 minutes. During the preparation process, the deposition parameters for low-pressure chemical vapor deposition were set as follows: the deposition temperature was controlled at 650℃, the deposition pressure was 35Pa, the pulse interval of the precursor was controlled at 5s to stabilize the deposition rate at 0.5nm / min, and the deposition time was 40 minutes to form a patterned protective layer 4 with a thickness of 55nm, a refractive index of 1.38, and a Mohs hardness >6. The remaining preparation steps were the same as in Example 4.

[0120] The BC battery prepared in this embodiment has a front scratch rate of 0.6%, a light absorption efficiency (light wavelength range of 300~1100nm) of 93.1%, an open circuit voltage of 745mV, a fill factor of 85.6%, and a conversion efficiency of 27.5%.

[0121] Example 7 This embodiment provides a BC battery and its preparation method. The difference from Embodiment 1 is that the patterned protective layer 4 is a dot matrix pattern, while the rest of the structure, preparation steps and process parameters are the same as in Embodiment 1.

[0122] Example 8 This embodiment provides a BC battery and its preparation method. The difference from Embodiment 3 is that the patterned protective layer 4 is a grid pattern with a circular grid. The remaining structure, preparation steps and process parameters are the same as those in Embodiment 3.

[0123] This invention adds a protective layer with a discontinuous pattern to the antireflective layer 3 on the front side 101 of the battery to resist scratches on the front side 101, greatly reducing the damage rate of the front side 101. The difference between its refractive index and the refractive index of the antireflective layer 3 is small, which reduces interface reflection and improves the light absorption effect, making the light absorption efficiency not less than 93%, thereby improving the battery conversion efficiency.

[0124] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A BC battery, characterized in that, The BC battery includes a silicon substrate with a front side and a back side. The front side is provided with a front passivation layer, an anti-reflection layer and a patterned protective layer stacked sequentially. The patterned protective layer has a discontinuous structure. The back side is provided with P-regions and N-regions, and metal grid lines are provided in the P-regions and the N-regions.

2. The BC battery according to claim 1, characterized in that, The graphic protective layer is an inorganic material layer.

3. The BC battery according to claim 2, characterized in that, The material of the patterned protective layer includes at least one of aluminum oxide, silicon oxide, or magnesium fluoride.

4. The BC battery according to any one of claims 1-3, characterized in that, The thickness of the patterned protective layer is 10nm~80nm; Preferably, the orthographic projection area of ​​the patterned protective layer on the surface of the antireflective layer is 30% to 60% of the area of ​​the antireflective layer.

5. The BC battery according to any one of claims 1-3, characterized in that, The Mohs hardness of the patterned protective layer is ≥6; The refractive index of the patterned protective layer is less than that of the antireflective layer; Preferably, the refractive index of the patterned protective layer is 1.3 to 1.

9.

6. The BC battery according to claim 1, characterized in that, Both the front and back sides of the silicon substrate have a textured surface; Preferably, the front passivation layer comprises a silicon oxide layer and / or an aluminum oxide layer; Preferably, the antireflection layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a titanium oxide layer.

7. The BC battery according to any one of claims 1-3, characterized in that, The graphic protective layer is at least one of the following: a grid pattern, a dot matrix pattern, an alternating wave pattern, an alternating strip pattern, and an alternating cross pattern.

8. A method for preparing a BC battery according to any one of claims 1-7, characterized in that, The preparation method includes: A passivation layer and an antireflection layer are sequentially deposited on the front side of a silicon substrate. Then, a precursor material is deposited on the antireflection layer using a mask to form a patterned protective layer with a discontinuous structure. Selective doping of the back side of the silicon substrate forms P-regions and N-regions; Metal grid lines are fabricated in regions P and N respectively; The process of forming the patterned protective layer is either before or after the fabrication of the metal grid lines.

9. The method for preparing a BC battery according to claim 8, characterized in that, When the patterned protective layer is formed before the metal grid lines are fabricated, the precursor material includes alumina; when the patterned protective layer is formed after the metal grid lines are fabricated, the precursor material includes silicon oxide or magnesium fluoride. Preferably, when the patterned protective layer is formed after the metal grid line fabrication process, the preparation method further includes: ozone surface modification of the antireflection layer before depositing the precursor raw material; Preferably, the ozone concentration used in the ozone surface modification is ≥80 mg / m³. 3 The time is 3 to 5 minutes; Preferably, the mask includes a metal mask, a quartz mask, or a polymer mask; Preferably, the deposition method of the patterned protective layer includes atmospheric pressure chemical vapor deposition or low pressure chemical vapor deposition; Preferably, when the patterned protective layer is patterned by atmospheric pressure chemical vapor deposition, the deposition temperature is 650℃~850℃, the deposition pressure is 0.5kPa~5.0kPa, the deposition time is 8min~20min, and the flow ratio of precursor raw material to gas source is 1:(3~5). When the low-pressure chemical vapor deposition patterned protective layer is used, the deposition temperature is 600℃~700℃, the deposition pressure is 5Pa~50Pa, the deposition rate is 0.5nm / min~5.0nm / min, and the deposition time is 12min~40min.

10. The method for preparing a BC battery according to claim 8 or 9, characterized in that, The preparation method further includes: after completing the deposition of the patterned protective layer and the fabrication of the metal grid lines, annealing is performed to eliminate internal stress, followed by laser cutting for edge isolation to obtain the BC cell; Preferably, the annealing treatment is performed at a temperature of 400℃~500℃ for a time of 30min~60min; Preferably, the laser cutting power is 5W~10W and the cutting speed is 100mm / s~200mm / s.

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