Temperature coefficient adjustable current source generation circuit and clock generation circuit

Abstract

The application provides a temperature coefficient adjustable current source generation circuit and a clock generation circuit, the temperature coefficient adjustable current source generation circuit comprises a first operational amplifier, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor, a first triode and a second triode, and the clock generation circuit further comprises a sawtooth wave generation module, a voltage comparison and enable control module, a threshold voltage generation module and a logic shaping and flip-flop module; the temperature coefficient adjustable current source generation circuit and the clock generation circuit jointly generate a current source with zero temperature coefficient, achieve the temperature compensation effect, and the application has the advantages of low cost, small size, short starting time, no mechanical device and good shockproof effect.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a temperature coefficient adjustable current source generation circuit and a clock generation circuit. Background Technology

[0002] Clocks are a core foundational module of modern digital systems, providing a stable timing reference for chips, circuits, and communication protocols. They are widely used in critical areas such as timing, synchronization, data sampling, and signal processing. With the continuous evolution of communication technologies towards 5G / 6G, high-speed SerDes, optical communication, and high-performance computing, data transmission rates have reached hundreds of Gb or even Tb per second. This places extremely stringent requirements on the frequency stability, phase noise, and jitter performance of clock signals. Any minute deviation in the clock signal can accumulate and amplify in high-speed links, leading to receiver synchronization failures, a sharp increase in bit error rate, and even communication link interruptions. Among the many environmental factors affecting clock stability, temperature drift is one of the most common and difficult challenges to overcome. An ideal clock source should possess extremely high temperature stability, with its output frequency remaining unchanged regardless of ambient temperature variations, thus ensuring consistent system performance across the entire temperature range. Therefore, developing clock sources with low temperature coefficients (i.e., smooth frequency-temperature characteristics) has always been a key technological goal for high-frequency, high-reliability electronic systems. In existing technologies, crystal oscillators are commonly used as clocks for key modules because crystal oscillators have a small temperature coefficient. However, using crystal oscillators has four obvious disadvantages: 1. Slow startup speed (on the order of hundreds of microseconds) 2. High cost 3. Large size 4. Not shockproof. Summary of the Invention

[0003] This invention is made to solve the above-mentioned problems, and its purpose is to provide a temperature coefficient adjustable current source generation circuit and a clock generation circuit.

[0004] This invention provides a temperature-coefficient adjustable current source generation circuit, characterized by comprising: a first operational amplifier for stabilizing the circuit's static operating point; a first transistor, with its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain electrically connected to the non-inverting input terminal of the first operational amplifier, for providing a reference current branch; a second transistor, with its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain electrically connected to the inverting input terminal of the first operational amplifier, for providing a reference current branch; a third transistor, with its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain as a constant current output terminal, for replicating and outputting the charging current; and a first resistor, with its first terminal... A first resistor, electrically connected to the drain of the second transistor, provides a potential matching branch for the inverting input of the first operational amplifier; a second resistor, with its first end electrically connected to the drain of the first transistor and its second end grounded, provides a potential matching branch for the non-inverting input of the first operational amplifier; a third resistor, with its first end electrically connected to the drain of the second transistor, adjusts the potential of the inverting input of the first operational amplifier and the temperature coefficient of the charging current; a first transistor, with its emitter electrically connected to the drain of the first transistor and its collector shorted to its base and grounded, provides a negative temperature coefficient reference voltage; a second transistor, with its emitter electrically connected to the second end of the first resistor and its collector shorted to its base and grounded, generates a positive temperature coefficient voltage difference to counteract the negative temperature coefficient emitter junction voltage.

[0005] The temperature coefficient adjustable current source generation circuit provided by the present invention may also have the following features: wherein the parallel connection multiple of the emitter region of the first transistor is 2, and the parallel connection multiple of the emitter region of the second transistor is 16.

[0006] The temperature coefficient adjustable current source generation circuit provided by the present invention may also have the following feature: wherein the first transistor and the second transistor are PNP transistors.

[0007] The present invention also provides a clock generation circuit, including the temperature coefficient adjustable current source generation circuit as described above, and further comprising: a sawtooth wave generation module for generating a ramp voltage; a voltage comparison and enable control module connected to the sawtooth wave generation module for converting the ramp voltage into a digital signal; a threshold voltage generation module connected to the voltage comparison and enable control module for providing a threshold voltage to the voltage comparison and enable control module; and a logic shaping and trigger module connected to both the sawtooth wave generation module and the voltage comparison and enable control module for signal shaping and output driving, thereby completing the oscillation closed loop.

[0008] The clock generation circuit provided by this invention may also have the following features: the sawtooth wave generation module includes: a first capacitor with its second terminal grounded, used to provide a periodic ramp signal; a first current source with its first terminal connected to a power supply and its second terminal connected to the first terminal of the first capacitor, used to provide a constant charging current; a first switching transistor with its drain connected to the first current source and its source grounded to the substrate; a second capacitor with its second terminal grounded, used to provide a periodic ramp signal; a second current source with its first terminal connected to a power supply and its second terminal connected to the first terminal of the second capacitor, used to provide a constant charging current; and a second switching transistor with its drain connected to the second current source and its source grounded to the substrate.

[0009] The clock generation circuit provided by this invention may also have the following features: the voltage comparison and enable control module includes: a second operational amplifier, the non-inverting input of which is connected to the first terminal of the first capacitor, for generating a digital signal; a third switch, the gate of which receives an enable signal, the drain of which is connected to the output terminal of the second operational amplifier, and the source of which is grounded to the substrate; the third operational amplifier, the non-inverting input of which is connected to the first terminal of the second capacitor, for generating a digital signal; and a fourth switch, the gate of which receives an enable signal, the drain of which is connected to the output terminal of the third operational amplifier, and the source of which is connected to the substrate and the power supply.

[0010] The clock generation circuit provided by this invention may also have the following features: the threshold voltage generation module includes: a fourth resistor, the first end of which is connected to the inverting input terminal of the second operational amplifier and the inverting input terminal of the third operational amplifier respectively, and the second end is grounded, for adjusting the peak value of the sawtooth wave and the frequency of the output clock; and a third current source, the first end of which is connected to the power supply and the second end of which is connected to the first end of the fourth resistor, for providing operating current to the fourth resistor.

[0011] The clock generation circuit provided by this invention may also have the following features: the logic shaping and flip-flop module includes: a first inverter, the input of which is connected to the output of a second operational amplifier, for converting a sawtooth wave into a square wave; an RS flip-flop, the first input of a first NAND gate is connected to the first inverter, the output of the first NAND gate is connected to the first input of a second NAND gate, and the output of the second NAND gate is connected to the second input of the first NAND gate, for implementing output state flipping and holding; a second inverter, the input of which is connected to the output of the first NAND gate of the RS flip-flop, and the output of which is connected to the gate of a first switching transistor, for further smoothing the square wave and converting the signal phase; a third inverter, the input of which is connected to the output of a third operational amplifier, and the output of which is connected to the second input of the second NAND gate of the RS flip-flop, for converting a sawtooth wave into a square wave; and a fourth inverter, the input of which is connected to the output of the second NAND gate of the RS flip-flop, and the output of which is connected to the gate of a second switching transistor, for further smoothing the square wave and converting the signal phase.

[0012] The clock generation circuit provided by this invention may also have the following feature: the clock output frequency calculation formula of the clock generation circuit is:

[0013]

[0014] in, For output frequency, The period of the output clock. The duration of a single capacitor charge. The output current of the first current source or the second current source. The output current of the third current source. This is the resistance value of the fourth resistor. This refers to the capacitance value of either the first or second capacitor.

[0015] The role and effect of invention

[0016] The temperature-coefficient adjustable current source generation circuit and clock generation circuit according to the present invention include: a first operational amplifier for stabilizing the static operating point of the circuit; a first transistor, whose gate is electrically connected to the output terminal of the first operational amplifier, whose source is connected to the positive terminal of the power supply, and whose drain is electrically connected to the non-inverting input terminal of the first operational amplifier, for providing a reference current branch; a second transistor, whose gate is electrically connected to the output terminal of the first operational amplifier, whose source is connected to the positive terminal of the power supply, and whose drain is electrically connected to the inverting input terminal of the first operational amplifier, for providing a reference current branch; a third transistor, whose gate is electrically connected to the output terminal of the first operational amplifier, whose source is connected to the positive terminal of the power supply, and whose drain is a constant current output terminal, for replicating and outputting the charging current; and a first resistor, whose first terminal is electrically connected to the drain of the second transistor, for providing a potential to the inverting input terminal of the first operational amplifier. The circuit comprises a matching branch; a second resistor, with its first end electrically connected to the drain of the first transistor and its second end grounded, used to provide a potential matching branch for the non-inverting input of the first operational amplifier; a third resistor, with its first end electrically connected to the drain of the second transistor, used to adjust the potential of the inverting input of the first operational amplifier and the temperature coefficient of the charging current; a first transistor, with its emitter electrically connected to the drain of the first transistor and its collector shorted to its base and grounded, used to provide a negative temperature coefficient reference voltage; and a second transistor, with its emitter electrically connected to the second end of the first resistor and its collector shorted to its base and grounded, used to generate a positive temperature coefficient voltage difference to offset the negative temperature coefficient emitter junction voltage. Therefore, compared with the use of a crystal oscillator, the temperature coefficient adjustable current source generation circuit and clock generation circuit of the present invention are lower in cost, smaller in size, have shorter startup time, no mechanical components, and have good shock resistance. Attached Figure Description

[0017] Figure 1This is a circuit diagram of the temperature coefficient adjustable current source generation circuit and the clock generation circuit in an embodiment of the present invention.

[0018] Figure 2 This is a circuit diagram of the temperature coefficient adjustable current source generation circuit in an embodiment of the present invention.

[0019] Figure 3 This is a circuit diagram of the clock generation circuit in an embodiment of the present invention. Detailed Implementation

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0021] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the following embodiments, in conjunction with the accompanying drawings, provide a detailed description of the temperature coefficient adjustable current source generation circuit and clock generation circuit of the present invention.

[0022] Example

[0023] Figure 1 This is a circuit diagram of the temperature coefficient adjustable current source generation circuit and the clock generation circuit in an embodiment of the present invention.

[0024] Figure 2 This is a circuit diagram of the temperature coefficient adjustable current source generation circuit in an embodiment of the present invention.

[0025] like Figure 1 and Figure 2 As shown, this embodiment provides a temperature coefficient adjustable current source generation circuit 100, including: a first operational amplifier A1, a first transistor M5, a second transistor M6, a third transistor M7, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, and a second transistor Q2.

[0026] The first operational amplifier A1 is used to stabilize the quiescent operating point of the circuit.

[0027] The gate of the first transistor M5 is electrically connected to the output terminal of the first operational amplifier A1, the source is connected to the positive terminal of the power supply, and the drain is electrically connected to the non-inverting input terminal of the first operational amplifier A1, which is used to provide a reference current branch.

[0028] The gate of the second transistor M6 is electrically connected to the output terminal of the first operational amplifier A1, its source is connected to the positive terminal of the power supply, and its drain is electrically connected to the inverting input terminal of the first operational amplifier A1, which is used to provide a reference current branch.

[0029] The gate of the third transistor M7 is electrically connected to the output terminal of the first operational amplifier A1, its source is connected to the positive terminal of the power supply, and its drain is the constant current output terminal, used to replicate and output the charging current.

[0030] The first terminal of the first resistor R1 is electrically connected to the drain of the second transistor M6, and is used to provide a potential matching branch for the inverting input terminal of the first operational amplifier A1.

[0031] The first end of the second resistor R2 is electrically connected to the drain of the first transistor M5, and the second end is grounded, which is used to provide a potential matching branch for the non-inverting input of the first operational amplifier A1.

[0032] The first terminal of the third resistor R3 is electrically connected to the drain of the second transistor M6, and is used to adjust the potential of the inverting input terminal of the first operational amplifier A1 and the temperature coefficient of the charging current.

[0033] The emitter of the first transistor Q1 is electrically connected to the drain of the first transistor M5, and its collector is shorted to the base and grounded to provide a negative temperature coefficient reference voltage.

[0034] The emitter of the second transistor Q2 is electrically connected to the second terminal of the first resistor R1, and the collector is shorted to the base and grounded. This is used to generate a voltage difference with a positive temperature coefficient to counteract the emitter junction voltage with a negative temperature coefficient.

[0035] The emitter multiple of the first transistor Q1 is 2, and the emitter multiple of the second transistor Q2 is 16. Both transistors Q1 and Q2 are PNP transistors.

[0036] Figure 2 This is a circuit diagram of the clock generation circuit in an embodiment of the present invention.

[0037] like Figure 2 As shown, this embodiment also provides a clock generation circuit 1000, including the temperature coefficient adjustable current source generation circuit 100 as described above, and further including: a sawtooth wave generation module 200, a voltage comparison and enable control module 300, a threshold voltage generation module 400, and a logic shaping and trigger module 500.

[0038] The sawtooth wave generation module 200 is used to generate ramp voltage.

[0039] The sawtooth wave generation module 200 includes: a first capacitor C0, a first current source Icharge1, a first switch M3, a second capacitor C1, a second current source Icharge2, and a second switch M4.

[0040] The second terminal of the first capacitor C0 is grounded to provide a periodic ramp signal.

[0041] The first current source Icharge1 is connected to the power supply at its first terminal and to the first terminal of the first capacitor C0 at its second terminal, and is used to provide a constant charging current.

[0042] The drain of the first switching transistor M3 is connected to the first current source Icharge1, and the source is grounded to the substrate.

[0043] The second capacitor C1 is grounded at its second terminal to provide a periodic ramp signal.

[0044] The first terminal of the second current source Icharge2 is connected to the power supply, and the second terminal is connected to the first terminal of the second capacitor C1, which is used to provide a constant charging current.

[0045] The drain of the second switching transistor M4 is connected to the second current source Icharge2, and the source is grounded to the substrate.

[0046] The voltage comparison and enable control module 300 is connected to the sawtooth wave generation module 200 and is used to convert the ramp voltage into a digital signal.

[0047] The voltage comparison and enable control module 300 includes: a second operational amplifier A3, a third switch M1, a third operational amplifier A4, and a fourth switch M2.

[0048] The non-inverting input of the second operational amplifier A3 is connected to the first terminal of the first capacitor C0 to generate a digital signal.

[0049] The gate of the third switch M1 receives the enable signal, its drain is connected to the output of the second operational amplifier A3, and its source is grounded to the substrate.

[0050] The non-inverting input of the third operational amplifier A4 is connected to the first terminal of the second capacitor C1 to generate digital signals.

[0051] The gate of the fourth switch M2 receives the enable signal, its drain is connected to the output of the third operational amplifier A4, and its source is connected to the substrate and the power supply.

[0052] The threshold voltage generation module 400 is connected to the voltage comparison and enable control module 300 and is used to provide the threshold voltage to the voltage comparison and enable control module 300.

[0053] The threshold voltage generation module 400 includes: a fourth resistor R4 and a third current source Icm.

[0054] The first terminal of the fourth resistor R4 is connected to the inverting input terminal of the second operational amplifier A3 and the inverting input terminal of the third operational amplifier A4, respectively, and the second terminal is grounded. It is used to adjust the peak value of the sawtooth wave and the frequency of the output clock.

[0055] The first terminal of the third current source Icm is connected to the power supply, and the second terminal is connected to the first terminal of the fourth resistor R4, which is used to provide the working current for the fourth resistor R4.

[0056] The logic shaping and trigger module 500 is connected to the sawtooth wave generation module 200 and the voltage comparison and enable control module 300, respectively, for signal shaping and output driving, to complete the oscillation closed loop.

[0057] The logic shaping and trigger module 500 includes:

[0058] The input terminal of the first inverter G1 is connected to the output terminal of the second operational amplifier A3, and is used to convert the sawtooth wave into a square wave.

[0059] In the RS flip-flop, the first input terminal of the first NAND gate N1 is connected to the first inverter G1, the output terminal of the first NAND gate N1 is connected to the first input terminal of the second NAND gate N2, and the output terminal of the second NAND gate N2 is connected to the second input terminal of the first NAND gate N1, which is used to realize the output state flipping and holding.

[0060] The input of the second inverter G2 is connected to the output of the first NAND gate N1 of the RS flip-flop, and the output is connected to the gate of the first switching transistor M3, which is used to further smooth the square wave and convert the signal phase.

[0061] The input of the third inverter G3 is connected to the output of the third operational amplifier A4, and the output is connected to the second input of the second NAND gate N2 of the RS flip-flop, which is used to convert the sawtooth wave into a square wave.

[0062] The input of the fourth inverter G4 is connected to the output of the second NAND gate N2 of the RS flip-flop, and the output is connected to the gate of the second switch M4, which is used to further smooth the square wave and convert the signal phase.

[0063] The formula for calculating the clock output frequency of the clock generation circuit is as follows:

[0064]

[0065] in, For output frequency, The period of the output clock. The duration of a single capacitor charge. The output current of the first current source or the second current source. The output current of the third current source. This is the resistance value of the fourth resistor. This refers to the capacitance value of either the first capacitor C0 or the second capacitor C1. In this embodiment, the first current source Icharge1 and the second current source Icharge2 are equal.

[0066] The working principle of the temperature coefficient adjustable current source generation circuit and the clock generation circuit in this embodiment is as follows:

[0067] In the temperature-coefficient adjustable current source generation circuit, the sources of the first transistor M5, the second transistor M6, and the third transistor M7 are connected to the same power supply, and their gates are connected to the output of the first operational amplifier A1, forming a common-gate current mirror. The same gate voltage output by the first operational amplifier A1 ensures that the gate-source voltages Vgs of the three transistors are completely identical. When the channel width-to-length ratio is matched, the drain current can be precisely replicated proportionally. The first transistor M5 and the second transistor M6 provide matching currents for the two branches of the non-inverting and inverting inputs of the operational amplifier, respectively, and the rightmost third transistor M7 outputs charging current to the clock generation circuit.

[0068] Both transistors Q1 and Q2 are diodes with their collectors and bases shorted, and their collectors are grounded to provide a negative temperature coefficient of Vbe / R1.

[0069] The first transistor Q1 and the second transistor Q2 are connected in parallel with different multiples m, which generates a positive temperature coefficient emitter-junction voltage difference ΔVbe / R2. By using different ratios of R1:R2, a current source with zero temperature coefficient, a current source with positive temperature coefficient, and a current source with negative temperature coefficient can be generated.

[0070] In the clock generation circuit, the third current source Icm flows through resistor R, generating a fixed reference voltage Vcm, which provides a unified switching threshold for the two operational amplifiers. The two completely symmetrical charging and discharging branches provide constant charging currents to the first capacitor C0 and the second capacitor C1 respectively through the first current source Icharge1 and the second current source Icharge2, causing the capacitor voltage to rise linearly. The first switch M3 and the second switch M4 act as controlled discharge switches, controlled by the output signal of the RS flip-flop, to achieve nanosecond-level rapid discharge and reset of the corresponding capacitors.

[0071] When the charging voltage of a capacitor exceeds the threshold Vcm, the corresponding operational amplifier (comparator) output rapidly flips, generating a digital switching signal that triggers the cross-coupled RS flip-flop to switch its output state. After the RS flip-flop flips, it synchronously switches the operating state of the two branches. The branch that has completed charging turns on its discharge tube and quickly resets, while the other branch turns off its discharge tube and enters the charging stage, thus forming a continuous alternating cycle. After the RS flip-flop output is shaped and buffered by an inverter, the final output clock has a turns-to-space ratio close to 1:1, making the output frequency more accurate.

[0072] The role and effect of the embodiments

[0073] The temperature-coefficient adjustable current source generation circuit and clock generation circuit involved in this embodiment include: a first operational amplifier for stabilizing the static operating point of the circuit; a first transistor, with its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain electrically connected to the non-inverting input terminal of the first operational amplifier, for providing a reference current branch; a second transistor, with its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain electrically connected to the inverting input terminal of the first operational amplifier, for providing a reference current branch; a third transistor, with its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain as a constant current output terminal, for replicating and outputting the charging current; and a first resistor, with its first terminal electrically connected to the drain of the second transistor, for providing a potential to the inverting input terminal of the first operational amplifier. The circuit comprises a matching branch; a second resistor, with its first end electrically connected to the drain of the first transistor and its second end grounded, used to provide a potential matching branch for the non-inverting input of the first operational amplifier; a third resistor, with its first end electrically connected to the drain of the second transistor, used to adjust the potential of the inverting input of the first operational amplifier and the temperature coefficient of the charging current; a first transistor, with its emitter electrically connected to the drain of the first transistor and its collector shorted to its base and grounded, used to provide a negative temperature coefficient reference voltage; and a second transistor, with its emitter electrically connected to the second end of the first resistor and its collector shorted to its base and grounded, used to generate a positive temperature coefficient voltage difference to offset the negative temperature coefficient emitter junction voltage. Therefore, compared with the use of a crystal oscillator, the temperature coefficient adjustable current source generation circuit and clock generation circuit of the present invention are lower in cost, smaller in size, have shorter startup time, no mechanical components, and have good shock resistance.

[0074] In this embodiment, the temperature coefficient adjustable current source generation circuit and the clock generation circuit match the temperature characteristics of the charging current and the threshold current, and the output clock frequency hardly drifts with temperature in the entire temperature range, with stability far exceeding that of traditional temperature-compensated RC oscillators.

[0075] All modules in this embodiment can be integrated on a single chip, eliminating the need for external crystal oscillators, resonant cavities, and compensation capacitors. This results in low cost, small size, and no risk of vibration failure, making it suitable for high-reliability scenarios such as automotive, industrial, and mobile terminals.

[0076] In this embodiment, the operational amplifier output is steepened and shaped by an inverter to eliminate the gradual transition and noise, resulting in a purer oscillation frequency and less jitter.

[0077] Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to this invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A temperature-coefficient adjustable current source generation circuit, characterized in that, include: The first operational amplifier is used to stabilize the quiescent operating point of the circuit. The first transistor has its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain electrically connected to the non-inverting input terminal of the first operational amplifier, and is used to provide a reference current branch. The second transistor has its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain electrically connected to the inverting input terminal of the first operational amplifier, and is used to provide a reference current branch. The third transistor has its gate electrically connected to the output terminal of the first operational amplifier, its source connected to the positive terminal of the power supply, and its drain as a constant current output terminal, used to replicate and output the charging current. The first resistor, with its first end electrically connected to the drain of the second transistor, is used to provide a potential matching branch for the inverting input of the first operational amplifier. The second resistor has its first end electrically connected to the drain of the first transistor and its second end grounded, and is used to provide a potential matching branch for the non-inverting input of the first operational amplifier. The third resistor, with its first end electrically connected to the drain of the second transistor, is used to adjust the potential of the inverting input of the first operational amplifier and the temperature coefficient of the charging current. The first transistor has its emitter electrically connected to the drain of the first transistor, and its collector shorted to its base and grounded, in order to provide a negative temperature coefficient reference voltage. The second transistor has its emitter electrically connected to the second end of the first resistor, and its collector short-circuited to the base and grounded. This is used to generate a voltage difference with a positive temperature coefficient to counteract the emitter-junction voltage with a negative temperature coefficient.

2. The temperature coefficient adjustable current source generation circuit according to claim 1, characterized in that: in, The parallel connection multiple of the emitter region of the first transistor is 2, and the parallel connection multiple of the emitter region of the second transistor is 16.

3. The temperature coefficient adjustable current source generation circuit according to claim 1, characterized in that: in, The first transistor and the second transistor are PNP transistors.

4. A clock generation circuit, comprising the temperature coefficient adjustable current source generation circuit as described in claims 1-3, characterized in that, Also includes: Sawtooth wave generation module, used to generate ramp voltage; A voltage comparison and enable control module, connected to the sawtooth wave generation module, is used to convert the ramp voltage into a digital signal; A threshold voltage generation module, connected to the voltage comparison and enable control module, is used to provide a threshold voltage for the voltage comparison and enable control module; The logic shaping and trigger module is connected to the sawtooth wave generation module and the voltage comparison and enable control module, respectively, and is used for signal shaping and output driving to complete the oscillation closed loop.

5. The clock generation circuit according to claim 1, Its features are: The sawtooth wave generation module includes: The first capacitor has its second terminal grounded, and it is used to provide a periodic ramp signal. The first current source has a first end connected to the power supply and a second end connected to the first end of the first capacitor, and is used to provide a constant charging current. The first switching transistor has its drain connected to the first current source and its source grounded to the substrate. The second capacitor, with its second terminal grounded, is used to provide a periodic ramp signal; The second current source has its first end connected to the power supply and its second end connected to the first end of the second capacitor, and is used to provide a constant charging current. The drain of the second switching transistor is connected to the second current source, and the source is grounded to the substrate.

6. The clock generation circuit according to claim 5, Its features are: The voltage comparison and enable control module includes: The second operational amplifier has its non-inverting input connected to the first terminal of the first capacitor, and is used to generate digital signals. The third switch has an enable signal at its gate, its drain connected to the output of the second operational amplifier, and its source grounded to the substrate. The third operational amplifier has its non-inverting input connected to the first terminal of the second capacitor, and is used to generate digital signals. The fourth switch receives an enable signal at its gate, its drain is connected to the output of the third operational amplifier, and its source is connected to the substrate and the power supply.

7. The clock generation circuit according to claim 6, Its features are: The threshold voltage generation module includes: The fourth resistor has its first end connected to the inverting input of the second operational amplifier and the inverting input of the third operational amplifier, respectively, and its second end grounded. It is used to adjust the peak value of the sawtooth wave and the frequency of the output clock. The third current source has its first end connected to the power supply and its second end connected to the first end of the fourth resistor, and is used to provide operating current to the fourth resistor.

8. The clock generation circuit according to claim 7, Its features are: The logic shaping and trigger module includes: The first inverter, whose input is connected to the output of the second operational amplifier, is used to convert a sawtooth wave into a square wave. An RS flip-flop has a first input terminal of a first NAND gate connected to the first inverter, an output terminal of the first NAND gate connected to the first input terminal of a second NAND gate, and an output terminal of the second NAND gate connected to the second input terminal of the first NAND gate, used to achieve output state flipping and holding. The second inverter has its input terminal connected to the output terminal of the first NAND gate of the RS flip-flop, and its output terminal connected to the gate of the first switching transistor, and is used to further smooth the square wave and convert the signal phase. The third inverter has its input terminal connected to the output terminal of the third operational amplifier and its output terminal connected to the second input terminal of the second NAND gate of the RS flip-flop. It is used to convert a sawtooth wave into a square wave. The fourth inverter has its input connected to the output of the second NAND gate of the RS flip-flop, and its output connected to the gate of the second switching transistor, and is used to further smooth the square wave and convert the signal phase.

9. The clock generation circuit according to claim 8, characterized in that: in, The formula for calculating the clock output frequency of the clock generation circuit is as follows: in, For output frequency, The period of the output clock. The duration of a single capacitor charge. The output current of the first current source or the second current source. The output current of the third current source. The resistance value of the fourth resistor is... The capacitance value is the value of the first capacitor or the second capacitor.

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