Imaging circuit and method for operating an imaging circuit

Abstract

The present disclosure relates generally to imaging circuitry, comprising: a first semiconductor layer comprising: a photodiode; a global shutter memory node for a global shutter mode; and a first pass gate coupled between the photodiode and the global shutter memory node; and a second pass gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer comprising the pixel amplifier; and a third semiconductor layer comprising analog-to-digital conversion circuitry.

Description

Technical Field

[0001] This disclosure generally relates to imaging circuits and methods for operating imaging circuits in the field of charge domain global / rolling shutter operation. Background Technology

[0002] Typically, global shutter operation of image sensors is known. In this operation, the exposure for each row of pixels remains (approximately) the same for each row, and the readout for each row is delayed after a rolling readout, where the pixel amplifier acts as a charge buffer before performing readout in the voltage domain.

[0003] It is possible to distinguish between charge-domain global shutters (CD-GS; also known as floating diffusion global shutters FD-GS) and voltage-domain global shutters (VD-GS). In charge-domain global shutters, readouts can occur in the charge domain. In voltage-domain global shutters, readouts can occur in the voltage domain.

[0004] Moreover, Correlated double sampling (CDS) is known, which refers to sampling a signal twice to perform differential measurements and eliminating all correlated noise that appears in each measurement in the same way by subtracting the two measurements.

[0005] Although techniques exist for global shutter operation, it is generally desirable to provide imaging circuitry and methods for operating the imaging circuitry. Summary of the Invention

[0006] According to a first aspect, this disclosure provides an imaging circuit comprising: The first semiconductor layer includes: Photodiode; Global shutter memory node, used for global shutter mode; and A first transmission gate is connected between the photodiode and the global shutter memory node; and The second transmission gate is connected between the global shutter memory node and the pixel amplifier in the second semiconductor layer; The second semiconductor layer includes a pixel amplifier; and The third semiconductor layer includes analog-to-digital conversion circuitry.

[0007] According to a second aspect, this disclosure provides a method for operating an imaging circuit, the imaging circuit comprising: The first semiconductor layer includes: Photodiode; Global shutter memory node, used for global shutter mode; and A first transmission gate is connected between the photodiode and the global shutter memory node; and The second transmission gate is connected between the global shutter memory node and the pixel amplifier in the second semiconductor layer; The second semiconductor layer includes a pixel amplifier; and The third semiconductor layer includes analog-to-digital conversion circuitry. The method includes: Executes either global shutter mode or rolling shutter mode based on a predetermined signaling sequence.

[0008] Other aspects are set forth in the dependent claims, the drawings and the following description. Attached Figure Description

[0009] Referring to the accompanying drawings, the implementation method is illustrated by example, wherein: Figure 1 depicts an image sensor configured for a rolling shutter and also for a charge domain global shutter (in some embodiments, without correlated double sampling capability), wherein Figure 1a The sensor is depicted as a circuit diagram, and Figure 1b This describes how the sensors are stacked; Figure 2 A pixel circuit configured for a charge domain global shutter is depicted, which also has the capability for correlated double sampling; Figure 3 depicts an image sensor configured for a voltage-domain global shutter, in which... Figure 3a The sensor is depicted as a circuit diagram, and Figure 3b This describes how the sensors are stacked; Figure 4 depicts an imaging circuit according to the present disclosure for a charge-domain global shutter with correlated double sampling (and in some embodiments, high dynamic range capability), wherein Figure 4a The sensor is depicted as a circuit diagram. Figure 4b It describes how the sensors are stacked; Figure 5 illustrates the timing diagram for controlling the imaging circuit of Figure 4 to execute the global shutter mode. Figure 5a , Figure 5b , Figure 5c ); Figure 6 depicts a timing diagram for controlling the imaging circuit of Figure 4 to execute the rolling shutter mode. Figure 6a , Figure 6b , Figure 6c ); Figure 7 A method for controlling an imaging circuit according to the present disclosure is described; Figure 8 Another method for controlling the imaging circuitry according to this disclosure to perform a rolling shutter mode is described; and Figure 9Another method for controlling the imaging circuitry according to this disclosure to perform correlated double sampling during global shutter mode is described. Detailed Implementation

[0010] Before giving a detailed description of the implementation method starting from Figure 4, a general description will be given.

[0011] Figure 1 depicts the image sensor. Figure 1a The diagram shows a circuit diagram of the image sensor for pixel 1. The image sensor includes a stacked first wafer 2 and a second wafer 3 (see also...). Figure 1b The first wafer 2 includes pixel circuitry. It should be noted that the pinned photodiode (PPD) generates charge, which is transmitted via the transfer gate TRG / M. TX Transferred to memory node (floating diffusion) FD1. TRG and M TX They refer to the same device, where TRG stands for transmission gate and refers to the signal, while M... TX This represents the MOS transistor activated when TRG is high. Floating diffusion FD1 represents the readout holding charge. M FDG It is configured to short FD1 and FD2 when FDG goes high. RST is a reset transistor, configured to clear charge from PPD, FD1, and FD2. M SF It is a source follower, configured as an amplifier in the pixel. M SEL It is a selection transistor, configured to connect the pixel to the readout circuit when SEL goes high.

[0012] The second wafer 3 includes an analog-to-digital converter (ADC) circuit, which includes a ramp generator and a comparator. Additionally, the second wafer 3 includes digital image signal processing (ISP) circuitry. The image sensor 1 is configured to operate in global shutter (GS) mode, i.e., biasing each pixel row with the same value during readout.

[0013] As from Figure 1b As can be seen, wafers 2 and 3 are stacked so that a pixel is set on the first wafer 2 and the pixel can be read out based on the ADC and ISP circuits of the second wafer 3.

[0014] However, in image sensor 1, correlated double sampling (CDS) cannot be performed in global shutter mode, resulting in high readout noise for the pixels of image sensor 1. This is likely because, without memory nodes, it may be impossible to perform global exposure (global shutter) while sequentially reading line by line, and to eliminate noise from the reset phase of each pixel. Furthermore, pixel performance optimization may be limited by other pixel transistors, as if many transistors are too close together, they may introduce impurities into the silicon and limit the performance of the photodiode.

[0015] However, the image sensor 1 provides enough space on the second wafer to allow the ISP circuitry to be implemented on the chip (instead of on another chip).

[0016] To allow for a global shutter and CDS in the charge domain, additional transmission gates and additional memory nodes may be required, and these additional memory nodes can be roughly the size of the pixel size (PPD). Such a known pixel circuit 10... Figure 2 As shown.

[0017] Pixel circuit 10 includes an additional memory node FD preceding memory node FD1. GS and additional transmission gate M TX1 This enables CDS.

[0018] However, it has been recognized that these pixels are quite large and therefore unsuitable for small-pitch production.

[0019] With reference to Figure 1 and Figure 2 In contrast to the charge domain method discussed, the voltage domain method is shown in Figure 3. Figure 3a A circuit diagram depicts the pixels disposed on the first wafer 20 and the readout circuit disposed on the second wafer 21.

[0020] from Figure 3b As can be seen, the second wafer 21 includes CDS circuitry and ADC circuitry. Therefore, this implementation does not leave room for ISP (Image Signal Processing) circuitry. Furthermore, readout noise depends on capacitor size, making scaling this implementation challenging.

[0021] When a voltage domain GS with CDS is enabled, readout noise can depend on the capacitor size. Furthermore, CDS capacitors may be directly exposed to light, which is considered undesirable. Some embodiments of this disclosure can address or mitigate these problems.

[0022] Typically, for a charge-domain global shutter (CD-GS; also known as a floating diffusion global shutter), the noise in electron form can be determined as follows:

[0023] On the other hand, for voltage-domain global shutter (VD-GS), the noise expressed in volts can be determined as follows:

[0024] In these equations, k refers to Boltzmann's constant, T is the temperature in Kelvin, C is the capacitance at the node used to calculate noise, and q is the electron charge.

[0025] In the charge domain, capacitance is in the numerator of the above expression, but in the denominator of the voltage domain expression. Therefore, in the charge domain, the smaller the capacitor, the lower the noise. This noise can be completely or almost completely eliminated using CDS. On the other hand, in the voltage domain, the smaller the capacitor, the higher the noise. Furthermore, noise may not be completely eliminated because sampling may introduce new, potentially irrelevant, noise.

[0026] Therefore, it has been recognized that there is a desire to provide a charge domain global shutter imaging circuit capable of CDS, and that this circuit also provides the possibility of implementing on-chip image signal processing circuitry.

[0027] Therefore, some implementations relate to an imaging circuit including: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transmission gate connected between the photodiode and the global shutter memory node; and a second transmission gate connected between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including an analog-to-digital converter circuit.

[0028] The imaging circuit may include a single pixel or an array of pixels, and is therefore suitable for use as an image sensor. The individual semiconductor layers (e.g., wafers) may include any type of semiconductor, such as those based on CMOS (Complementary Metal-Oxide-Semiconductor) technology, NMOS (n-type Metal-Oxide-Semiconductor) technology, etc. In some embodiments, a mixture of different semiconductor types may be used. For example, the first semiconductor layer may be based on CMOS technology and the second semiconductor layer may be based on NMOS technology. This disclosure is not limited to any type of semiconductor layer. For example, as described above, a wafer may be such a layer, and this disclosure is not limited in this respect. Semiconductor layers may be bonded together by electrical connections, interconnections within or between layers, etc.

[0029] In the first semiconductor layer, a pixel circuit including a photodiode, a global shutter memory node, and two transmission gates can be provided. The first transmission gate can be connected between the photodiode and the global shutter memory node. The second transmission gate can be connected between the global shutter memory node and an amplifier in the second semiconductor layer.

[0030] For example, Figure 2 The depicted circuitry can be distributed across a first semiconductor layer and a second semiconductor layer, such that the second semiconductor layer may include high dynamic range (HDR) circuitry. Therefore, the second semiconductor layer may include pixel amplifiers, as will be discussed further below.

[0031] In addition, the third semiconductor layer may include an ADC for reading out signals.

[0032] As described above, in some embodiments, the first semiconductor layer is configured for correlated double sampling, as will be discussed below.

[0033] In some implementations, correlated double sampling is performed based on a global shutter memory node and a photodiode, as will be discussed further below.

[0034] In some implementations, the second semiconductor layer further includes a reset transistor and an optional gain stage.

[0035] In some implementations, the third semiconductor layer also includes image signal processing circuitry. Therefore, the ISP circuitry can be located on the same chip as the pixel.

[0036] In some implementations, the imaging circuit is also configured to switch between a global shutter mode and a rolling shutter mode based on switching a first transmission gate.

[0037] For example, if the first transmission gate remains high during the acquisition period, then a rolling shutter can be enabled, as will be discussed further below.

[0038] In some implementations, the imaging circuit is also configured to activate a global shutter mode by activating a first transmission gate using a predetermined signaling sequence, as will be discussed further below.

[0039] In some implementations, the second semiconductor layer is configured for high dynamic range operation, as discussed herein.

[0040] In some implementations, the second semiconductor layer further includes at least one conversion gain stage.

[0041] In some implementations, the second semiconductor layer is an NMOS semiconductor.

[0042] For example, NMOS technology can be applied only (without PMOS technology) to reduce leakage in the second semiconductor layer.

[0043] In some embodiments, the first semiconductor layer further includes a photosensitive device. Thus, the photosensitive device can be exposed to light, while other devices in the second and third semiconductor layers can shield the light.

[0044] In some implementations, the rolling shutter mode is activated based on one acquisition cycle of the first transmission gate being turned on, as discussed herein.

[0045] Some implementations relate to a method for operating an imaging circuit including: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transmission gate connected between the photodiode and the global shutter memory node; and a second transmission gate connected between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including an analog-to-digital conversion circuit, the method including: executing a global shutter mode or a rolling shutter mode based on a predetermined signaling sequence, as discussed herein.

[0046] In some embodiments, the rolling shutter mode is activated based on opening the first transmission gate for one acquisition cycle, as discussed herein. In some embodiments, the method further includes performing correlated double sampling in global shutter mode, as discussed herein. In some embodiments, correlated double sampling is performed based on a global shutter memory node and a photodiode, as discussed herein. In some embodiments, the third semiconductor layer further includes image signal processing circuitry, as discussed herein. In some embodiments, the second semiconductor layer is configured for high dynamic range operation, as discussed herein. In some embodiments, the second semiconductor layer further includes at least one conversion gain stage, as discussed herein. In some embodiments, the second semiconductor layer is an NMOS semiconductor, as discussed herein. In some embodiments, the first semiconductor layer further includes a photosensitive device, as discussed herein.

[0047] The methods described herein are also implemented as a computer program in some embodiments, causing the computer and / or processor to perform the method when executed on a computer and / or processor. In some embodiments, a non-transitory computer-readable recording medium is also provided, in which a computer program product is stored, causing the methods described herein to be executed when the computer program product is executed by a processor (such as the processor described above).

[0048] Referring back to Figure 4, a schematic diagram of the imaging circuit 30 according to the present disclosure is depicted. The imaging circuit 30 includes three semiconductor layers (wafers) 31, 32, and 33.

[0049] The first semiconductor layer 31 includes a pixel circuit, which includes a photodiode PPD connected to a first transmission gate TRG1 and an overflow gate OFG, wherein the overflow gate OFG also provides a pixel voltage PIX_V. DD The transmission gate TRG1 is connected to the global shutter memory node FD. GS It is also connected to the second transmission gate TRG2.

[0050] Specifically, the source of the first transmission gate TRG1 is connected to the output of the photodiode PPD, and the drain is connected to the global shutter memory node FD. GS Connections. The source of the overflow gate OFG is connected to the output of the photodiode PPD, and the drain is connected to the pixel voltage PIX_V. DD Connection. Therefore, the global shutter memory node FD GS It is located between the drain of the first transmission gate TRG1 and the source of the second transmission gate TRG2.

[0051] The drain of the second transmission gate TRG2 is connected to a pixel amplifier disposed in the second semiconductor layer 32. It should be noted that any type of amplifier circuit can be used, and Figure 4a The amplifiers depicted herein are merely exemplary features.

[0052] transistor M in the amplifier SF The gate of [the gate] is connected to the drain of the second transmission gate TRG2. Furthermore, [the gate] is connected to M... SF The drain provides the pixel voltage PIX_V DD Its source is connected to the select transistor SEL.

[0053] Furthermore, the second semiconductor layer 32 includes multiple conversion gain stages, each comprising a transistor (FDG1, FDG2) and a capacitor. Additionally, a reset transistor RST is provided, which is supplied with the pixel voltage PIX_V. DD .

[0054] The source of the selection transistor SEL is connected to a capacitor disposed in the third semiconductor layer 33, which in turn is connected to a comparator configured to compare the output of the selection transistor with a ramp signal generated in a ramp generator disposed in the third semiconductor layer 33 (connected to the comparator via a capacitor). Furthermore, a counter CN connected to the ISP circuitry is provided after the comparator.

[0055] Figure 4b An exemplary diagram of stacked imaging circuitry 30 is depicted, illustrating pixel circuitry in a first semiconductor layer 31 stacked on a second semiconductor layer 32, the second semiconductor layer 32 including HDR circuitry stacked on a third semiconductor layer 33, the third semiconductor layer 33 including ADC circuitry and ISP circuitry, as discussed above. It should be noted that this disclosure is not limited to stacked image sensors, as any type of interconnected image circuitry can be conceived by those skilled in the art based on this disclosure.

[0056] Therefore, global shutter operation can be performed simultaneously with CDS. Furthermore, the ISP circuitry can be located on the chip. Similarly, as discussed herein, the photodiode PPD and the global shutter memory node FD are connected via the first transmission gate TRG1.GS Shorting the circuit allows for a rolling shutter.

[0057] It should be noted that some implementations involve global shutter (GS) and / or rolling shutter (RS) pixels, including: a photodiode (PPD); circuitry configured for correlated double sampling (CDS) in the case of global shutter; circuitry including the pixel amplifier and multiple conversion gain stages; and circuitry configured to convert analog pixel information into digital and perform on-chip signal processing. Implementations also include operating circuitry to provide corresponding methods for GS mode and / or RS mode.

[0058] In user devices such as cameras or mobile phones, image sensors including the aforementioned pixels can provide a user interface that enables the selection of a global shutter mode or a rolling shutter mode. The global shutter mode may be preferred for image quality, while the rolling shutter mode is preferred for saving battery power. The global shutter mode or the rolling shutter mode may be selected by the user or by the device algorithmically based on one or more of the following: (i) battery power, (ii) the field of view of the device's camera, (iii) ambient lighting, and (iv) whether a flash is used. More generally, the algorithm may determine whether the device's conditions or current operating settings would benefit from using the global shutter rather than the rolling shutter to provide a higher quality or less noisy output image, which is not limited to this. It should also be noted that the global shutter according to this disclosure may be additionally or alternatively used to obtain images free of motion artifacts and / or images synchronized with external light sources. The rolling shutter according to this disclosure can be used for imaging at a fast frame rate. The rolling shutter and global shutter according to this disclosure can be used for high dynamic range and low noise imaging.

[0059] Embodiments of this disclosure provide a hybrid global shutter / rolling shutter circuit.

[0060] In some implementations, the CDS function resides on a different wafer than the pixel amplifier and the multiple conversion gain stages (FDG1, FDG2, FD2, FD3). It should be noted that the conversion gain stages may be based on FD2 and FD3, but this disclosure is not limited in this respect, as it may be based solely on FD2 or on more floating diffusion than FD2 and FD3.

[0061] In some implementations, a global shutter with CDS (GS) or rolling shutter (RS) is selected by switching TRG1. In some implementations, switching transistor TRG1 causes transistor TRG1 (i.e., FD) to... GS Shorted with PPD. In some implementations, switching or shorting TRG1 maximizes or combines the effects across PPD and FD. GSThe capacitor allows for the use of a rolling shutter mode with a larger capacity than the global shutter mode, which further enhances the dynamic range.

[0062] In some implementations, the global shutter (GS) and / or rolling shutter (RS) pixels include circuitry located on two or three different wafer layers.

[0063] In some implementations, the global shutter mode is activated by activating TRG1 using a predetermined sequence.

[0064] In some embodiments, the first wafer includes a photodiode, a memory node, a first transmission gate between the photodiode and the memory node, and a second transmission gate between the memory node and the second wafer.

[0065] In some implementations, the first wafer also includes silicon, implants, trench isolation, color filters, and only one metal layer.

[0066] In some implementations, the pixel amplifier and multiple conversion gain stages are moved from the first wafer to the second wafer, thereby optimizing the performance of the photodiode.

[0067] In some implementations, the second wafer includes a pixel amplifier and a multi-conversion gain stage.

[0068] In some implementations, the second wafer includes only NMOS (but not PMOS).

[0069] In some implementations, the third wafer is a CMOS wafer.

[0070] Some implementations relate to methods for controlling imaging circuits as discussed herein.

[0071] In some implementations, the method includes executing a global shutter mode.

[0072] In some implementations, a global shutter mode is executed based on activating the first and second transmission gates in a predetermined timing sequence. This will also be referenced. Figure 5a Let's have a discussion.

[0073] In some implementations, the predetermined timing includes controlling a first transmission gate as a global shutter and a second transmission gate as a rolling shutter.

[0074] In some implementations, at the end of the exposure phase, the first transmission gate is set high (and then set low again), and the second transmission gate is set high during the readout phase following the exposure phase.

[0075] Figure 5a A timing diagram 40 for global shutter mode according to this disclosure is depicted.

[0076] During reset / shutter mode 41, pulses are applied to the bases of transistors RST, FDG, TRG1, and TRG2. Then, at the end of exposure phase 42, a further pulse is applied to the base of TRG1, after which readout phase 43 begins.

[0077] During the readout phase, firstly, while FDG is set high for a predetermined time, a pulse is applied to the reset transistor. Shortly thereafter, the signal on SEL is set high for a predetermined time (longer than the FDG signal). When SEL is set low again, a pulse is applied to TRG2. Subsequently, SEL is set high again, and when it is set low again, FDG is simultaneously set high, and shortly thereafter, a further pulse is applied to TRG2.

[0078] Therefore, it is possible to achieve based on Figure 5b The readout is shown. The black lines depict the exposure being constant in the first and second cycles, while the buffer time (dashed lines) increases in each cycle, and the readout (shaded lines) is therefore delayed for each cycle, so that each row of pixels can be read out after the next. Similarly, Figure 5c Constant exposure and delayed readout for five exemplary pixel rows are described, but this disclosure is not limiting in this respect.

[0079] Figure 6a A timing diagram 50 for rolling shutter mode according to this disclosure is depicted, which differs from timing diagram 40 in that the signal TRG1 is set high for one cycle. Therefore, from Figure 6b and Figure 6c As can be seen, without using a buffer, the exposure and readout of each line are delayed.

[0080] Figure 7 A method 70 for operating an imaging circuit according to this disclosure is described. The method includes, at 71, executing a global shutter mode or a rolling shutter mode, as discussed herein, based on a predetermined signaling sequence.

[0081] Figure 8 A method 80 for operating an imaging circuit according to this disclosure is described. At 81, a transmission gate is turned on, thereby shorting the photodiode to the global shutter memory node for one acquisition cycle, such that at 82, RS mode is executed.

[0082] Figure 9 A method 90 for operating an imaging circuit according to this disclosure is described. At 91, a global shutter mode is executed. Simultaneously, at 92, a CDS is executed, as discussed herein.

[0083] It should be understood that the embodiments describe a method with an exemplary sequence of method steps. However, the specific order of the method steps is given for illustrative purposes only and should not be construed as limiting. For example, the order can be interchanged. Figure 9 The order of steps 91 and 92 in the implementation method. Other variations in the order of method steps will be apparent to those skilled in the art.

[0084] Please note that the division of the ADC and ISP circuits in the third semiconductor layer is for illustrative purposes only, and this disclosure is not limited to any specific functional division into specific units. For example, the units in the third semiconductor layer can be implemented by corresponding programming processors, field-programmable gate arrays (FPGAs), etc.

[0085] In some embodiments, a non-transitory computer-readable recording medium is also provided, which stores a computer program product that, when executed by a processor (such as the processor described above), causes the methods described herein to be performed.

[0086] Unless otherwise stated, all units and entities described in this specification and claimed in the appended claims may be implemented as integrated circuit logic, for example, on a chip, and unless otherwise stated, the functionality provided by these units and entities may be implemented by software.

[0087] With regard to the implementation of the embodiments of the present disclosure at least in part using a software-controlled data processing apparatus, it should be understood that providing such a software-controlled computer program and the transmission, storage or other medium through which such a computer program is provided are contemplated as aspects of the present disclosure.

[0088] It should be understood that, for clarity, the above description has described embodiments with reference to different functional units, circuits, and / or processors. However, it will be apparent that any suitable functional distribution can be used among the different functional units, circuits, and / or processors without departing from the embodiments.

[0089] The described embodiments can be implemented in any suitable form, including hardware, software, firmware, or any combination thereof. The described embodiments can optionally be implemented, at least in part, as computer software running on one or more data processors and / or digital signal processors. Elements and components of any embodiment can be implemented physically, functionally, and logically in any suitable manner. In practice, functionality can be implemented in a single unit, in multiple units, or as part of other functional units. Therefore, the disclosed embodiments can be implemented in a single unit or can be physically and functionally distributed among different units, circuits, and / or processors.

[0090] Although this disclosure has been described in conjunction with some embodiments, it is not intended to be limited to the specific forms set forth herein. Furthermore, while features may appear to be described in conjunction with particular embodiments, those skilled in the art will recognize that the various features of the described embodiments can be combined in any manner suitable for implementing the technology.

[0091] It should be noted that this technology can also be configured as described below.

[0092] (1) An imaging circuit, comprising: The first semiconductor layer includes: Photodiode; Global shutter memory node, used for global shutter mode; and The first transmission gate is connected between the photodiode and the global shutter memory node; and The second transmission gate is connected between the global shutter memory node and the pixel amplifier in the second semiconductor layer; The second semiconductor layer includes a pixel amplifier; and The third semiconductor layer includes analog-to-digital conversion circuitry.

[0093] (2) According to the imaging circuit of (1), wherein the first semiconductor layer is configured for correlated double sampling.

[0094] (3) According to the imaging circuit of (2), correlation double sampling is performed based on the global shutter memory node and photodiode.

[0095] (4) An imaging circuit according to any one of (1) to (3), wherein the third semiconductor layer further includes an image signal processing circuit.

[0096] (5) The imaging circuit according to any one of (1) to (4) is also configured to switch between global shutter mode and rolling shutter mode based on switching the first transmission gate.

[0097] (6) The imaging circuit according to any one of (1) to (5) is also configured to activate the global shutter mode by activating the first transmission gate with a predetermined signaling sequence.

[0098] (7) An imaging circuit according to any one of (1) to (6), wherein the second semiconductor layer is configured for high dynamic range operation.

[0099] (8) An imaging circuit according to any one of (1) to (7), wherein the second semiconductor layer further includes at least one conversion gain stage.

[0100] (9) An imaging circuit according to any one of (1) to (8), wherein the second semiconductor layer is an NMOS semiconductor.

[0101] (10) An imaging circuit according to any one of (1) to (9), wherein the first semiconductor layer further includes a photosensitive device.

[0102] (11) An imaging circuit according to any one of (1) to (10), wherein the rolling shutter mode is activated based on one acquisition cycle of the first transmission gate being turned on.

[0103] (12) A method for operating an imaging circuit, the imaging circuit comprising: The first semiconductor layer includes: Photodiode; Global shutter memory node, used for global shutter mode; and The first transmission gate is connected between the photodiode and the global shutter memory node; and The second transmission gate is connected between the global shutter memory node and the pixel amplifier in the second semiconductor layer; The second semiconductor layer includes a pixel amplifier; and The third semiconductor layer includes analog-to-digital conversion circuitry. The method includes: Executes either global shutter mode or rolling shutter mode based on a predetermined signaling sequence.

[0104] (13) According to the method of (12), the rolling shutter mode is activated based on the first transmission gate being turned on for one acquisition cycle.

[0105] (14) According to the method of (12) or (13), it also includes: Perform related double sampling in global shutter mode.

[0106] (15) According to the method of (14), in which correlated double sampling is performed based on the global shutter memory node and photodiode.

[0107] (16) The method according to any one of (12) to (15), wherein the third semiconductor layer further includes an image signal processing circuit.

[0108] (17) The method of any one of (12) to (16), wherein the second semiconductor layer is configured for high dynamic range operation.

[0109] (18) The method according to any one of (12) to (17), wherein the second semiconductor layer further includes at least one conversion gain stage.

[0110] (19) The method of any one of (12) to (18), wherein the second semiconductor layer is an NMOS semiconductor.

[0111] (20) The method according to any one of (12) to (19), wherein the first semiconductor layer further includes a photosensitive device.

[0112] (21) A computer program comprising program code that, when executed on a computer, causes the computer to perform the method according to any one of (11) to (20).

[0113] (22) A non-transitory computer-readable recording medium, wherein a computer program product is stored, which, when executed by a processor, causes the method according to any one of (11) to (20) to be performed.

Claims

1. An imaging circuit, comprising: The first semiconductor layer includes: Photodiode; Global shutter memory node, used for global shutter mode; and A first transmission gate is connected between the photodiode and the global shutter memory node; and The second transmission gate is connected between the global shutter memory node and the pixel amplifier in the second semiconductor layer; The second semiconductor layer includes the pixel amplifier; and The third semiconductor layer includes analog-to-digital conversion circuitry.

2. The imaging circuit according to claim 1, wherein, The first semiconductor layer is configured for correlated double sampling.

3. The imaging circuit according to claim 2, wherein, The correlated double sampling is performed based on the global shutter memory node and the photodiode.

4. The imaging circuit according to claim 1, wherein, The third semiconductor layer also includes image signal processing circuitry.

5. The imaging circuit of claim 1 is further configured to switch between the global shutter mode and the rolling shutter mode based on switching the first transmission gate.

6. The imaging circuit of claim 1 is further configured to activate the global shutter mode by activating the first transmission gate with a predetermined signaling sequence.

7. The imaging circuit according to claim 1, wherein, The second semiconductor layer is configured for high dynamic range operation.

8. The imaging circuit according to claim 1, wherein, The second semiconductor layer also includes at least one conversion gain stage.

9. The imaging circuit according to claim 1, wherein, The second semiconductor layer is an NMOS semiconductor.

10. The imaging circuit according to claim 1, wherein, The first semiconductor layer also includes a photosensitive device.

11. The imaging circuit according to claim 1, wherein, The rolling shutter mode is activated based on one acquisition cycle of the first transmission gate being turned on.

12. A method for operating an imaging circuit, the imaging circuit comprising: The first semiconductor layer includes: Photodiode; Global shutter memory node, used for global shutter mode; and A first transmission gate is connected between the photodiode and the global shutter memory node; and The second transmission gate is connected between the global shutter memory node and the pixel amplifier in the second semiconductor layer; The second semiconductor layer includes a pixel amplifier; and The third semiconductor layer includes analog-to-digital conversion circuitry. The method includes: The global shutter mode or rolling shutter mode is executed based on a predetermined signaling sequence.

13. The method according to claim 12, wherein, The rolling shutter mode is activated based on one acquisition cycle of the first transmission gate being turned on.

14. The method of claim 12, further comprising: Correlated double sampling is performed in the global shutter mode.

15. The method according to claim 14, wherein, Correlated double sampling is performed based on the global shutter memory node and the photodiode.

16. The method according to claim 12, wherein, The third semiconductor layer also includes image signal processing circuitry.

17. The method according to claim 12, wherein, The second semiconductor layer is configured for high dynamic range operation.

18. The method according to claim 12, wherein, The second semiconductor layer also includes at least one conversion gain stage.

19. The method according to claim 12, wherein, The second semiconductor layer is an NMOS semiconductor.

20. The method according to claim 12, wherein, The first semiconductor layer also includes a photosensitive device.

Images