Nonvolatile memory

Abstract

The invention relates to the field of memories, and provides a nonvolatile memory, which comprises a bistable latch consisting of four nonvolatile metal compound transistors; the bistable latch is connected with the first transmission gate transistor through a first storage node and connected with the second transmission gate transistor through a second storage node, and the potential states of the first storage node and the second storage node are opposite and used for marking the two storage states of 0 or 1; the first transmission gate transistor and the second transmission gate transistor are both connected with a control main line and are connected or disconnected under the control of the control main line. The invention relates to a memory and a method thereof, and aims to solve the defects of power failure volatility, data loss risk, huge dynamic / static energy consumption and device heating of an SRAM (Static Random Access Memory) in the related technology, the memory provided by the scheme of the invention adopts a nonvolatile metal compound transistor, so that the memory also has nonvolatile property, and the data security is improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to a non-volatile memory. Background Technology

[0002] Static Random-Access Memory (SRAM) is a semiconductor memory based on bistable flip-flops. It features high-speed access, no refresh required, and low latency, and is mainly used in CPU cache, embedded systems, and network devices.

[0003] However, SRAM in related technologies is volatile when powered off, posing a risk of data loss, as well as significant dynamic / static power consumption and device heat generation issues. Summary of the Invention

[0004] This invention provides a non-volatile memory to address the shortcomings of SRAM in related technologies, such as power-off volatility, risk of data loss, and significant dynamic / static power consumption and device overheating. The memory provided in this application utilizes non-volatile metal compound transistors, making the memory itself non-volatile and improving data security.

[0005] This invention provides a non-volatile memory, comprising: A bistable latch consists of four non-volatile metal compound transistors; The bistable latch is connected to the first transmission gate transistor through the first storage node and to the second transmission gate transistor through the second storage node. The first and second storage nodes have opposite potential states to indicate the two storage states of 0 or 1. Both the first transmission gate transistor and the second transmission gate transistor are connected to the control main line and are connected or disconnected under the control of the control main line. The metal compound transistor includes: Substrate layer; A channel layer is disposed on top of the substrate layer; The source layer is used for current input; Drain layer, used for current output; The source layer and the drain layer are respectively disposed at both ends of the channel layer; A gate dielectric layer is disposed at the center of the top of the channel layer; A gate layer is disposed on one side of the top center position of the gate layer.

[0006] According to the non-volatile memory provided by the present invention, the first transmission gate transistor and the second transmission gate transistor are metal compound transistors.

[0007] According to the non-volatile memory provided by the present invention, the first storage node and the second storage node exchange their level states when the storage state changes.

[0008] According to the non-volatile memory provided by the present invention, the first transmission gate transistor is connected to a bit line, and the second transmission gate transistor is connected to a complementary bit line. The bit lines and the complementary bit lines are connected to the power amplifier.

[0009] According to the non-volatile memory provided by the present invention, the source layer and the drain layer are disposed on the top of the channel layer, and the bottom of the source layer and the drain layer are in contact with the channel layer.

[0010] According to the non-volatile memory provided by the present invention, the source layer and the drain layer are disposed on the side of the channel layer, and the side edges of the source layer and the drain layer are in contact with the side edges of the channel layer.

[0011] The non-volatile memory provided by the present invention further includes a back gate layer; The back gate layer is disposed between the channel layer and the substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

[0012] According to the non-volatile memory provided by the present invention, the channel layer is made of aluminum scandium nitride, or any one or more mixed materials selected from aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen and yttrium. The material of the gate dielectric layer includes, but is not limited to, any one or more of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride; The materials of the source layer and the drain layer include, but are not limited to, any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel, and cobalt. The material of the gate layer includes, but is not limited to, any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum, and aluminum.

[0013] According to the non-volatile memory provided by the present invention, when a write voltage exceeding a threshold voltage is applied to the metal compound transistor, the channel resistance changes, thereby realizing data writing. After the write voltage is removed, the written state remains unchanged, thus exhibiting non-volatility. The metal compound transistor applies a readout voltage below a threshold voltage, and determines whether the channel resistance is low or high based on the magnitude of the output current, thus reading out data 1 or 0.

[0014] In the non-volatile memory provided by the present invention, the threshold voltage is 0.1 to 1 volt.

[0015] The non-volatile memory provided by this invention can use non-volatile metal compound transistors to form bistable latches. Since the transistors used are non-volatile, the memory as a whole is also non-volatile. There is no risk of data loss when power is off, which improves the security of data storage. Furthermore, since no external voltage is required to maintain the data after it is written, it can also reduce energy consumption and heat generation compared to conventional memory. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the non-volatile memory provided in an embodiment of the present invention; Figure 2 This is one of the structural schematic diagrams of the metal compound transistor provided in the embodiments of the present invention; Figure 3 This is a second schematic diagram of the structure of a metal compound transistor provided in an embodiment of the present invention; Figure 4 This is the third schematic diagram of the structure of the metal compound transistor provided in the embodiments of the present invention; Figure 5 This is one of the performance evaluation diagrams provided in the embodiments of the present invention; Figure 6 This is the second performance evaluation diagram provided in the embodiments of the present invention; Figure 7 This is the third performance evaluation diagram provided in the embodiments of the present invention.

[0018] in: 1-Bismulan latch; 2-Substrate layer; 3-Channel layer; 4-Source layer; 5-Drain layer; 6-Gate dielectric layer; 7-Gate layer; 8-Back gate layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] Figure 1 This is a schematic diagram of the structure of the non-volatile memory provided in an embodiment of the present invention.

[0021] like Figure 1 As shown, this embodiment provides a non-volatile memory, including: Bistable latch 1 is composed of four non-volatile metal compound transistors, namely M1, M2, M3 and M4; The bistable latch 1 is connected to the first transmission gate transistor through the first storage node and to the second transmission gate transistor through the second storage node. The first and second storage nodes have opposite potential states to indicate the two storage states of 0 or 1. In practice, the transmission gate transistor used can be a non-volatile metal compound transistor or a traditional metal oxide semiconductor transistor.

[0022] Both the first transmission gate transistor and the second transmission gate transistor are connected to the control main line and are connected or disconnected under the control of the control main line. In practical applications, the first storage node can be The second storage node can be a node, or a node that can be a second storage node. For each node, the first transmission gate transistor can be an M6 transistor, and the second transmission gate transistor can be an M5 transistor. In practical applications, both the M6 ​​and M5 transistors can also be metal-compound transistors. That is to say, in the solution provided in this application... Figure 1 In the memory structure shown, the six transistors M1 to M6 can all be non-volatile metal compound transistors, or only the four transistors M1 to M4 corresponding to the bistable latch can be non-volatile metal compound transistors. Both of these implementations can make the constructed memory non-volatile.

[0023] In practical applications, in the memory provided in this application, VDD only needs to be energized during read and write operations. When maintaining the state, VDD can be de-energized to reduce power consumption. However, during high duty cycle and high frequency operations, VDD can also be kept on to avoid delays caused by frequent switching.

[0024] Meanwhile, when all transistors M1 to M6 in the memory are non-volatile transistors, the control main line WL needs to be powered on to turn on M5 and M6 when reading and writing begin. After M5 and M6 are turned on, the voltage of the control main line WL can be removed to reduce power consumption.

[0025] In practice, the first storage node is the power supply terminal, and the second storage node can be grounded. When the storage state of the memory changes, that is, from 0 to 1 or from 1 to 0, the level states of the first and second storage nodes can be interchanged.

[0026] The metal compound transistor includes: Substrate layer 2; The channel layer 3 is disposed on top of the substrate layer 2; in practical applications, the material of the channel layer 3 can be aluminum scandium nitride, or any one or more mixed materials selected from aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen and yttrium. Source layer 4 is used for current input; Drain layer 5 is used for current output; The source layer 4 and the drain layer 5 are respectively disposed at both ends of the channel layer 3. The materials of the source layer 4 and the drain layer 5 may be any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel and cobalt. The gate dielectric layer 6 is disposed at the center of the top of the channel layer 3. The material of the gate dielectric layer 6 may be any one or more of silicon suboxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride. The gate layer 7 is disposed on one side of the top center position of the gate dielectric layer 6. The material of the gate layer 7 may be any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum and aluminum, including but not limited to polysilicon, titanium nitride, tungsten, tantalum, platinum and aluminum.

[0027] In practical applications, the field-induced phase transition effect of AlScN (aluminum scandium nitride) can be utilized (an electric field is applied to induce a phase transition, thereby changing the resistance state). Referring to the conventional metal compound transistor structure in the prior art, that is, referring to the MOSFET to construct NV (non-volatile)-FET, that is, the metal compound transistor provided by the solution of this application. The core difference between the NV-FET provided by the solution of this application and the MOSFET in the related technology is that its channel material is different from that of traditional semiconductors. It is a non-volatile field-induced phase transition material. In addition, other thin film materials can be superimposed on the upper and lower surfaces of the channel material as needed to improve the interface characteristics.

[0028] in Figure 2 and Figure 3 Two implementations of the metal compound transistor provided for the scheme of this application are as follows: Figure 2As shown, the source layer 4 and the drain layer 5 can be disposed on the top of the channel layer 3, and the bottom of the source layer 4 and the drain layer 5 are in contact with the channel layer 3.

[0029] like Figure 3 As shown, the source layer 4 and the drain layer 5 can also be disposed on the side of the channel layer 3, and the side edges of the source layer 4 and the drain layer 5 are in contact with the side edge of the channel layer 3. It also includes a back gate layer 8, which is disposed between the channel layer 3 and the substrate layer 2, and is used to adjust the electric field distribution of the channel layer 3. An insulating dielectric layer is provided between the back gate layer 8 and the channel layer 3 to separate the back gate layer and the channel layer to prevent leakage.

[0030] Figure 4 This is the third schematic diagram of the structure of a metal compound transistor provided in an embodiment of the present invention. Figure 4 This is a top view of a transistor. As can be seen from the top view angle, Figure 3 and Figure 3 The two corresponding implementations are identical.

[0031] The metal compound transistor provided in this application can also be used in the application of P / N type MOSFETs in the prior art to construct various logic devices and memory devices. In principle, it can completely replace them and bring performance improvements such as non-volatility.

[0032] The metal compound transistor provided in this application can perform normal write and read operations during application. Specifically, during data writing, it can... In a write operation, if a write voltage exceeding the forward threshold voltage is applied, after successful programming, the NV-NFET exhibits a low-resistance state (high current), and the NV-PFET exhibits a high-resistance state (low current). After the voltage is removed, the written state remains unchanged, indicating non-volatility. Similarly, if a write voltage exceeding the reverse threshold voltage is applied, after successful programming, the NV-NFET exhibits a high-resistance state (low current), and the NV-PFET exhibits a low-resistance state (high current). After the voltage is removed, the written state remains unchanged, indicating non-volatility. Here, NV-NFET refers to an N-type NV-FET, and NV-PFET refers to a P-type NV-FET.

[0033] When performing data readout operations, NV-NFET and NV-PFET operate in the same way, and both can apply a readout voltage less than the threshold voltage. Preferably, it can be less than 50% of the threshold voltage. Furthermore, it can identify the high-resistance state (off, logic 0) and the low-resistance state (on, logic 1) based on the current magnitude. In practical applications, the threshold voltage can be 0.1 to 1 volt.

[0034] Figure 5 This is one of the performance evaluation diagrams provided in the embodiments of the present invention.

[0035] Figure 6 This is the second performance evaluation diagram provided in the embodiments of the present invention.

[0036] like Figure 5 and Figure 6 As shown, the performance of the metal compound transistor provided in this application can also be tested. In this embodiment, an ID-VG test was performed on the metal compound transistor. The ID-VG curve can show the variation of the drain-source current (ID) with the gate-source voltage (VGS) under a fixed drain-source voltage (VDS). Figure 5 The ID-VG curve obtained from the ID-VG experiment of NV-NFET. Figure 6 To obtain the ID-VG curve from the ID-VG test of the NV-PFET, from Figure 5 and Figure 6 As can be seen, the NV-FET provided in this embodiment can perform data writing and data reading operations normally.

[0037] Figure 7 This is the third performance evaluation diagram provided in the embodiments of the present invention. Specifically, Figure 7 The butterfly curve for the memory provided in this embodiment, from Figure 7 It can be seen that its storage units have good stability.

[0038] In summary, the metal compound transistor provided by this application is non-volatile, and the memory, due to the application of the non-volatile metal compound transistor, is also non-volatile, thus reducing the risk of data loss. Furthermore, because it is non-volatile, it does not require an external voltage to hold the data, thereby reducing the power consumption of the external voltage and the risk of leakage, thus achieving the beneficial effect of reducing heat generation.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A non-volatile memory, characterized in that, include: A bistable latch consists of four non-volatile metal compound transistors; The bistable latch is connected to the first transmission gate transistor through the first storage node and to the second transmission gate transistor through the second storage node. The first and second storage nodes have opposite potential states to indicate the two storage states of 0 or 1. Both the first transmission gate transistor and the second transmission gate transistor are connected to the control main line and are connected or disconnected under the control of the control main line. The metal compound transistor includes: Substrate layer; A channel layer is disposed on top of the substrate layer; The source layer is used for current input; Drain layer, used for current output; The source layer and the drain layer are respectively disposed at both ends of the channel layer; A gate dielectric layer is disposed at the center of the top of the channel layer; A gate layer is disposed on one side of the top center position of the gate layer.

2. The non-volatile memory according to claim 1, characterized in that, The first transmission gate transistor and the second transmission gate transistor are metal compound transistors.

3. The non-volatile memory according to claim 1, characterized in that, When the storage state of the first storage node and the second storage node changes, their voltage levels are interchanged.

4. The non-volatile memory according to claim 1, characterized in that, The first transmission gate transistor is connected to the bit line, and the second transmission gate transistor is connected to the complementary bit line; The bit lines and the complementary bit lines are connected to the power amplifier.

5. The non-volatile memory according to claim 1, characterized in that, The source layer and the drain layer are disposed on top of the channel layer, and the bottom of the source layer and the drain layer are in contact with the channel layer.

6. The non-volatile memory according to claim 1, characterized in that, The source layer and the drain layer are disposed on the side of the channel layer, and the side edges of the source layer and the drain layer are in contact with the side edges of the channel layer.

7. The non-volatile memory according to claim 1, characterized in that, It also includes the back gate layer; The back gate layer is disposed between the channel layer and the substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

8. The non-volatile memory according to claim 1, characterized in that, The channel layer is made of aluminum scandium nitride, or any one or more of aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen, and yttrium. The material of the gate dielectric layer includes, but is not limited to, any one or more of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride; The materials of the source layer and the drain layer include, but are not limited to, any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel, and cobalt. The material of the gate layer includes, but is not limited to, any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum, and aluminum.

9. The non-volatile memory according to claim 1, characterized in that, When a write voltage exceeding a threshold voltage is applied to the metal compound transistor, the channel resistance changes, thereby enabling data writing. After the write voltage is removed, the written state remains unchanged, exhibiting non-volatility. The metal compound transistor applies a readout voltage below a threshold voltage, and determines whether the channel resistance is low or high based on the magnitude of the output current, thus reading out data 1 or 0.

10. The non-volatile memory according to claim 9, characterized in that, The threshold voltage is 0.1 to 1 volt.

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