Distributed control system and method for an ion cyclotron wave source transmitter

Abstract

The application provides a distributed control system and method of an ion cyclotron wave source transmitter, which comprises a master control unit, a plurality of power supply interface units and a quick interlock protection unit independent of the master control unit. Each power supply interface unit adopts a unified hardware template, integrates a voltage / frequency conversion circuit, a frequency / voltage conversion circuit and an optical fiber transceiver to realize signal isolation transmission in a strong electromagnetic environment; the quick interlock protection unit comprises a hardware comparator network, a complex programmable logic device and a solid-state controller, the protection response time is not more than 20 microseconds, and hierarchical shutdown logic is configured to perform differentiated shutdown combination according to the fault type of a filament, a grid, an anode or a grid power supply. The application solves the problems of poor anti-interference, slow protection response, non-uniform interface and lack of hierarchical shutdown of the existing control system, and is suitable for a high-power radio frequency heating system of a nuclear fusion device.

Description

Technical Field

[0001] This invention relates to the field of nuclear fusion devices and high-power radio frequency heating technology, specifically to a distributed control system and method for an ion cyclotron wave source transmitter. Background Technology

[0002] Ion cyclotron wave heating is one of the most important auxiliary heating methods for magnetic confinement fusion devices (such as tokamak). The transmitter of an ion cyclotron wave heating system typically includes two stages of power amplification: a pre-stage and a final stage. Each stage requires multiple power supplies, such as filament power, grid power, anode power, and screen grid power, to work together, and must perform functions such as precise impedance tuning, rapid fault protection, and high-speed data acquisition.

[0003] In existing technologies, the control system of the transmitter in an ion cyclotron wave heating system mainly uses a programmable logic controller (PLC) as the core control unit. Analog and digital signals are transmitted via copper cables, and a host computer is used to implement timing control, status monitoring, and protection logic. However, the aforementioned existing control systems still have the following technical shortcomings in practical applications: (1) Poor electromagnetic compatibility: The transmitter generates a strong radio frequency electromagnetic field of hundreds of kilowatts during operation. Traditional control systems use copper cables to transmit analog and switching signals. The signal lines are very susceptible to radio frequency interference, resulting in large measurement errors, frequent false triggers, and even protection malfunctions, which seriously affect the reliability and stability of the system.

[0004] (2) Slow protection response speed: Under mismatch or arcing conditions, the heat accumulation time constant of the anode surface of a high-power electron tube (tetraode) is only tens to hundreds of microseconds, and the heat capacity of the grid and screen grid is even smaller. In the existing technology, although the rapid cut-off of high voltage based on hardware circuit has been realized, most solutions still rely on PLC to perform fault detection and main control logic. The scanning cycle of PLC is generally 10ms to 100ms, which is much larger than the thermal damage time window of electron tube, resulting in irreversible damage to electron tube before the protection action (such as gas release, arcing, electrode melting).

[0005] (3) Low standardization of interfaces: The control interface boards for different power supplies such as filament, grid, anode, and screen grid are designed independently, and the hardware circuits are not universal, resulting in high development costs, many types of spare parts, and difficult maintenance. At the same time, the signal transmission between each power supply interface board and the main control unit lacks a unified physical interface and electrical specifications, resulting in poor system integration and scalability.

[0006] (4) Lack of graded shutdown strategy: Existing protection schemes are mostly a one-size-fits-all mode of "full shutdown upon fault", without distinguishing the fault type and the scope of impact (for example, filament faults, grid faults, anode overcurrents, etc. have different degrees of threat to different electrodes of the electron tube). This mode leads to unnecessary power outages, prolonging fault recovery time and reducing the operating efficiency of the fusion device. In addition, existing systems also lack rapid detection and automatic recovery mechanisms for sparking faults. Summary of the Invention

[0007] The present invention aims to provide a distributed control system and method for an ion cyclotron wave source transmitter that can combine strong electromagnetic compatibility, microsecond-level protection response, interface standardization, and hierarchical shutdown capability, so as to solve the problems of poor electromagnetic compatibility, slow protection response speed, low degree of interface standardization, and lack of hierarchical shutdown strategy in the prior art.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A distributed control system for an ion cyclotron wave source transmitter includes: The main control unit is used to realize overall timing control and status monitoring; Multiple power interface units are used for interface conversion of filament power, grid power, anode power and curtain grid power respectively. Each power interface unit adopts a unified hardware template, which integrates voltage / frequency conversion circuit, frequency / voltage conversion circuit and fiber optic transceiver. All power interface units are connected by the same type of connector. The fast interlock protection unit, independent of the main control unit, includes a hardware comparator network, complex programmable logic devices, and a solid-state controller. The fast interlock protection unit is configured with hierarchical shutdown logic, which executes differentiated shutdown combinations based on the type of fault source, including: when the fault source is the filament power supply, simultaneously shutting down the gate power supply, anode power supply, and screen grid power supply, and blocking the excitation; when the fault source is the gate power supply, shutting down the anode power supply and screen grid power supply, and blocking the excitation; when the fault source is the anode power supply, shutting down the screen grid power supply, and blocking the excitation; and when the fault source is the screen grid power supply, shutting down the screen grid power supply, and blocking the excitation.

[0009] Furthermore, the system also includes a tuning control unit, which includes a servo motor and its driver, as well as a short-circuit plate pneumatic control system; the short-circuit plate pneumatic control system is configured to: inflate the short-circuit plate to disconnect it from the resonant cavity before driving the servo motor, and deflate it after the movement is completed to short-circuit the short-circuit plate to the resonant cavity.

[0010] Furthermore, the hardware template integrates two voltage / frequency conversion circuits, two frequency / voltage conversion circuits, four optical signal output channels, and four optical signal input channels; the voltage / frequency conversion circuits are used to convert 0-10V analog setpoints into 0-2MHz frequency signals, and the frequency / voltage conversion circuits are used to convert 0-2MHz frequency signals received by the optical fiber into 0-10V analog quantities.

[0011] Furthermore, the system also includes a measurement and control motherboard, which is a printed circuit board with multiple DB25 connectors for connecting the multiple power interface units. The internal wiring of the measurement and control motherboard enables digital signals to be directly connected to the hardware wiring of the fast interlock protection unit, while analog signals are independently routed to the analog input module and data acquisition unit of the main control unit.

[0012] Furthermore, the graded shutdown logic also includes: when the anode dissipation power is detected to be greater than a preset threshold, the anode power supply and the screen grid power supply are shut down and the excitation is blocked; when the final stage reflection power is detected to be too high, the standing wave ratio is too high, or the solid-state amplifier is abnormal, the excitation is blocked; when the tetrode arcing is detected, the anode power supply is shut down and the excitation is blocked; when the arcing is detected elsewhere in the transmitter resonant cavity, the anode power supply is shut down and the excitation is blocked, and if there is no abnormality within 20 microseconds, it is automatically restored.

[0013] Furthermore, the hardware comparator network includes a high-speed operational amplifier circuit and a hardware comparator. The high-speed operational amplifier circuit is used to amplify and distribute the incident power signal and reflected power signal detected by the directional coupler into four channels, which are respectively used for comparison protection, slow acquisition by the main control unit, fast acquisition by the data acquisition card, and front panel testing. The hardware comparator is used to compare the analog signal with a preset threshold and output a fault flag to the complex programmable logic device.

[0014] The present invention also provides a control method based on the above-described control system, comprising the following steps: S1. Each power interface unit receives the feedback signal and status signal of the corresponding power supply through optical fiber, and inputs them to the main control unit and the fast interlock protection unit after frequency / voltage conversion. The frequency / voltage conversion converts the 0-2MHz frequency signal received by the optical fiber into a 0-10V analog signal. At the same time, the analog set value output by the main control unit is sent to each power supply unit through optical fiber after voltage / frequency conversion. The voltage / frequency conversion converts the 0-10V analog set value into a 0-2MHz frequency signal. S2. Before driving the servo motor, inflate the short circuit board to disconnect it from the resonant cavity. After the movement is completed, deflate the board to short-circuit the resonant cavity. S3. The hardware comparator network compares the detection signal with a preset threshold and outputs a fault flag to the complex programmable logic device. The complex programmable logic device determines the fault type according to the hierarchical shutdown logic and outputs a shutdown command. After receiving the shutdown command, the solid-state controller cuts off the corresponding power output.

[0015] Furthermore, the protection response time of the fast interlocking protection unit does not exceed 20 microseconds, and the protection response time is the total delay from the occurrence of the fault to the solid-state controller cutting off the power output.

[0016] Further, in step S3, the hardware comparator network amplifies the detection signal and distributes it into four channels, wherein the first channel is used to compare with a preset threshold to trigger protection, the second channel is sent to the main control unit for slow acquisition, the third channel is sent to the data acquisition card for fast waveform recording, and the fourth channel is sent to the front panel for testing.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention adopts a fully fiber-optic isolated power interface board architecture. All analog and switching signals are transmitted through ST optical fiber, integrating V / F and F / V conversion circuits, with an isolation voltage of up to 2500Vrms, completely eliminating ground loops and radio frequency electromagnetic interference, and achieving highly reliable error-free transmission in strong electromagnetic environments. At the same time, the four types of power interface boards—filament, grid, anode, and screen grid—use a unified hardware template, combined with the DB25 motherboard bus architecture, significantly reducing development costs and spare parts types, supporting flexible configuration of different power levels in the front and rear stages, and offering strong scalability and maintainability.

[0018] 2. This invention constructs a full hardware protection chain of "hardware comparator-FPGA-solid-state controller", with a protection response time of no more than 20 microseconds, which is 2 to 3 orders of magnitude better than the traditional PLC solution. It can complete the shutdown within the time window of thermal damage of vacuum tubes, effectively protecting expensive high-power tetrodes and avoiding irreversible damage.

[0019] 3. This invention performs differentiated shutdown combinations based on the fault source type (filament, grid, anode, screen grid) and fault mode (overcurrent, arcing, excessive reflection, etc.), avoiding unnecessary shutdowns caused by full shutdown, effectively shortening fault recovery time, reducing frequent impacts on electron tubes, and extending service life; at the same time, an automatic recovery mechanism with no abnormalities within 20 microseconds is designed for arcing faults, improving the operating efficiency of the fusion device.

[0020] 4. This invention adopts a short-circuit board pneumatic coordinated control (inflation → movement → deflation sequence interlocking) to prevent the short-circuit board from rubbing against or sparking with the resonant cavity during movement, ensuring the mechanical safety of impedance tuning operation; at the same time, through the measurement and control motherboard, digital signals are directly connected to the interlocking protection network, and analog signals are independently routed to the main control unit and data acquisition unit, realizing the parallel and coordinated operation of fast protection and slow monitoring. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall architecture of the distributed control system of the ion cyclotron wave source transmitter of the present invention; Figure 2 This is a diagram showing the internal logic structure of the fast interlocking protection unit of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The illustrative embodiments and descriptions of this invention are for illustrative purposes only and are not intended to limit the invention.

[0023] Example 1: System Overall Architecture like Figure 1 As shown, this embodiment provides a distributed control system for an ion cyclotron wave source transmitter, including: a main control unit, a power interface unit group, a fast interlock protection unit, a tuning control unit, a measurement and control motherboard, and a data acquisition unit.

[0024] The main control unit uses a Siemens S7-1500 series programmable logic controller (PLC) and communicates with each functional unit via PROFINET industrial Ethernet. It is responsible for overall timing control, status monitoring, and human-machine interaction functions. The main control unit can also be connected to a host computer via a switch for parameter setting and operation monitoring.

[0025] The power interface unit group comprises four independent power interface boards, used for interface conversion of filament power, grid power, anode power, and screen grid power, respectively. Each power interface board uses a unified hardware template (i.e., the same printed circuit board design), adapting to power units of different power levels only by configuring different resistor and capacitor parameters. Each hardware template integrates two voltage / frequency conversion circuits (V / F), two frequency / voltage conversion circuits (F / V), four ST optical signal output channels, and four ST optical signal input channels. The V / F conversion circuit converts the 0-10V analog setpoint output by the main control unit into a 0-2MHz frequency signal, which is then transmitted to the corresponding power supply unit via optical fiber. The F / V conversion circuit converts the 0-2MHz frequency signal fed back from the power supply unit via optical fiber into a 0-10V analog signal, which is then input to the main control unit and the fast interlock protection unit. The ST optical signal output channel outputs switch commands such as "on", "cooling normal", and "fault reset". The ST optical signal input channel receives status signals such as "fault feedback" and "value reached feedback". All optical transceivers use HFBR-1414 (transmitter) and HFBR-2412 (receiver), providing an isolation voltage of 2500Vrms to ensure error-free signal transmission in strong radio frequency electromagnetic field environments.

[0026] Each power interface board is connected to the measurement and control motherboard via a standard DB25 connector. The measurement and control motherboard is a multi-layer printed circuit board with multiple DB25 sockets. The internal wiring design of the motherboard enables signal splitting: digital signals (such as fault feedback, peak feedback, and start commands) are directly connected to the network of the fast interlocking protection unit via hardware wiring; analog signals (such as voltage and current sample values) are independently routed to the analog input module and data acquisition unit of the main control unit. This design allows the fast protection path and the slow monitoring path to work independently and in parallel, ensuring both the real-time nature of the protection response and the integrity of data acquisition.

[0027] The data acquisition unit uses an NI USB-6453 data acquisition card, providing one single-ended analog input (0-10V), with a maximum sampling rate of 1Ms / s per channel. It achieves synchronous acquisition with the transmitter pulse through an external synchronous trigger signal (synchronous trigger), and is used to record fast waveforms such as ignition and power transients.

[0028] The tuning control unit includes multiple servo motors and their drivers, as well as a short-circuit plate pneumatic control system. The drivers receive commands from the main control unit via PROFINET, driving the servo motors to move the variable capacitor and variable inductor to achieve impedance matching. The short-circuit plate pneumatic control system controls the short-circuit plate within the resonant cavity. Its control logic is as follows: before driving the designated servo motor, the short-circuit plate is inflated to disconnect it from the cavity (remove the short-circuit connection); after movement is complete, the air is released to short-circuit the short-circuit plate back into the cavity. This sequential interlocking control ensures mechanical safety during tuning, preventing the short-circuit plate from rubbing against the cavity or generating arcing during movement.

[0029] Example 2: Fast Interlocking Protection Unit and Hierarchical Shutdown Strategy like Figure 2 As shown, the fast interlocking protection unit is independent of the main control unit and is implemented entirely in hardware, including: a high-speed operational amplifier circuit, a hardware comparator, a complex programmable logic device (Field Programmable Gate Array FPGA), and a solid-state controller.

[0030] The high-speed operational amplifier circuit uses an OPA2690 high-speed operational amplifier to amplify the incident and reflected power signals detected by the directional coupler and distribute them into four channels: the first channel is sent to a hardware comparator for comparison protection; the second channel is sent to the PLC analog input module of the main control unit for slow acquisition; the third channel is sent to the data acquisition unit for fast waveform recording; and the fourth channel is sent to the front panel test port for debugging. Taking the incident power signal as an example, the amplification factor is set to 10 times, amplifying the millivolt-level signal output by the directional coupler to the 0-10V range.

[0031] The hardware comparator uses an LMV7219 high-speed comparator to compare the amplified analog signal with a preset threshold voltage. For example, the threshold voltage corresponding to the reflected power is set to 5V (corresponding to 50% of the rated power). When the reflected power signal exceeds this threshold, the comparator outputs a TTL high-level fault flag. The threshold voltage is set through a precision resistor divider network and can be adjusted according to different protection requirements.

[0032] The FPGA uses an Altera Cyclone IV series (such as EP4CE6) or a Xilinx Spartan-6 series field-programmable gate array, receiving output signals from multiple hardware comparators and TTL level signals from other fault detection modules (such as gate overvoltage, anode overcurrent, arcing detection, etc.). The FPGA internally implements a finite state machine (FSM) to perform multi-condition logic judgments, signal debouncing processing (e.g., setting a 10μs debouncing time window), priority processing, and hierarchical shutdown logic. The FPGA clock frequency is 50MHz, corresponding to a clock period of 20ns. The combinational logic judgment delay within the FPGA is typically in the nanosecond range. With clock synchronization design, fault type identification and shutdown command output can be completed within several clock cycles (tens of nanoseconds to microseconds).

[0033] The specific rules for the tiered shutdown logic are as follows: the FPGA executes differentiated shutdown combinations based on the identified fault source type: Filament power supply failure (such as abnormal filament voltage or filament open circuit): Simultaneously turn off the grid power supply, anode power supply, and screen grid power supply, and block the excitation signal; Gate power supply failure (such as gate overvoltage or overcurrent): Turn off the anode power supply and screen grid power supply, and block the excitation signal; Anode power supply failure (such as anode overvoltage or overcurrent): Turn off the screen grid power supply and block the excitation signal; Screen grid power supply failure (such as screen grid overvoltage or overcurrent): Turn off the screen grid power supply and block the excitation signal; If the anode power dissipation exceeds a preset threshold (which can be configured according to the electron tube model and operating conditions, for example, it can be set to 800kW, or adjusted according to actual needs): the anode power supply and the screen grid power supply are turned off, and the excitation signal is blocked. Excessive final stage reflection power, VSWR > 2.5, solid-state amplifier malfunction: only block the excitation signal; Tetraode arcing: Turn off the anode power supply and block the excitation signal; Sparking occurs elsewhere in the resonant cavity: Turn off the anode power supply and block the excitation signal; if there is no abnormality within 20μs, it will automatically recover.

[0034] The above-mentioned power dissipation The calculation formula is: ; in: The anode input power (unit: kW) is determined by the anode voltage. (Unit: kV) and anode current The product (unit: A) divided by 1000 yields: ; Transmitter output power (unit: kW), incident power detected by the directional coupler. (Unit: kW) Subtract reflected power (Unit: kW) .

[0035] Example 3: Control Method Flow This embodiment provides a distributed control method based on the above system, including the following steps: Step S1: Signal Acquisition and Isolation Transmission Each power interface unit receives feedback and status signals from the corresponding power unit via optical fiber. Taking the anode power supply as an example, the anode power supply attenuates the output voltage (0-750V) to 0-10V through a voltage divider resistor, then converts it into a 0-2MHz frequency signal via a V / F conversion circuit (model: AD654), which is then transmitted via the HFBR-1414 optical fiber transmitter. The HFBR-2412 optical fiber receiver on the power interface board receives this frequency signal, and converts it back to a 0-10V analog signal via an F / V conversion circuit (model: LM331). One input is sent to the PLC analog input module of the main control unit for status display and slow recording, and the other input is sent to the high-speed operational amplifier circuit of the fast interlock protection unit for real-time protection.

[0036] Meanwhile, the analog setpoints output by the main control unit (such as the anode voltage setpoint of 6V, corresponding to 450V) are converted into frequency signals by the V / F conversion circuit and sent to the power supply unit through optical fiber to achieve closed-loop control.

[0037] Step S2: Tuning and Coordination Control When impedance matching is required, the main control unit sends a tuning command to the tuning control unit. The tuning control unit first executes the pneumatic coordinated control of the short-circuit board: it sends an inflation command to the short-circuit board pneumatic control system, the solenoid valve opens, compressed air (0.6MPa pressure) enters the cylinder, pushing the short-circuit board upwards by 2mm to disconnect it from the resonant cavity. After a 50ms delay until the short-circuit board is completely disengaged, the driver drives the servo motor to move the variable capacitor or variable inductor, changing the resonant frequency. After the movement is complete, the tuning control unit sends a deflation command, the solenoid valve reverses, the cylinder vents, and the short-circuit board resets under spring force, short-circuiting back into the cavity. Throughout the process, the main control unit monitors the status of the short-circuit board through a position sensor to ensure reliable execution of the sequential interlocking.

[0038] Step S3: Fast Protection Response During system operation, the fast interlock protection unit continuously monitors various key parameters. Taking abnormal reflected power as an example: The reflected power signal detected by the directional coupler is converted into an analog voltage of 0-10V through a signal conditioning circuit, which has a linear relationship with the reflected power of 0-100kW, i.e., the reflected power... (Unit: kW) and input voltage (Unit: V) Satisfies the following relation: For example: when the reflected power is 20kW, the corresponding voltage is 2V; when the reflected power is 50kW, the corresponding voltage is 5V; when the reflected power reaches the full scale of 100kW, the corresponding voltage is 10V.

[0039] The threshold voltage of the hardware comparator can be flexibly set according to protection requirements. For example, setting the threshold to 5V will trigger protection when the reflected power exceeds 50kW. Specifically, the high-speed operational amplifier circuit amplifies the signal and distributes it into four paths. The first path enters the hardware comparator, whose threshold is set to 5V. When the reflected power signal exceeds 5V, the comparator outputs a TTL high-level fault flag to the FPGA.

[0040] The FPGA's internal finite state machine polls all input fault flags (16 inputs in total). When a high-level reflected power fault flag is detected, the FPGA determines the current fault type as "excessive reflected power in the final stage" based on its hierarchical shutdown logic and executes the corresponding shutdown operation: it only outputs an excitation lockout command to the gate drive circuit, without shutting down the power supply to any of the electrodes. If an anode overcurrent fault is also detected (anode current exceeding the threshold corresponding to 30A), the FPGA executes the shutdown operation corresponding to the anode fault: it outputs a screen grid power-off command and an excitation lockout command.

[0041] After receiving the TTL high-level shutdown command from the FPGA, the solid-state controller switches the RF switch from the on state to the off state within 1μs, cutting off the RF output. The entire protection response time, from the reflected power signal exceeding the threshold to the shutdown of the RF output, was measured to be 10μs, which is much smaller than the thermal damage time window of the vacuum tube, effectively protecting the vacuum tube.

[0042] Furthermore, when the arcing detection module (which can use an ultraviolet phototube or a current surge detection circuit) detects arcing inside the tetrode, it immediately sends a TTL high-level fault flag to the fast interlock protection unit. The FPGA executes the graded shutdown logic: shutting off the anode power supply and blocking the excitation signal. Simultaneously, a 20μs timer is started. If the FPGA does not receive any fault flags within 20μs (i.e., no abnormality), it automatically outputs a reset command: reconnecting the anode power supply, releasing the excitation block, and the system returns to normal operation. If arcing is detected again within 20μs, the shutdown state is maintained, and an "arcing fault" alarm is reported to the main control unit, awaiting manual reset.

[0043] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A distributed control system for an ion cyclotron wave source transmitter, characterized in that, include: The main control unit is used to realize overall timing control and status monitoring; Multiple power interface units are used for interface conversion of filament power, grid power, anode power and curtain grid power respectively. Each power interface unit adopts a unified hardware template, which integrates voltage / frequency conversion circuit, frequency / voltage conversion circuit and fiber optic transceiver. All power interface units are connected by the same type of connector. The fast interlock protection unit, independent of the main control unit, includes a hardware comparator network, complex programmable logic devices, and a solid-state controller; The fast interlocking protection unit is configured with hierarchical shutdown logic, which executes differentiated shutdown combinations based on the type of fault source, including: When the fault source is the filament power supply, the gate power supply, anode power supply and screen grid power supply are turned off and the excitation is blocked. When the fault source is the gate power supply, the anode power supply and the screen grid power supply are turned off and the excitation is blocked. When the fault source is the anode power supply, the screen grid power supply is turned off and the excitation is blocked. When the fault source is the screen grid power supply, turn off the screen grid power supply and block the excitation.

2. The distributed control system of the ion cyclotron wave source transmitter according to claim 1, characterized in that, It also includes a tuning control unit, which includes a servo motor and its driver, and a short-circuit plate pneumatic control system; the short-circuit plate pneumatic control system is configured to: inflate the short-circuit plate to disconnect it from the resonant cavity before driving the servo motor, and deflate it to short-circuit the short-circuit plate to the resonant cavity after the movement is completed.

3. The distributed control system of the ion cyclotron wave source transmitter according to claim 1, characterized in that, The hardware template integrates two voltage / frequency conversion circuits, two frequency / voltage conversion circuits, four optical signal output channels, and four optical signal input channels. The voltage / frequency conversion circuits are used to convert 0-10V analog setpoints into 0-2MHz frequency signals, and the frequency / voltage conversion circuits are used to convert 0-2MHz frequency signals received by the optical fiber into 0-10V analog quantities.

4. The distributed control system of the ion cyclotron wave source transmitter according to claim 1, characterized in that, It also includes a measurement and control motherboard, which is a printed circuit board with multiple DB25 connectors for connecting the multiple power interface units; the internal wiring of the measurement and control motherboard realizes that digital signals are directly connected to the hardware connection of the fast interlock protection unit, and analog signals are independently routed to the analog input module and data acquisition unit of the main control unit.

5. The distributed control system of the ion cyclotron wave source transmitter according to claim 1, characterized in that, The hierarchical shutdown logic also includes: When the detected anode dissipation power exceeds the preset threshold, the anode power supply and the screen grid power supply are turned off and the excitation is blocked. When excessive final stage reflection power, excessive VSWR, or solid-state amplifier abnormality is detected, the excitation is blocked. When tetrode arcing is detected, the anode power supply is turned off and the excitation is blocked. When arcing is detected elsewhere in the transmitter resonant cavity, the anode power supply is shut off and the excitation is blocked. If no abnormality is detected within 20 microseconds, the power supply will automatically recover.

6. The distributed control system of the ion cyclotron wave source transmitter according to claim 1, characterized in that, The hardware comparator network includes a high-speed operational amplifier circuit and a hardware comparator. The high-speed operational amplifier circuit amplifies and distributes the incident power signal and reflected power signal detected by the directional coupler into four channels, which are respectively used for comparison protection, slow acquisition by the main control unit, fast acquisition by the data acquisition card, and front panel testing. The hardware comparator is used to compare the analog signal with a preset threshold and output a fault flag to the complex programmable logic device.

7. A distributed control method for an ion cyclotron wave source transmitter, the method being implemented based on the distributed control system of the ion cyclotron wave source transmitter as described in any one of claims 1 to 6, characterized in that, The control method includes the following steps: S1. Each power interface unit receives the feedback signal and status signal of the corresponding power supply through optical fiber, and inputs them to the main control unit and the fast interlock protection unit after frequency / voltage conversion. The frequency / voltage conversion converts the 0-2MHz frequency signal received by the optical fiber into a 0-10V analog signal. At the same time, the analog set value output by the main control unit is sent to each power supply unit through optical fiber after voltage / frequency conversion. The voltage / frequency conversion converts the 0-10V analog set value into a 0-2MHz frequency signal. S2. Before driving the servo motor, inflate the short circuit board to disconnect it from the resonant cavity. After the movement is completed, deflate the board to short-circuit the resonant cavity. S3. The hardware comparator network compares the detection signal with a preset threshold and outputs a fault flag to the complex programmable logic device. The complex programmable logic device determines the fault type according to the hierarchical shutdown logic and outputs a shutdown command. After receiving the shutdown command, the solid-state controller cuts off the corresponding power output.

8. The distributed control method for the ion cyclotron wave source transmitter according to claim 7, characterized in that, The protection response time of the fast interlock protection unit is no more than 20 microseconds, and the protection response time is the total delay from the occurrence of the fault to the solid-state controller cutting off the power output.

9. The distributed control method for the ion cyclotron wave source transmitter according to claim 7, characterized in that, In step S3, the hardware comparator network amplifies the detection signal and distributes it into four channels. The first channel is used to compare with a preset threshold to trigger protection, the second channel is sent to the main control unit for slow acquisition, the third channel is sent to the data acquisition card for fast waveform recording, and the fourth channel is sent to the front panel for testing.

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