Chip stacking structure, packaging structure, electronic device

Abstract

A chip stacking structure, a packaging structure and an electronic device. The chip stacking structure comprises: in a first direction, a second chip on an even layer is arranged offset to a first chip on an odd layer, a plurality of first signal pads on the first chip on the odd layer are exposed, and the plurality of first signal pads are arranged along a second direction; in the second direction, the second chip on the even layer is arranged offset to the first chip on the odd layer, a plurality of first common pads on the first chip on the odd layer are exposed, the plurality of first signal pads are arranged along the first direction, the first direction is perpendicular to the second direction; a plurality of second common pads on the second chip are arranged along the first direction, and a lead between the first common pads and the second common pads is perpendicular to the first direction. The chip stacking structure has good performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a chip stacking structure, a packaging structure, and an electronic device. Background Technology

[0002] Semiconductor products require high-capacity data processing while their size is gradually decreasing. However, as the number of stacked semiconductor chips increases, the electrical connections between them become more complex. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a chip stacking structure is provided, comprising:

[0004] In a first direction, the second chip located on an even-numbered layer is offset relative to the first chip located on an odd-numbered layer, exposing a plurality of first signal pads on the first chip on the odd-numbered layer, the plurality of first signal pads being arranged along a second direction;

[0005] In the second direction, the second chip located on the even-numbered layer is offset relative to the first chip located on the odd-numbered layer, exposing a plurality of first common pads on the first chip on the odd-numbered layer. The plurality of first signal pads are arranged along the first direction, which is perpendicular to the second direction.

[0006] In this configuration, a plurality of second common pads on the second chip are arranged along the first direction, and the plurality of second common pads are located on the edge of the second chip near the first common pad. Each first common pad corresponds to each second common pad, and the lead between the first common pad and the second common pad is perpendicular to the first direction.

[0007] In some embodiments, the chip stacking structure includes a plurality of first chips and a plurality of second chips, wherein in the vertical direction, the projection areas of the plurality of first chips are offset sequentially, and the projection areas of the plurality of second chips are offset sequentially.

[0008] In some embodiments, in the first direction, the second chip has a first offset relative to the first chip, and in the second direction, the second chip has a second offset relative to the first chip, wherein the first offset is less than the second offset.

[0009] In some embodiments, the first offset is greater than the spacing between the adjacent first signal pads.

[0010] In some embodiments, the spacing between adjacent first signal pads is greater than the spacing between adjacent first common pads.

[0011] In some embodiments, the second chip further includes a plurality of second signal pads arranged along the second direction and located on the edge of the second chip away from the first signal pad.

[0012] In some embodiments, the first chip further includes a first ground pad located between a plurality of first signal pads; the second chip further includes a second ground pad located between a plurality of second signal pads.

[0013] In some embodiments, the second chip further includes a plurality of second signal pads arranged along the second direction and located on the edge of the second chip near the first signal pad.

[0014] In some embodiments, the second signal pad on the second chip is connected to the first signal pad on the first chip via a lead.

[0015] In some embodiments, the first common pad is located on a first edge of the first chip, and the shortest distance from the first edge to the first signal pad is greater than the second offset.

[0016] In some embodiments, the first signal pad is located on the second edge of the first chip, and the shortest distance from the second edge to the first common pad is greater than the first offset.

[0017] In some embodiments, the chip stack structure further includes a packaging substrate having a plurality of substrate common pads, the substrate common pads being connected to the first common pad via leads.

[0018] In some embodiments, the packaging substrate further includes at least one column of first substrate signal pads, the at least one column of first substrate signal pads being arranged in parallel with a plurality of first signal pads, and each of the first signal pads of the first chip being connected to each of the first substrate signal pads via leads.

[0019] According to a second aspect of the present disclosure, a packaging structure is provided, comprising:

[0020] The packaging substrate includes multiple substrate common pads;

[0021] Multiple chips are stacked on the packaging substrate;

[0022] In the first direction, the second chip located on the even-numbered layer is offset relative to the first chip located on the odd-numbered layer, exposing a plurality of first signal pads on the first chip on the odd-numbered layer, and the plurality of first signal pads are arranged along the second direction;

[0023] In the second direction, the second chip located on the even-numbered layer is offset relative to the first chip located on the odd-numbered layer, exposing a plurality of first common pads on the first chip on the odd-numbered layer. The plurality of first signal pads are arranged along the first direction, which is perpendicular to the second direction.

[0024] In this configuration, a plurality of second common pads on the second chip are arranged along the first direction, and the plurality of second common pads are located on the edge of the second chip near the first common pad. Each first common pad corresponds to each second common pad, and the lead between the first common pad and the second common pad is perpendicular to the first direction.

[0025] Each of the substrate common pads corresponds to each of the first common pads, and the lead between the substrate common pads and the first common pads is perpendicular to the first direction.

[0026] According to a third aspect of the present disclosure, an electronic device is provided, comprising: the above-described chip stack structure and a motherboard.

[0027] In summary, this disclosure provides a chip stacking structure, a packaging structure, and an electronic device. The chip stacking structure employs an offset stacking method, such that the second chip is offset relative to the first chip in both the first and second directions. However, a one-to-one correspondence is formed between multiple first common pads on the first chip and multiple second common pads on the second chip, and the leads between the first and second common pads are perpendicular to the first direction. This simplifies the electrical connection between the two chips. Simultaneously, it reduces the signal path between the two chips, thereby lowering signal loss. Attached Figure Description

[0028] Figure 1 This is a schematic diagram illustrating a chip stacking structure according to an exemplary embodiment;

[0029] Figure 2 This is illustrated according to an exemplary embodiment. Figure 1 Cross-sectional view in the X direction;

[0030] Figure 3 This is illustrated according to an exemplary embodiment. Figure 1 Cross-sectional view in the Y direction;

[0031] Figure 4This is illustrated according to an exemplary embodiment. Figure 1 Top view in X / Y;

[0032] Figure 5 This is a schematic diagram showing the offset of a first chip and a second chip according to an exemplary embodiment;

[0033] Figure 6 This is a schematic diagram of a first ground pad / second ground pad according to an exemplary embodiment;

[0034] Figure 7 This is a schematic diagram showing the offset of a first chip and a second chip according to an exemplary embodiment;

[0035] Figure 8 This is a cross-sectional view of a chip stacking structure in the X direction according to an exemplary embodiment;

[0036] Figure 9 This is a cross-sectional view of a chip stacking structure in the Y direction according to an exemplary embodiment;

[0037] Figure 10 This is a top view of a packaging substrate according to an exemplary embodiment;

[0038] Figure 11 This is a top view of a chip stacking structure illustrated according to an exemplary embodiment;

[0039] Figure 12 This is a schematic diagram showing another offset of the first chip and the second chip according to an exemplary embodiment;

[0040] Figure 13 This is another cross-sectional view in the X direction of a chip stacking structure illustrated according to an exemplary embodiment;

[0041] Figure 14 This is another top view of a packaging substrate according to an exemplary embodiment;

[0042] Figure 15 This is a schematic diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0043] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0044] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0045] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0046] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0047] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0048] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0049] In related technologies, semiconductor chips can be stacked to increase the storage capacity of semiconductor products. However, as the number of semiconductor chips increases, the electrical connections between these semiconductor chips become relatively complex, which also leads to signal loss in the semiconductor chips.

[0050] In view of the above-mentioned technical problems, this disclosure proposes a chip stacking structure that can improve the complexity of electrical connections and reduce signal loss.

[0051] like Figure 1 As shown, this disclosure provides a chip stacking structure 100, which may include a plurality of semiconductor chips stacked in a vertical direction (Z direction). For example, Figure 1The chip stack structure 100 includes four semiconductor chips stacked vertically. Of course, the chip stack structure 100 may include at least two semiconductor chips, i.e., multiple semiconductor chips. The multiple semiconductor chips may be memory semiconductor chips. Each of the memory semiconductor chips may be, for example, a volatile memory semiconductor chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). According to some exemplary embodiments, the multiple semiconductor chips may be flash memory, such as NAND flash memory. According to other exemplary embodiments, the multiple semiconductor chips included in the chip stack structure 100 may include different types of semiconductor chips. For example, some of the multiple semiconductor chips may be logic chips, and others may be memory chips. For example, each of the logic chips may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. The multiple semiconductor chips may have the same size. For example, multiple semiconductor chips can have the same horizontal width, the same vertical width, and the same thickness.

[0052] like Figures 1-2 As shown, the chip stack structure 100 includes, for example, two first chips 101 located on an odd-numbered layer and two second chips 102 located on an even-numbered layer. In this embodiment, the odd-even-odd-even layers can be defined vertically from bottom to top, such that the first chips 101 and the second chips 102 alternate with each other. In a first direction (X direction), the second chips 102 on the even-numbered layers are located on top of the first chips 101 on the odd-numbered layers. The second chips 102 are offset to the right relative to the first chips 101, such that the second chips 102 extend beyond the side surface of the first chips 101, i.e., a portion of the second chips 102 protrudes from the first chips 101 in the first direction. In the first direction, the side surfaces of the two first chips 101 are aligned, i.e., in the first direction, neither chip of the two first chips 101 extends beyond the other. In the first direction, the side surfaces of the two second chips 102 are aligned, i.e., in the first direction, neither chip of the two second chips 102 extends beyond the other.

[0053] like Figures 1-3As shown, in the second direction (Y direction), the two second chips 102 and the two first chips 101 are offset from each other sequentially, such that each semiconductor chip extends beyond the side surface of the underlying semiconductor chip. That is, the second chip 102 can be stacked on the first chip 101 disposed below it, such that a portion of the second chip 102 protrudes from the first chip 101 in the second direction (Y direction). The first chip 101 can be stacked on the second chip 102 disposed below it, such that a portion of the first chip 101 protrudes from the second chip 102 in the second direction (Y direction). For example, the first chip 101 and the second chip 102 can be stacked on top of each other in a stepped manner, that is, in the Y direction, the offset of the second chip 102 relative to the first chip 101 is equal to the offset of the first chip 101 relative to the second chip 102.

[0054] like Figure 1 and Figure 4 As shown in the embodiments of this disclosure, Figure (a) is a top view of a plurality of first chips 101. The dashed lines represent the projection area of ​​the lower first chip 101, and the solid lines represent the projection area of ​​the upper first chip 101. As can be seen from Figure (a), these two projection areas are aligned in the X direction and sequentially offset in the Y direction; that is, a portion of the upper first chip 101 protrudes beyond the side surface of the lower first chip 101. Figure (b) is a top view of a plurality of second chips 102. The dashed lines represent the projection area of ​​the lower second chip 102, and the solid lines represent the projection area of ​​the upper second chip 102. As can be seen from Figure (b), these two projection areas are aligned in the X direction and sequentially offset in the Y direction; that is, a portion of the upper second chip 102 protrudes beyond the side surface of the lower second chip 102.

[0055] In some embodiments, the X and Y directions can be interchanged. In this case, the projection area of ​​the first chip 101 can be offset in the X direction, and the projection area of ​​the second chip 102 can also be offset in the X direction.

[0056] like Figure 5 As shown, Figure 5The diagram shows a top view of a second chip 102 and a top view of a first chip 101. In a first direction (X-direction), the second chip 102 is offset relative to the first chip 101, thereby exposing a plurality of first signal pads 103 on the first chip 101. These first signal pads 103 can be arranged along a second direction (Y-direction). These first signal pads 103 can be arranged along the edge of the first chip 101. In the disclosed embodiment, the first signal pads 103 are used, for example, to transmit I / O signals, DQS signals, CE signals, RE signals, WE signals, CLE signals, ALE signals, R / B signals, etc. In the second direction (Y-direction), the second chip 102 is offset relative to the first chip 101, thereby exposing a plurality of first common pads 104 on the first chip 101. These first common pads 104 can be arranged along the first direction. These first common pads 104 can be arranged along the edge of the first chip 101. Since the first direction is perpendicular to the second direction, the first signal pad 103 and the first common pad 104 can be disposed on adjacent edges of the first chip 101. In this embodiment, the first common pad 104 can provide ground voltage, power supply voltage, and address signals.

[0057] like Figure 5 As shown, in some embodiments, the second chip 102 also has a plurality of second common pads 105, which are located on the edge of the second chip 102 and can be arranged along a first direction. The second chip 102 also has a plurality of second signal pads 106, which can be located on the edge of the second chip 102, for example, on the edge of the second chip 102 away from the first signal pad 103. The second signal pads 106 can be arranged along a second direction to facilitate wire bonding on the second signal pads 106 of the second chip 102. The second common pads 105 can provide ground voltage, power supply voltage, and address signals. The second signal pads 106 are used, for example, to transmit I / O signals, DQS signals, CE signals, RE signals, WE signals, CLE signals, ALE signals, R / B signals, etc.

[0058] like Figure 5As shown, the second common pad 105 is located on the edge of the second chip 102 near the first chip 101, meaning that both the first common pad 104 and the second common pad 105 are arranged along the first direction. The number of first common pads 104 can be equal to the number of second common pads 105, and both the first common pads 104 and the second common pads 105 can transmit the same common signal for the first chip 101 and the second chip 102. This allows for a one-to-one correspondence between the first common pads 104 and the second common pads 105, and they are then connected via leads 107. Because multiple first common pads 104 and multiple second common pads 105 form a one-to-one correspondence, the leads 107 between the first common pads 104 and the second common pads 105 can be perpendicular to the first direction. Since the leads 107 are perpendicular to the first direction, the electrical connection between the first chip 101 and the second chip 102 becomes relatively simple, and the length of the leads 107 can be reduced, improving signal loss. If the first common pad 104 and the second common pad 105 are not in a one-to-one correspondence, that is, if the second common pad 105 is offset relative to the first common pad 104, then the connection line 107 between the first common pad 104 and the second common pad 105 cannot be perpendicular to the first direction. This makes the electrical connection between the first chip 101 and the second chip 102 relatively complex, and the length of the lead 107 will increase, resulting in greater signal loss. It should be noted that the perpendicularity here can be either planar or spatial. Therefore, in this embodiment, the lead 107 can be perpendicular to the first direction in either a planar or spatial manner.

[0059] like Figure 5 As shown, in a first direction, the second chip 102 has a first offset d1 relative to the first chip 101, which fully exposes the first signal pads 103 on the first chip 101. The first offset d1 can be the distance between the right edge of the first chip 101 and the right edge of the second chip 102 in the first direction. The first offset d1 can also be the distance between the left edge of the first chip 101 and the left edge of the second chip 101 in the first direction. In a second direction, the second chip 102 has a second offset d2 relative to the first chip 101, which fully exposes the first common pads 104 on the first chip 101. The second offset d2 can be the distance between the upper edge of the first chip 101 and the upper edge of the second chip 102 in the second direction. The second offset d2 can also be the distance between the lower edge of the first chip 101 and the lower edge of the second chip 102 in the second direction.

[0060] like Figure 5As shown, in some embodiments, the first offset d1 can be less than the second offset d2. Since the second chip 102 is offset in the first direction, exposing the first signal pad 103 on the first chip 101, and offset in the second direction, exposing the first common pad 104 on the first chip 101. The first signal pad 103 on the first chip 101 and the second signal pad 106 on the second chip 102 need to be wire-connected to the substrate, and the first common pad 104 on the first chip 101 and the second common pad 105 on the second chip 102 need to be wire-connected. Therefore, to reduce the difficulty of wire bonding for the first common pad 104 and the second common pad 105, the second offset d2 can be greater than the first offset d1. If the second offset d2 is less than the first offset d1, the spacing between the first common pad 104 and the second common pad 105 decreases in the second direction, which is detrimental to the wire bonding process.

[0061] In some embodiments, if the range of the first offset d1 and the second offset d2 both exceed 200um, for example, 220-260um, the first offset d1 can be equal to the second offset d2. This makes the design of the chip stacking structure 100 relatively simple and also reduces the complexity of the electrical connections between chips.

[0062] like Figure 5 As shown, multiple first signal pads 103 are spaced apart on the edge of the first chip 101, for example, a column of first signal pads 103 is provided on the edge of the first chip 101. Multiple first common pads 104 are spaced apart on the edge of the first chip 101, for example, a row of first common pads 104 is provided on the edge of the first chip 101. The column of first signal pads 103 and the row of first common pads 104 are located on adjacent edges of the first chip 101. There is a spacing d3 between two adjacent first signal pads 103 and a spacing d4 between two adjacent first common pads 104. In some embodiments, the first offset d1 can be greater than the spacing d3, and the spacing d3 can be greater than the spacing d4. Since the first offset d1 is small, the spacing d3 of the first signal pads 103 can be small, allowing more first signal pads 103 to be provided on the edge of the first chip 101. At the same time, it can also ensure that signal crosstalk is avoided when the first signal pads 103 transmit signals. The spacing d4 between the first common pads 104 is smaller. Since the first common pads 104 are used to transmit signals such as power supply voltage or ground voltage, there will be no signal crosstalk or other problems.

[0063] like Figure 6As shown, in some embodiments, to improve signal crosstalk between data signals, a plurality of first ground pads 108 can be provided on the first chip 101, and the first ground pads 108 can be spaced apart between adjacent first signal pads 103. Similarly, a plurality of second ground pads 109 can be provided on the second chip 102, and the second ground pads 109 can be spaced apart between adjacent second signal pads 106.

[0064] like Figure 7 As shown, the first common pad 104 can be disposed on the first edge 1011 of the first chip 101. The first signal pad 103 can be disposed on the second edge 1012 of the first chip 101. In the first direction, the second chip 102 has a first offset d1 relative to the first chip 101. At this time, the shortest distance d5 from the second edge 1012 to the first common pad 104 can be greater than the first offset d1. At the same time, in the second direction, the second chip 102 has a second offset d2 relative to the first chip 101. At this time, the shortest distance d6 from the first edge 1011 to the first signal pad 103 can be greater than the second offset d2. It should be noted that the shortest distance d5 from the second edge 1012 to the first common pad 104 can be understood as the distance from the first common pad 104 closest to the second edge 1012 to the second edge 1012. The shortest distance d6 from the first edge 1011 to the first signal pad 103 can be understood as the distance from the first signal pad 104 closest to the first edge 1011 to the first edge 1011. In this embodiment, in the first direction, the shortest distance d5 is greater than the first offset d1, thereby ensuring a one-to-one correspondence between the common pads on the first chip 101 and the second chip 102, and thus ensuring that the connection is perpendicular to the first direction. At the same time, in the second direction, the shortest distance d6 is greater than the second offset d2, which ensures that these first signal pads 103 are relatively concentrated in certain areas of the second edge 1012, thereby facilitating the routing paths of the first signal pads 103 and other pads.

[0065] like Figures 8-10As shown, in some embodiments, the chip stack structure 100 may further include a packaging substrate 110. A first chip 101 is mounted on the packaging substrate 110 via a first adhesive layer 111, and a second chip 102 is mounted on the first chip 101 via the first adhesive layer 111. A first signal pad 103 on the first chip 101 is connected to a first substrate signal pad 114 on the packaging substrate 110 via a first lead 112, and a second signal pad 106 on the second chip 102 is connected to a second substrate signal pad 115 on the packaging substrate 110 via a first lead 112. The packaging substrate 110 may have at least one column of first substrate signal pads 114 and at least one column of second substrate signal pads 115. Since the first signal pads 103 on multiple first chips 101 are respectively connected to the packaging substrate 110, multiple columns of first substrate signal pads 114 may be provided on the packaging substrate 110. That is, the number of columns of first substrate signal pads 114 may be equal to the number of first chips 101. Since the second signal pads 106 on the multiple first chips 102 are respectively connected to the packaging substrate 110, multiple rows of second substrate signal pads 115 can be provided on the packaging substrate 110. That is, the number of rows of second substrate signal pads 115 can be equal to the number of second chips 102. In this embodiment, the first adhesive layer 111 can be DAF (dieattach film). Since the thickness of the first adhesive layer 111 is small, it cannot cover the first lead 112. Therefore, this embodiment adopts an offset stacking method to ensure that the signal pads on the first chips 101 and the second chips 102 can be electrically connected to the packaging substrate 110. Since the DAF is thin, the overall thickness of the chip stack structure can be reduced, and the thermal conductivity of the material is less than that of the first chip 101, thus improving the heat dissipation effect of the chip stack structure.

[0066] like Figures 8-10 As shown, the first common pad 104 on the first chip 101 and the second common pad 105 on the second chip 102 are connected by a lead 107. Then, the first common pad 104 on the first chip 101 is connected to the substrate common pad 113 on the package substrate 110 via the lead 107. Since the substrate common pad 113 can provide power supply voltage and / or ground voltage, these chips can be connected together via the lead 107, and thus connected to the package substrate 110. Figure 9 As can be seen, lead 107 can be spatially perpendicular to the first direction, thereby reducing the difficulty of electrical connection between these chips and reducing signal loss.

[0067] like Figure 11 As shown, Figure 11 The image shown is a top view of the chip stack structure 100. Figure 11Only a top view of leader 107 is shown. Figure 11 In this embodiment, a lead 107 connects the first chip 101, the second chip 102, and the packaging substrate 110. The lead 107 is perpendicular to the first direction in the plane. During the stacking process of the first chip 101 and the second chip 102, the first common pad 104 and the second common pad 105 are made to correspond one-to-one, and the lead 107 between the first common pad 104 and the second common pad 105 is made perpendicular to the first direction, that is, the lead 107 is prevented from being tilted to the first direction. This improves the complexity of the electrical connection between the first chip 101 and the second chip 102, and also improves signal loss. If the first common pad 104 on the first chip 101 does not correspond one-to-one with the second common pad 105 on the second chip 102, then the lead 107 between the first common pad 104 and the second common pad 105 is tilted to the first direction, which will increase the difficulty and length of wire bonding, and thus be detrimental to the electrical connection between the first chip 101 and the second chip 102.

[0068] like Figure 12 As shown, this embodiment also proposes another chip stacking structure 100, which may include a first chip 101 and a second chip 102, with the second chip 102 offset from the first chip 101. In a first direction, the second chip 102 is offset relative to the first chip 101, exposing a first signal pad 103 on the first chip 101. In a second direction, the second chip 102 is offset relative to the first chip 101, exposing a first common pad 104 on the first chip 101. The second chip 102 also has a second common pad 105 and a second signal pad 106. The second common pad 105 is arranged parallel to the first common pad 104. The second common pad 105 is located on the edge of the second chip 102 near the first chip 101. The second common pad 105 and the first common pad 104 can form a one-to-one correspondence, so that the lead 107 between the first common pad 104 and the second common pad 105 can be perpendicular to the first direction, improving the complexity of the electrical connection between the first chip 101 and the second chip 102. The second signal pad 106 is located on the edge of the second chip 102 near the first signal pad 103, so that the first signal pad 103 and the second signal pad 106 are arranged parallel, thus forming a one-to-one correspondence between the first signal pad 103 and the second signal pad 106. Furthermore, the first lead 112 between the first signal pad 103 and the second signal pad 106 can be perpendicular to the second direction, thereby improving the complexity of the electrical connection between the first chip 101 and the second chip 102.

[0069] like Figures 12-13As shown, in some embodiments, the chip stack structure 100 may further include a packaging substrate 110. A first chip 101 can be mounted on the packaging substrate 110 via a first adhesive layer 111, and a first second chip 102 can be mounted on the first chip 101 via the first adhesive layer 111. A second first chip 101 can be mounted on the first second chip 102 via a second adhesive layer 116, and a second second chip 102 can be mounted on the second first chip 101 via the first adhesive layer 111. The thickness of the first adhesive layer 111 may be less than the thickness of the second adhesive layer 116, so that the second adhesive layer 116 can cover the first lead 112. The second signal pad 106 on the second chip 102 is connected to the first signal pad 103 on the first chip 101 via the first lead 112, and then connected to the signal pad on the packaging substrate 110 via the first lead 112. Since the signal pads of the first chip 101 and the second chip 102 are connected via the first lead 112, the signal path between the first chip 101 and the second chip 102 can be reduced, thereby improving the signal time difference between the first chip 101 and the second chip 102. In this embodiment, the second adhesive layer 116 can be FOW (Film over Wire).

[0070] like Figure 14 As shown, Figure 14 Displayed as Figure 13 Top view of the intermediate packaging substrate 110. Figure 14 and Figure 10 The difference is that, Figure 14 The first substrate signal pad 114 and the second substrate signal pad 115 are located on the same side of the packaging substrate 110, and are connected to the first chip 101 via first leads 112. Because the first substrate signal pad 114 and the second substrate signal pad 115 are located on the same side of the packaging substrate 110, the volume of the packaging substrate 110 can be reduced, thereby reducing the volume of the chip stack structure 100. The substrate common pad 113 on the packaging substrate 110 can be connected to the first chip 101 and the second chip 102 via leads; the connection relationship can be found in [reference needed]. Figure 11 Center lead 107. In some embodiments, the packaging substrate 110 can be any of various types of substrates, such as a printed circuit board (PCB), an organic substrate, an inorganic substrate, a glass substrate, or a flexible substrate. Furthermore, the packaging substrate 110 can be a substrate for various types of electronic devices, such as mobile devices, memory devices, display devices, or display driver integrated circuits (DDI). The packaging substrate 110 can be a multilayer (printed) circuit board having vias and various circuit patterns connected to the vias.

[0071] like Figure 7 and Figure 11 As shown in the embodiments of this disclosure, a packaging structure is also proposed. This packaging structure may include a packaging substrate 110, on which substrate common pads 113 are arranged along a first direction and located on the edge of the packaging substrate 110. A first chip 101 and a second chip 102 are stacked sequentially on the packaging substrate 110. In the first direction (X direction), the second chip 102 is offset relative to the first chip 101, exposing a first signal pad 103 on the first chip 101, i.e., the first signal pad 103 is arranged along a second direction. In the second direction (Y direction), the second chip 102 is offset relative to the first chip 101, exposing a first common pad 104 on the first chip 101, i.e., the first common pad 104 is arranged along the first direction. The second chip 102 also has a second common pad 105, which is arranged along the first direction. The second common pad 105 is located on the edge of the second chip 102 near the first common pad 104, so that the first common pad 104 and the second common pad 105 form a one-to-one correspondence. At the same time, the substrate common pad 113 can also form a one-to-one correspondence with the first common pad 104. Therefore, when the lead 107 connects the packaging substrate 110, the first chip 101 and the second chip 102, the lead 107 can be perpendicular to the first direction, thereby improving the complexity of the electrical connection between the first chip 101, the second chip 102 and the packaging substrate 110. Figure 14 A cross-sectional view in the X or Y direction can be referenced. Figure 8 and Figure 9 .

[0072] like Figure 15As shown in the embodiments of this disclosure, another electronic device 10 is also disclosed. This electronic device 10 may include a motherboard 200 and a chip stack structure 100, the chip stack structure 100 being fixed to the motherboard 200 by solder balls. The structure of the chip stack structure 100 can be referred to the above description. This electronic device 10 may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs). This electronic device 10 can also be applied in large servers, such as data centers, AI computers, and other fields. The electronic device 10 can also be used in personal navigation devices or portable navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), wearable computers, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, and / or drones.

[0073] In summary, this disclosure provides a chip stacking structure, a packaging structure, and an electronic device. The chip stacking structure employs an offset stacking method, such that the second chip is offset relative to the first chip in both the first and second directions. However, a one-to-one correspondence is formed between multiple first common pads on the first chip and multiple second common pads on the second chip, and the leads between the first and second common pads are perpendicular to the first direction. This simplifies the electrical connection between the two chips. Simultaneously, it reduces the signal path between the two chips, thereby lowering signal loss.

[0074] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip stacking structure, characterized in that, include: In a first direction, the second chip located on an even-numbered layer is offset relative to the first chip located on an odd-numbered layer, exposing a plurality of first signal pads on the first chip on the odd-numbered layer, the plurality of first signal pads being arranged along a second direction; In the second direction, the second chip located on the even-numbered layer is offset relative to the first chip located on the odd-numbered layer, exposing a plurality of first common pads on the first chip on the odd-numbered layer. The plurality of first signal pads are arranged along the first direction, which is perpendicular to the second direction. In this configuration, a plurality of second common pads on the second chip are arranged along the first direction, and the plurality of second common pads are located on the edge of the second chip near the first common pad. Each first common pad corresponds to each second common pad, and the lead between the first common pad and the second common pad is perpendicular to the first direction.

2. The chip stacking structure according to claim 1, characterized in that, The chip stacking structure includes multiple first chips and multiple second chips. In the vertical direction, the projection areas of the multiple first chips are offset sequentially, and the projection areas of the multiple second chips are offset sequentially.

3. The chip stacking structure according to claim 1, characterized in that, In the first direction, the second chip has a first offset relative to the first chip, and in the second direction, the second chip has a second offset relative to the first chip, wherein the first offset is less than the second offset.

4. The chip stacking structure according to claim 3, characterized in that, The first offset is greater than the spacing between the adjacent first signal pads.

5. The chip stacking structure according to any one of claims 1-4, characterized in that, The spacing between adjacent first signal pads is greater than the spacing between adjacent first common pads.

6. The chip stacking structure according to any one of claims 1-4, characterized in that, The second chip also includes a plurality of second signal pads, which are arranged along the second direction and located on the edge of the second chip away from the first signal pad.

7. The chip stacking structure according to claim 6, characterized in that, The first chip further includes a first ground pad located between a plurality of first signal pads; the second chip further includes a second ground pad located between a plurality of second signal pads.

8. The chip stacking structure according to any one of claims 1-4, characterized in that, The second chip also includes a plurality of second signal pads, which are arranged along the second direction and located on the edge of the second chip near the first signal pad.

9. The chip stacking structure according to claim 8, characterized in that, The second signal pad on the second chip is connected to the first signal pad on the first chip via a lead.

10. The chip stacking structure according to claim 3 or 4, characterized in that, The first common pad is located on the first edge of the first chip, and the shortest distance from the first edge to the first signal pad is greater than the second offset.

11. The chip stacking structure according to claim 3 or 4, characterized in that, The first signal pad is located on the second edge of the first chip, and the shortest distance from the second edge to the first common pad is greater than the first offset.

12. The chip stacking structure according to claim 6 or 8, characterized in that, The chip stacking structure also includes a packaging substrate, which has multiple substrate common pads, and the substrate common pads are connected to the first common pads via leads.

13. The chip stacking structure according to claim 12, characterized in that, The packaging substrate also has at least one column of first substrate signal pads, and the at least one column of first substrate signal pads is arranged in parallel with a plurality of first signal pads. Each of the first signal pads of the first chip is connected to each of the first substrate signal pads by a lead.

14. A packaging structure, characterized in that, include: The packaging substrate includes multiple substrate common pads; Multiple chips are stacked on the packaging substrate; In the first direction, the second chip located on the even-numbered layer is offset relative to the first chip located on the odd-numbered layer, exposing a plurality of first signal pads on the first chip on the odd-numbered layer, and the plurality of first signal pads are arranged along the second direction; In the second direction, the second chip located on the even-numbered layer is offset relative to the first chip located on the odd-numbered layer, exposing a plurality of first common pads on the first chip on the odd-numbered layer. The plurality of first signal pads are arranged along the first direction, which is perpendicular to the second direction. In this configuration, a plurality of second common pads on the second chip are arranged along the first direction, and the plurality of second common pads are located on the edge of the second chip near the first common pad. Each first common pad corresponds to each second common pad, and the lead between the first common pad and the second common pad is perpendicular to the first direction. Each of the substrate common pads corresponds to each of the first common pads, and the lead between the substrate common pads and the first common pads is perpendicular to the first direction.

15. An electronic device, characterized in that, Includes the chip stacking structure and motherboard as described in any one of claims 1-13.

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