A display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes a first driving transistor and a second driving transistor. The first driving transistor is coupled between a first power line and a first electrode of the light-emitting element, and the second driving transistor is coupled between the first power line and the first electrode of the light-emitting element. The subthreshold swing of the first driving transistor is greater than that of the second driving transistor. In a first brightness mode, the first driving transistor connects the first power line and the first electrode of the light-emitting element. In a second brightness mode, the second driving transistor connects the first power line and the first electrode of the light-emitting element. The brightness of the light-emitting element in the first brightness mode is greater than that in the second brightness mode. This application can accommodate the different display requirements of the display panel under high and low brightness conditions, thereby improving the display uniformity of the display panel under high and low brightness conditions.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel and a display device. Background Technology

[0002] Currently, the pixel driving circuits used in display panels typically employ low-temperature polycrystalline silicon (LTPS) transistors. When displaying at low brightness and low grayscale, the driving transistors operate in the subthreshold region. Due to the poor uniformity of the subthreshold swing of LTPS transistors, driving transistors with larger subthreshold swings have higher currents, while those with smaller subthreshold swings have lower currents. This results in uneven display performance when displaying at low brightness and low grayscale, severely impacting the display effect.

[0003] Therefore, how to balance the different needs of display panels under high and low brightness conditions and ensure that display panels have high display uniformity under different brightness levels has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a display panel and display device that can take into account the different display requirements of the display panel under high brightness and low brightness conditions, thereby improving the display uniformity of the display panel under high brightness and low brightness conditions.

[0005] In a first aspect, embodiments of this application provide a display panel, including a pixel driving circuit and a light-emitting element; the pixel driving circuit includes a first driving transistor and a second driving transistor; the first driving transistor is coupled between a first power line and a first electrode of the light-emitting element, and the second driving transistor is coupled between the first power line and the first electrode of the light-emitting element; the subthreshold swing of the first driving transistor is greater than the subthreshold swing of the second driving transistor; wherein, in a first brightness mode, the first driving transistor connects the first power line and the first electrode of the light-emitting element; in a second brightness mode, the second driving transistor connects the first power line and the first electrode of the light-emitting element; the brightness of the light-emitting element in the first brightness mode is greater than the brightness of the light-emitting element in the second brightness mode.

[0006] Secondly, embodiments of this application provide a display device, including a display panel as described in the first aspect embodiment.

[0007] Compared with the prior art, the display panel and display device provided in this application achieve at least the following beneficial effects: This application provides a display panel and a display device. The display panel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes a first driving transistor and a second driving transistor. The first driving transistor is coupled between a first power line and a first electrode of the light-emitting element, and the second driving transistor is coupled between the first power line and the first electrode of the light-emitting element. The subthreshold swing of the first driving transistor is greater than that of the second driving transistor. In a first brightness mode, the first driving transistor connects the first power line and the first electrode of the light-emitting element. In a second brightness mode, the second driving transistor connects the first power line and the first electrode of the light-emitting element. The brightness of the light-emitting element in the first brightness mode is greater than that in the second brightness mode. In the case of high grayscale and high brightness in the first brightness mode, this application uses the first driving transistor to connect the first power line and the first electrode of the light-emitting element. Because the subthreshold swing of the first driving transistor is large, the electron mobility of the first driving transistor is higher, which can ensure the high current driving capability of the first driving transistor, thereby meeting the requirement of the pixel driving circuit to provide a large driving current. Furthermore, the high electron mobility of the first driving transistor enables faster and more thorough threshold voltage compensation during the threshold compensation stage, effectively compensating for the threshold voltage offset of the first driving transistor and improving the display uniformity of the display panel. In the low grayscale and low brightness mode of the second brightness mode, this application uses a second driving transistor to connect the first power line to the first electrode of the light-emitting element. The second driving transistor operates in the subthreshold region, where the driving current flowing through it is relatively small. Because the subthreshold swing of the second driving transistor is small, its gate voltage can more sensitively regulate the drain current. This allows the display panel to achieve fine grayscale gradation within a smaller driving current range, thus avoiding severe brightness fluctuations in low brightness and low grayscale display conditions, thereby improving the display uniformity of the display panel. Therefore, this application can accommodate the different display requirements of the display panel in both high and low brightness conditions, thereby improving the display uniformity of the display panel in both high and low brightness conditions. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application; Figure 2 This is a structural example diagram of another pixel driving circuit provided in an embodiment of this application; Figure 3This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application; Figure 5 A timing diagram of a pixel driving circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an inverting module provided in an embodiment of this application; Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0010] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0011] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0012] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0013] In the embodiments of this application, the term "electrical connection" can refer to two components being directly electrically connected, or it can refer to two components being electrically connected via one or more other components.

[0014] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0015] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0016] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: Currently, the pixel driving circuits used in display panels typically employ low-temperature polycrystalline silicon (LTPS) transistors. When displaying at low brightness and low grayscale, the driving transistors operate in the subthreshold region. Due to the poor uniformity of the subthreshold swing of LTPS transistors, driving transistors with larger subthreshold swings have higher currents, while those with smaller subthreshold swings have lower currents. This results in uneven display performance when displaying at low brightness and low grayscale, severely impacting the display effect.

[0017] If, to ensure display uniformity at low brightness and low grayscale levels, the driving transistor is replaced with an indium gallium zinc oxide (IGZO) transistor, the electron mobility of the IGZO transistor as a driving transistor is typically much lower than that of the LTPS transistor. In high-brightness displays, the light-emitting elements require a large driving current, necessitating a sufficiently high mobility of the driving transistor for rapid charging and stable current supply. The low mobility of the IGZO transistor limits its current output capability and response speed under high-brightness conditions, leading to insufficient charging of the light-emitting elements, prolonged charging time, and consequently, brightness differences between different light-emitting elements. This makes it difficult to guarantee the uniformity of the display panel under high-brightness conditions.

[0018] Therefore, how to balance the different needs of display panels under high and low brightness conditions and ensure that display panels have high display uniformity under different brightness levels has become a technical problem that urgently needs to be solved by those skilled in the art.

[0019] To address the aforementioned technical problems, this application provides a display panel and a display device. This application can take into account the different display requirements of the display panel under high brightness and low brightness conditions, thereby improving the display uniformity of the display panel under high brightness and low brightness conditions.

[0020] The various embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0021] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application, such as... Figure 1 As shown, the display panel includes a pixel driving circuit 10 and a light-emitting element 20.

[0022] The pixel driving circuit 10 includes a first driving transistor M11 and a second driving transistor M12; the first driving transistor M11 is coupled between the first power line PVDD and the first electrode of the light-emitting element 20, and the second driving transistor M12 is coupled between the first power line PVDD and the first electrode of the light-emitting element 20; the subthreshold swing of the first driving transistor M11 is greater than the subthreshold swing of the second driving transistor M12.

[0023] In the first brightness mode, the first driving transistor M11 connects the first power line PVDD to the first electrode of the light-emitting element 20.

[0024] In the second brightness mode, the second driving transistor M12 connects the first power line PVDD to the first electrode of the light-emitting element 20.

[0025] The brightness of the light-emitting element 20 in the first brightness mode is greater than the brightness of the light-emitting element 20 in the second brightness mode.

[0026] For example, the first brightness mode is a high-brightness, high-grayscale display mode. In this mode, the driving transistors in the pixel driving circuit 10 operate in the saturation region, requiring a large driving current. Therefore, the driving transistors need to have high electron mobility to ensure sufficient high-current driving capability. Simultaneously, the high electron mobility of the driving transistors allows for faster and more thorough compensation during the threshold compensation phase, effectively compensating for threshold voltage deviation and improving the display uniformity of the display panel. Transistors with larger subthreshold swings have higher electron mobility. Therefore, in the high-brightness, high-grayscale mode corresponding to the first brightness mode, the pixel driving circuit 10 turns on the first driving transistor M11 with a larger subthreshold swing, connecting the first power line PVDD to the first electrode of the light-emitting element 20.

[0027] The second brightness mode is a low-brightness, low-grayscale display mode. In this mode, the driving transistors in the pixel driving circuit 10 operate in the subthreshold region, where the driving current flowing through them is relatively small. For the driving transistors, the smaller the subthreshold swing, the more sensitive the gate voltage is to the drain current. This allows the display panel to achieve fine grayscale gradation within a smaller driving current range, thus avoiding severe brightness fluctuations in low-brightness, low-grayscale display conditions and improving display uniformity. Therefore, in the low-brightness, low-grayscale mode corresponding to the second brightness mode, the pixel driving circuit 10 turns on the second driving transistor M12, which has a smaller subthreshold swing, connecting the first power line PVDD to the first electrode of the light-emitting element 20.

[0028] As an example, the gates of the first driving transistor M11 and the second driving transistor M12 are connected to different control nodes. For instance, the gate of the first driving transistor M11 is connected to the first control node, and the gate of the second driving transistor M12 is connected to the second control node. In the first brightness mode, the first control node provides a conduction level, and the second control node provides a cutoff level, thereby connecting the first driving transistor M11 to the first power line PVDD and the first terminal of the light-emitting element 20, while the second driving transistor M12 remains disconnected. In the second brightness mode, the second control node provides a conduction level, and the first control node provides a cutoff level, thereby connecting the second driving transistor M12 to the first power line PVDD and the first terminal of the light-emitting element 20, while the first driving transistor M11 remains disconnected.

[0029] As another example, the gates of the first driving transistor M11 and the second driving transistor M12 are connected to the same control node. For instance, both the gates of the first driving transistor M11 and the second driving transistor M12 are connected to a third control node. During the light-emitting phase of the display panel, the third control node provides a conduction level that turns on both the first driving transistor M11 and the second driving transistor M12. To enable the first driving transistor M11 and the second driving transistor M12 to drive the light-emitting element 20 to emit light in different brightness modes, switching units can be provided on the conduction paths of the first driving transistor M11 and the second driving transistor M12, respectively. For example, the first driving transistor M11 and the first switching unit are coupled between the first power line PVDD and the first electrode of the light-emitting element 20, and the second driving transistor M12 and the second switching unit are coupled between the first power line PVDD and the first electrode of the light-emitting element 20.

[0030] In the first brightness mode, the third control node provides a conduction level, and the first switching unit is turned on, thereby connecting the first driving transistor M11 to the first power line PVDD and the first terminal of the light-emitting element 20. Although the second driving transistor M12 is turned on, the first power line PVDD remains disconnected through the conduction path between the second driving transistor M12 and the first terminal of the light-emitting element 20 because the second switching unit is turned off. In the second brightness mode, the third control node provides a conduction level, and the second switching unit is turned on, thereby connecting the second driving transistor M12 to the first power line PVDD and the first terminal of the light-emitting element 20. Although the first driving transistor M11 is turned on, the first power line PVDD remains disconnected through the conduction path between the first driving transistor M11 and the first terminal of the light-emitting element 20 because the first switching unit is turned off.

[0031] Because the first driving transistor M11 has a large subthreshold swing, its electron mobility is also higher, ensuring its high-current driving capability. In the high grayscale and high brightness conditions of the first brightness mode, the pixel driving circuit 10 requires a large driving current. Therefore, in the first brightness mode, the first driving transistor M11 is used to connect the first power line PVDD to the first electrode of the light-emitting element 20, thus meeting the requirement of the pixel driving circuit 10 to provide a large driving current. Furthermore, the high electron mobility of the first driving transistor M11 allows for faster and more thorough threshold voltage compensation during the threshold compensation stage, effectively compensating for the threshold voltage offset of the first driving transistor M11 and improving the display uniformity of the display panel. Therefore, in the first brightness mode, by connecting the first power line PVDD to the first electrode of the light-emitting element 20 through the first driving transistor M11, the display requirements of the display panel under high brightness conditions can be met, improving the display uniformity of the display panel.

[0032] In the low grayscale and low brightness mode of the second brightness mode, this application uses a second driving transistor M12 to connect the first power line PVDD to the first electrode of the light-emitting element 20. The second driving transistor M12 operates in the subthreshold region, at which time the driving current flowing through the second driving transistor M12 is relatively small. Because the subthreshold swing of the second driving transistor M12 is small, the gate voltage of the second driving transistor M12 can more sensitively control the drain current. Therefore, it is beneficial for the display panel to achieve fine grayscale gradation within a small driving current range, thereby avoiding severe brightness fluctuations in the display panel under low brightness and low grayscale display conditions, and thus improving the display uniformity of the display panel.

[0033] Therefore, this application can take into account the different display requirements of the display panel under high brightness and low brightness conditions, thereby improving the display uniformity of the display panel under high brightness and low brightness conditions.

[0034] In some embodiments, Figure 2 This is a structural example diagram of another pixel driving circuit provided in an embodiment of this application. Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application, as shown below. Figure 2 and Figure 3 As shown, the pixel driving circuit 10 also includes a first transistor M21 and a second transistor M22.

[0035] The first transistor M21 is connected in series with the first driving transistor M11, and the second transistor M22 is connected in series with the second driving transistor M12; the gates of the first driving transistor M11 and the second driving transistor M12 are both electrically connected to the first node N1; the gate of the first transistor M21 is connected to the first control terminal EN1, and the gate of the second transistor M22 is connected to the second control terminal EN2.

[0036] For example, see Figure 2 , Figure 2 An exemplary diagram shows a first transistor M21 above a first driving transistor M11, and a second transistor M22 above a second driving transistor M12. The first terminal of the first transistor M21 is connected to the first power line PVDD, and the second terminal of the first transistor M21 is connected to the first terminal of the first driving transistor M11. The second terminal of the first driving transistor M11 is connected to the light-emitting element 20. Similarly, the first terminal of the second transistor M22 is connected to the first power line PVDD, and the second terminal of the second transistor M22 is connected to the first terminal of the second driving transistor M12. The second terminal of the second driving transistor M12 is connected to the light-emitting element 20.

[0037] Figure 3 An exemplary diagram shows a first transistor M21 below a first driving transistor M11, and a second transistor M22 below a second driving transistor M12. The first terminal of the first driving transistor M11 is connected to the first power line PVDD, and the second terminal of the first driving transistor M11 is connected to the first terminal of the first transistor M21. The second terminal of the first transistor M21 is also connected to the light-emitting element 20. Similarly, the first terminal of the second driving transistor M12 is connected to the first power line PVDD, and the second terminal of the second driving transistor M12 is connected to the first terminal of the second transistor M22. The second terminal of the second transistor M22 is also connected to the light-emitting element 20.

[0038] It should be noted that, Figure 2 and Figure 3 The connection between the first driving transistor M11 and the first transistor M21 is shown only as an example. The connection between the second driving transistor M12 and the second transistor M22, as well as other circuit modules between the first driving transistors M11 and M21, and between the second driving transistors M12 and M22, are not shown. The connection between the first driving transistors M11 and M21, and between the second driving transistors M12 and M22, needs to be determined according to the actual situation, and is not specifically limited here.

[0039] In the first brightness mode, the first node N1 and the first control terminal EN1 are both at the on level, and the first driving transistor M11 and the first transistor M21 are connected to the first power line PVDD and the first pole of the light-emitting element 20.

[0040] For example, in the first brightness mode, the first node N1 is at the on level, at which time both the first driving transistor M11 and the second driving transistor M12 are turned on. The first control terminal EN1 also provides an on level, and the second control terminal EN2 provides an off level. Therefore, the first transistor M21 is turned on, and the second transistor M22 is turned off. Thus, the first driving transistor M11 and the first transistor M21 are connected to the first power line PVDD and the first electrode of the light-emitting element 20.

[0041] Because the first driving transistor M11 has a large subthreshold swing, its electron mobility is also higher, ensuring its high-current driving capability. In the high grayscale and high brightness conditions of the first brightness mode, this application uses the first driving transistor M11 and the first transistor M21 to connect the first power line PVDD to the first electrode of the light-emitting element 20, thereby meeting the requirement of the pixel driving circuit 10 to provide a large driving current. Furthermore, the high electron mobility of the first driving transistor M11 allows for faster and more thorough threshold voltage compensation during the threshold compensation stage, effectively compensating for the threshold voltage offset of the first driving transistor M11 and improving the display uniformity of the display panel. Therefore, in the first brightness mode, by connecting the first power line PVDD to the first electrode of the light-emitting element 20 using the first driving transistor M11, this application can meet the display requirements of the display panel under high brightness conditions, thus improving the display uniformity of the display panel.

[0042] In the second brightness mode, both the first node N1 and the second control terminal EN2 are at the on level, and the second driving transistor M12 and the second transistor M22 are connected to the first power line PVDD and the first pole of the light-emitting element 20.

[0043] For example, in the second brightness mode, the first node N1 is at the on level, at which time both the first driving transistor M11 and the second driving transistor M12 are turned on. The second control terminal EN2 also provides an on level, and the first control terminal EN1 provides an off level. Therefore, the second transistor M22 is turned on, and the first transistor M21 is turned off. Thus, the second driving transistor M12 and the second transistor M22 are connected to the first power line PVDD and the first electrode of the light-emitting element 20.

[0044] In the low grayscale and low brightness mode of the second brightness mode, this application uses a second driving transistor M12 and a second transistor M22 to connect the first power line PVDD to the first electrode of the light-emitting element 20. The second driving transistor M12 operates in the subthreshold region, at which time the driving current flowing through the second driving transistor M12 is relatively small. Because the subthreshold swing of the second driving transistor M12 is small, the gate voltage of the second driving transistor M12 can more sensitively control the drain current. Therefore, it is beneficial for the display panel to achieve fine grayscale gradation within a small driving current range, thereby avoiding severe brightness fluctuations in the display panel under low brightness and low grayscale display conditions, and thus improving the display uniformity of the display panel.

[0045] In some embodiments, Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application, as shown below. Figure 4 As shown, the first terminal of the first driving transistor M11 and the first terminal of the second driving transistor M12 are both electrically connected to the second node N2. The second terminal of the first driving transistor M11 is electrically connected to the first terminal of the first transistor M21. The second terminal of the first transistor M21 is electrically connected to the third node N3. The second terminal of the second driving transistor M12 is electrically connected to the first terminal of the second transistor M22. The second terminal of the second transistor M22 is electrically connected to the third node N3.

[0046] The pixel driving circuit further includes a data writing module 11 and a threshold compensation module 12. The threshold compensation module 12 is electrically connected to the first node N1, the third node N3, and the first scan signal terminal Scan1. The data writing module 11 is electrically connected to the second node N2, the data signal terminal Data, and the first scan signal terminal Scan1.

[0047] For example, the threshold compensation module 12 includes a first threshold compensation transistor M3, and the data writing module 11 includes a first data writing transistor M4. The gate of the first threshold compensation transistor M3 is connected to the first scan signal terminal Scan1, the first electrode of the first threshold compensation transistor M3 is connected to the first node N1, and the second electrode of the first threshold compensation transistor M3 is connected to the third node N3. The first electrode of the first data writing transistor M4 is connected to the data signal terminal Data, the gate of the first data writing transistor M4 is connected to the first scan signal terminal Scan1, and the second electrode of the first data writing transistor M4 is connected to the second node N2.

[0048] The first threshold compensation transistor M3 can be a dual-gate transistor.

[0049] The first driving transistor M11, the first transistor M21, the second driving transistor M12, and the second transistor M22 all write the data voltage provided by the data signal terminal Data to the second node N2 through the first data writing transistor M4. The first driving transistor M11, the first transistor M21, the second driving transistor M12, and the second transistor M22 all achieve threshold voltage compensation through the first threshold compensation transistor M3. This application ensures that the first driving transistor M11, the first transistor M21, the second driving transistor M12, and the second transistor M22 share the same threshold compensation module 12 and data writing module 11. Therefore, it can achieve the goal of accommodating different display requirements of the display panel under high and low brightness conditions while ensuring two different driving paths through the first driving transistor M11 and the second driving transistor M12, and also avoid an excessive number of transistors in the pixel driving circuit 10.

[0050] In some embodiments, see continue to see Figure 4 The pixel driving circuit 10 also includes a first reset module 13, a second reset module 14, a first capacitor C1, a first light emission control module 15, and a second light emission control module 16.

[0051] The first reset module 13 includes a first reset transistor M91, the second reset module 14 includes a second reset transistor M92, the first light emission control module 15 includes a first light emission control transistor M93, and the second light emission control module 16 includes a second light emission control transistor M94.

[0052] The first reset transistor M91 can be a dual-gate transistor.

[0053] The gate of the first reset transistor M91 is connected to the second scan signal terminal Scan2, the first terminal of the first reset transistor M91 is connected to the first reset signal terminal Vref1, and the second terminal of the first reset transistor M91 is connected to the first node N1. The first reset transistor M91 is used to reset the potential of the first node N1 to the potential of the first reset signal terminal Vref1 when the second scan signal terminal Scan2 provides a conduction level.

[0054] The gate of the second reset transistor M92 is connected to the second scan signal terminal Scan2, the first terminal of the second reset transistor M92 is connected to the second reset signal terminal Vref2, and the second terminal of the second reset transistor M92 is connected to the first terminal of the light-emitting element 20. The second reset transistor M92 is used to reset the potential of the first terminal of the light-emitting element 20 to the potential of the second reset signal terminal Vref2 when the second scan signal terminal Scan2 provides a conduction level.

[0055] The gate of the first light-emitting control transistor M93 is connected to the light-emitting control terminal Emit, the first terminal of the first light-emitting control transistor M93 is connected to the first power line PVDD, and the second terminal of the first light-emitting control transistor M93 is connected to the second node N2. The gate of the second light-emitting control transistor M94 is connected to the light-emitting control terminal Emit, the first terminal of the second light-emitting control transistor M94 is connected to the third node N3, and the second terminal of the second light-emitting control transistor M94 is connected to the first terminal of the light-emitting element 20. The first light-emitting control transistor M93 and the second light-emitting control transistor M94 are used to conduct when the light-emitting control terminal Emit provides a conduction level.

[0056] The first terminal of the first capacitor C1 is connected to the first power line PVDD, and the second terminal of the first capacitor C1 is connected to the first node N1.

[0057] Figure 5 This is a timing diagram of a pixel driving circuit provided in an embodiment of this application, as shown below. Figure 5 As shown, for example, if all transistors in the pixel driving circuit 10 are P-type transistors, then the on-level is low and the off-level is high. During the first time period T1, the first scan signal terminal Scan1 provides an on-level, and the pixel driving circuit 10 is in the reset phase. During the second time period T2, the second scan signal terminal Scan2 provides an on-level, and the pixel driving circuit 10 is in the data writing phase and the threshold compensation phase. During both the first time period T1 and the second time period T2, the light emission control terminal Emit provides an on-level, and the pixel driving circuit 10 is in the light emission phase.

[0058] In some embodiments, Figure 6 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application, as shown below. Figure 6 As shown, the first terminal of the first driving transistor M11 is electrically connected to the second node N2, the second terminal of the first driving transistor M11 is electrically connected to the first terminal of the first transistor M21, and the second terminal of the first transistor M21 is electrically connected to the third node N3. The first terminal of the second driving transistor M12 is electrically connected to the fourth node N4, the second terminal of the second driving transistor M12 is electrically connected to the first terminal of the second transistor M22, and the second terminal of the second transistor M22 is electrically connected to the fifth node N5.

[0059] The pixel driving circuit also includes a data writing module 11 and a threshold compensation module 12. The threshold compensation module 12 includes a second threshold compensation transistor M5 and a third threshold compensation transistor M6, and the data writing module 11 includes a second data writing transistor M7 and a third data writing transistor M8.

[0060] The gate of the second threshold compensation transistor M5 is connected to the first scan signal terminal Scan1, the first terminal of the second threshold compensation transistor M5 is connected to the first node N1, and the second terminal of the second threshold compensation transistor M5 is connected to the third node N3. The first terminal of the second data writing transistor M7 is connected to the data signal terminal Data, the gate of the second data writing transistor M7 is connected to the first scan signal terminal Scan1, and the second terminal of the second data writing transistor M7 is connected to the second node N2.

[0061] The gate of the third threshold compensation transistor M6 is connected to the first scan signal terminal Scan1, the first terminal of the third threshold compensation transistor M6 is connected to the first node N1, and the second terminal of the third threshold compensation transistor M6 is connected to the fifth node N5. The first terminal of the third data writing transistor M8 is connected to the data signal terminal Data, the gate of the third data writing transistor M8 is connected to the first scan signal terminal Scan1, and the second terminal of the third data writing transistor M8 is connected to the fourth node N4.

[0062] The first driving transistors M11 and M21 achieve threshold voltage compensation through the second threshold compensation transistor M5. The first driving transistors M11 and M21 also write the data voltage provided by the data signal terminal Data to the second node N2 through the second data writing transistor M7. The second driving transistors M12 and M22 achieve threshold voltage compensation through the third threshold compensation transistor M6. The second driving transistors M12 and M22 also write the data voltage provided by the data signal terminal Data to the fourth node N4 through the third data writing transistor M8. This application employs different threshold compensation modules 12 and data writing modules 11 for the first driving transistors M11 and M21, and for the second driving transistors M12 and M22. Therefore, when the first driving transistor M11 is used as the driving transistor, and when the second driving transistor M12 is used as the driving transistor, the data writing module 11 and the threshold compensation module 12 can use different types of transistors to adapt to the needs of the display panel at different brightness levels.

[0063] It should be noted that, Figure 6 The data writing module 11 and the threshold compensation module 12 are only schematically shown to illustrate the connection relationship between the data writing module 11 and the threshold compensation module 12 and the first driving transistor M11 and the first transistor M21, the second driving transistor M12 and the second transistor M22.

[0064] It should be noted that, Figure 4 and Figure 6 The transistors shown are P-type transistors. Each transistor can also be an N-type transistor; no specific limitation is made here.

[0065] In some embodiments, the first control terminal EN1 is electrically connected to the first control signal line, and the second control terminal EN2 is electrically connected to the second control signal line.

[0066] In the first brightness mode, the first control signal line provides an on level, and the second control signal line provides an off level.

[0067] In the second brightness mode, the second control signal line provides an on level, and the first control signal line provides an off level.

[0068] For example, see [link to previous article] Figure 5 Taking a pixel driving circuit where all transistors are P-type as an example, the on-state level is low and the off-state level is high. In the high grayscale and high brightness mode of the first brightness mode, the first control signal line provides an on-state level to the first control terminal EN1, and the second control signal line provides an off-state level to the second control terminal EN2. The first node N1 is on-state, therefore the first driving transistor M11 and the second driving transistor M12 are both on, the first transistor M21 is on, and the second transistor M22 is off. This allows the first driving transistor M11 and the first transistor M21 to connect the first power line PVDD to the first electrode of the light-emitting element 20 in the first brightness mode.

[0069] In the low grayscale and low brightness mode of the second brightness mode, the first control signal line provides a cutoff level to the first control terminal EN1, and the second control signal line provides a conduction level to the second control terminal EN2. The first node N1 is at the conduction level, therefore both the first driving transistor M11 and the second driving transistor M12 are turned on, the first transistor M21 is turned off, and the second transistor M22 is turned on. This allows the second driving transistors M12 and M22 to connect the first power line PVDD to the first electrode of the light-emitting element 20 in the second brightness mode.

[0070] The first and second control signal lines configured in this application can provide on and off levels respectively according to the first and second brightness modes. When the first control signal line provides an on level, the second control signal line provides an off level, and vice versa. The signals provided by the first and second control signal lines are always at opposite levels. Therefore, it can be determined that only one driving path is on in either the first or second brightness mode, avoiding the problem of abnormal light emission caused by the first and second transistors being on simultaneously.

[0071] In some embodiments, Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application, such as... Figure 7As shown, the display panel includes multiple pixel driving circuits 10 arranged in an array.

[0072] The first control terminal EN1 of at least one row of pixel driving circuit 10 is electrically connected to the same first control signal line 31; the second control terminal EN2 of at least one row of pixel driving circuit 10 is electrically connected to the same second control signal line 32.

[0073] For example, when the entire display panel displays the same grayscale, the first control terminal EN1 of all pixel driving circuits 10 of the display panel is electrically connected to the same first control signal line 31, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same second control signal line 32. That is, the display panel is provided with a first control signal line 31 and a second control signal line 32.

[0074] When the entire display panel is in the first brightness mode, the first control signal line 31 provides a conduction level, and the second control signal line provides a cutoff level. Within all pixel driving circuits 10 in the display panel, the first power line PVDD is connected to the first electrode of the light-emitting element 20 via the first driving transistor M11 and the first transistor M21. When the entire display panel is in the second brightness mode, the first control signal line 31 provides a cutoff level, and the second control signal line 32 provides a conduction level. Within all pixel driving circuits 10 in the display panel, the second driving transistors M12 and M22 are connected to the first power line PVDD and the first electrode of the light-emitting element 20.

[0075] In the case where the display panel displays the same grayscale in different areas, the display panel includes a first display area, a second display area, and a third display area. In the first display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same first control signal line 31, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same second control signal line 32. Similarly, in the second display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same first control signal line 31, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same second control signal line 32. In the third display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same first control signal line 31, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same second control signal line 32. That is, the display panel has three first control signal lines 31 and three second control signal lines 32.

[0076] When the first display area is in the first brightness mode, and the second and third display areas are in the second brightness mode, the first control signal line 31 connected to the first display area provides a conduction level, the second control signal line connected to the first display area provides a cutoff level, the first control signal line 31 connected to the second and third display areas provides a cutoff level, and the second control signal line connected to the second and third display areas provides a conduction level. Therefore, all pixel driving circuits 10 in the first display area are connected to the first power line PVDD and the first electrode of the light-emitting element 20 through the first driving transistor M11 and the first transistor M21. All pixel driving circuits 10 in the second and third display areas are connected to the first power line PVDD and the first electrode of the light-emitting element 20 through the second driving transistor M12 and the second transistor M22.

[0077] When the first display area is in the second brightness mode, the second display area is in the first brightness mode, and the third display area is in the second brightness mode, the first control signal line 31 connected to the second display area provides a conduction level, the second control signal line connected to the second display area provides a cutoff level, the first control signal line 31 connected to both the first and third display areas provides a cutoff level, and the second control signal line connected to both the first and third display areas provides a conduction level. Therefore, all pixel driving circuits 10 in the second display area are connected to the first power line PVDD and the first electrode of the light-emitting element 20 through the first driving transistor M11 and the first transistor M21. All pixel driving circuits 10 in both the first and third display areas are connected to the first power line PVDD and the first electrode of the light-emitting element 20 through the second driving transistor M12 and the second transistor M22.

[0078] It should be noted that, Figure 7 The illustration only shows that all pixel driving circuits 10 of the display panel are connected to a first control signal line 31 and a second control signal line 32. The number of first control signal lines 31 and second control signal lines 32 provided in the display panel needs to be determined according to the number of areas in the display panel used to display the same gray level. For example, if the display panel has three display areas that can display different gray levels, then the number of first control signal lines 31 and second control signal lines 32 is three each. If the display panel has five display areas that can display different gray levels, then the number of first control signal lines 31 and second control signal lines 32 is five each. The number of first control signal lines 31 and second control signal lines 32 provided in the display panel needs to be determined according to the actual situation, and is not specifically limited here.

[0079] In some embodiments, Figure 8This is a schematic diagram of another display panel provided in an embodiment of this application. Figure 9 This is a schematic diagram of another display panel provided in an embodiment of this application, as shown below. Figure 8 and Figure 9 As shown, the display panel also includes an inverter module 40.

[0080] The first control terminal EN1 is electrically connected to the third control signal line 33, and the third control signal line 33 is electrically connected to the second control terminal EN2 through the inverting module 40.

[0081] In the first brightness mode, the third control signal line 33 provides an on level; in the second brightness mode, the third control signal line 33 provides an off level.

[0082] For example, see Figure 8 In the high grayscale and high brightness mode of the first brightness mode, the third control signal line 33 provides a conduction level to the first control terminal EN1, and the third control signal line 33 provides a cutoff level to the second control terminal EN2 through the inverting module 40. The first node N1 is at the conduction level, so the first driving transistor M11 and the second driving transistor M12 are both turned on, the first transistor M21 is turned on, and the second transistor M22 is turned off. This makes the first driving transistor M11 and the first transistor M21 connected to the first power line PVDD and the first electrode of the light-emitting element 20 in the first brightness mode.

[0083] In the low grayscale and low brightness mode of the second brightness mode, the third control signal line 33 provides a cutoff level to the first control terminal EN1, and the third control signal line 33 provides a conduction level to the second control terminal EN2 through the inverting module 40. The first node N1 is at the conduction level, so both the first driving transistor M11 and the second driving transistor M12 are turned on, the first transistor M21 is turned off, and the second transistor M22 is turned on. This allows the second driving transistors M12 and M22 to connect the first power line PVDD to the first electrode of the light-emitting element 20 in the second brightness mode.

[0084] Alternatively, the second control terminal EN2 is electrically connected to the third control signal line 33, and the third control signal line 33 is electrically connected to the first control terminal EN1 through the inverting module 40.

[0085] In the first brightness mode, the third control signal line 33 provides a cutoff level; in the second brightness mode, the third control signal line 33 provides a conduction level.

[0086] For example, see Figure 9In the high grayscale and high brightness mode of the first brightness mode, the third control signal line 33 provides a conduction level to the first control terminal EN1 through the inverting module 40, and provides a cutoff level to the second control terminal EN2. The first node N1 is at the conduction level, so both the first driving transistor M11 and the second driving transistor M12 are turned on, the first transistor M21 is turned on, and the second transistor M22 is turned off. This allows the first driving transistor M11 and the first transistor M21 to connect the first power line PVDD to the first electrode of the light-emitting element 20 in the first brightness mode.

[0087] In the low grayscale and low brightness mode of the second brightness mode, the third control signal line 33 provides a cutoff level to the first control terminal EN1 through the inverting module 40, and provides a conduction level to the second control terminal EN2. The first node N1 is at the conduction level, therefore both the first driving transistor M11 and the second driving transistor M12 are turned on, the first transistor M21 is turned off, and the second transistor M22 is turned on. This allows the second driving transistors M12 and M22 to connect the first power line PVDD to the first electrode of the light-emitting element 20 in the second brightness mode.

[0088] Therefore, this application can achieve the simultaneous provision of a conduction level to the first transistor M21 and a cutoff level to the second transistor M22, and the simultaneous provision of a cutoff level to the first transistor M21 and a conduction level to the second transistor M22, by simply setting the third control signal line 33 and the inverting module 40. No additional control signal lines are required, which is beneficial for the narrow bezel design of the display panel.

[0089] In some embodiments, Figure 10 This is a schematic diagram of the structure of an inverting module provided in an embodiment of this application, as shown below. Figure 10 As shown, the inverter module 40 includes a third transistor M41 and a fourth transistor M42.

[0090] The gates of the third transistor M41 and the fourth transistor M42 are both electrically connected to the third control signal line 33. The first terminal of the third transistor M41 is electrically connected to the first power supply terminal 34. The second terminal of the third transistor M41 and the first terminal of the fourth transistor M42 are both electrically connected to the first control terminal EN1 or the second control terminal EN2. The second terminal of the fourth transistor M42 is electrically connected to the second power supply terminal 35.

[0091] The inverting module 40 is used to invert the level provided by the third control signal line 33.

[0092] Among them, the third transistor M41 is a second type transistor, and the fourth transistor M42 is a first type transistor; either the third transistor M41 or the fourth transistor M42 is a P-type transistor, and the other is an N-type transistor.

[0093] For example, taking a third transistor M41 as a P-type transistor, a fourth transistor M42 as an N-type transistor, a first power supply terminal 34 providing a high-level signal, and a second power supply terminal 35 providing a low-level signal as an example. When the third control signal line 33 provides a low-level signal, the third transistor M41 is turned on, the fourth transistor M42 is turned off, and the first power supply terminal 34 is connected to the first control terminal EN1 or the second control terminal EN2 through the turned-on third transistor M41, thereby providing a high-level signal to the first control terminal EN1 or the second control terminal EN2. When the third control signal line 33 provides a high-level signal, the third transistor M41 is turned off, the fourth transistor M42 is turned on, and the second power supply terminal 35 is connected to the first control terminal EN1 or the second control terminal EN2 through the turned-on fourth transistor M42, thereby providing a low-level signal to the first control terminal EN1 or the second control terminal EN2. Therefore, this application uses the inverting module 40 to invert the level provided by the third control signal line 33. This allows the display panel to provide a conduction level to the first transistor M21 and a cutoff level to the second transistor M22, and vice versa, by simply setting the third control signal line 33. No additional control signal line is required, which is beneficial for the narrow bezel design of the display panel.

[0094] In some embodiments, see continue to see Figure 8 and Figure 9 The display panel includes multiple pixel driving circuits 10 arranged in an array.

[0095] At least one row of pixel driving circuit 10 has its first control terminal EN1 electrically connected to the same third control signal line 33.

[0096] At least one row of pixel driving circuit 10 has its second control terminal EN2 electrically connected to the same third control signal line 33 through the inverting module 40.

[0097] For example, see Figure 8 In cases where the entire display panel displays the same grayscale, for example, the first control terminal EN1 of all pixel driving circuits 10 of the display panel is electrically connected to the same third control signal line 33, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 through the inverting module 40. That is, the display panel is provided with a third control signal line 33.

[0098] In the case where the display panel displays the same grayscale in different areas, the display panel includes a first display area, a second display area, and a third display area. In the first display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 through an inverter module 40. Similarly, in the second display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 through an inverter module 40. In the third display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 through an inverter module 40. That is, the display panel has three third control signal lines 33.

[0099] Alternatively, at least one row of pixel driving circuit 10 may have its second control terminal EN2 electrically connected to the same third control signal line 33.

[0100] At least one row of pixel driving circuit 10 has its first control terminal EN1 electrically connected to the same third control signal line 33 through the inverting module 40.

[0101] For example, see Figure 9 In cases where the entire display panel displays the same grayscale, for example, the first control terminal EN1 of all pixel driving circuits 10 of the display panel is electrically connected to the same third control signal line 33 through the inverting module 40, and the second control terminal EN2 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33. That is, the display panel is provided with a third control signal line 33.

[0102] In the case where the display panel displays the same grayscale in different areas, the display panel includes a first display area, a second display area, and a third display area. In the first display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 via the inverting module 40, and the second control terminal EN2 of all pixel driving circuits 10 is also electrically connected to the same third control signal line 33. Similarly, in the second display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 via the inverting module 40, and the second control terminal EN2 of all pixel driving circuits 10 is also electrically connected to the same third control signal line 33. In the third display area, the first control terminal EN1 of all pixel driving circuits 10 is electrically connected to the same third control signal line 33 via the inverting module 40, and the second control terminal EN2 of all pixel driving circuits 10 is also electrically connected to the same third control signal line 33. That is, the display panel has three third control signal lines 33.

[0103] It should be noted that, Figure 8 and Figure 9 The illustration only shows that all pixel driving circuits 10 of the display panel are connected to a third control signal line 33. The number of third control signal lines 33 provided in the display panel needs to be determined according to the number of areas in the display panel used to display the same gray level. For example, if the display panel has three display areas that can display different gray levels, then the number of third control signal lines 33 is three. If the display panel has five display areas that can display different gray levels, then the number of third control signal lines 33 is five. The number of third control signal lines 33 provided in the display panel needs to be determined according to the actual situation, and is not specifically limited here.

[0104] In some embodiments, the first driving transistor is a low-temperature polycrystalline silicon transistor; the second driving transistor is an indium gallium zinc oxide thin-film transistor.

[0105] For example, the subthreshold swing of a low-temperature polycrystalline silicon transistor is greater than that of an indium gallium zinc oxide thin-film transistor.

[0106] In the high grayscale and high brightness mode of the first brightness mode, the driving transistor in the pixel driving circuit 10 operates in the saturation region, requiring a large driving current. Therefore, the driving transistor needs to have a high electron mobility to ensure sufficient high-current driving capability. Simultaneously, the high electron mobility of the driving transistor enables faster and more thorough compensation during the threshold compensation phase, effectively compensating for the threshold voltage offset and improving the display uniformity of the display panel. The electron mobility of low-temperature polysilicon transistors (LTPS) is higher than that of indium gallium zinc oxide (IZO) thin-film transistors (ICPs). Therefore, in the high brightness and high grayscale mode corresponding to the first brightness mode, the pixel driving circuit 10 turns on the LPS with a larger subthreshold swing, connecting the first power line PVDD to the first electrode of the light-emitting element 20.

[0107] In the low brightness and low grayscale conditions of the second brightness mode, the driving transistor in the pixel driving circuit 10 operates in the subthreshold region, where the driving current flowing through the driving transistor is relatively small. For the driving transistor, the smaller the subthreshold swing, the more sensitive the gate voltage of the driving transistor is to the control of the drain current. This is beneficial for the display panel to achieve fine grayscale gradation within a smaller driving current range, thereby avoiding severe brightness fluctuations in low brightness and low grayscale display conditions and improving the display uniformity of the display panel. Therefore, in the low brightness and low grayscale conditions corresponding to the second brightness mode, the pixel driving circuit 10 turns on the indium gallium zinc oxide thin-film transistor with a smaller subthreshold swing, connecting the first power line PVDD to the first electrode of the light-emitting element 20.

[0108] In some embodiments, the channel width-to-length ratio of the first driving transistor is greater than that of the second driving transistor.

[0109] For example, the channel width-to-length ratio of a transistor is the ratio of the transistor's channel width to its channel length. The larger the channel width-to-length ratio, the larger the area occupied by the transistor; conversely, the smaller the channel width-to-length ratio, the smaller the area occupied by the transistor.

[0110] In the low grayscale and low brightness conditions of the second brightness mode, a second driving transistor is used to connect the first power line and the first electrode of the light-emitting element. Because the second driving transistor has a small subthreshold swing and a small channel width-to-length ratio, it is not necessary to adjust the gate-source voltage of the second driving transistor to the subthreshold region close to the threshold voltage when extremely small driving currents are required. As long as the difference between the gate-source voltage and the threshold voltage remains sufficiently large, the second driving transistor can operate stably in the strong inversion saturation region. This significantly improves the current uniformity among the light-emitting elements under low brightness conditions, ensuring the display uniformity of the display panel. Furthermore, it avoids the second driving transistor occupying a large area, which is beneficial for the narrow bezel design of the display panel.

[0111] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 11 , Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 11 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 11 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0112] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, Includes pixel driving circuitry and light-emitting elements; The pixel driving circuit includes a first driving transistor and a second driving transistor; the first driving transistor is coupled between a first power line and a first electrode of the light-emitting element, and the second driving transistor is coupled between the first power line and the first electrode of the light-emitting element; the subthreshold swing of the first driving transistor is greater than the subthreshold swing of the second driving transistor. In the first brightness mode, the first driving transistor connects the first power line to the first electrode of the light-emitting element; In the second brightness mode, the second driving transistor connects the first power line to the first electrode of the light-emitting element; The brightness of the light-emitting element in the first brightness mode is greater than the brightness of the light-emitting element in the second brightness mode.

2. The display panel according to claim 1, characterized in that, The pixel driving circuit also includes a first transistor and a second transistor; The first transistor is connected in series with the first driving transistor, and the second transistor is connected in series with the second driving transistor; the gates of the first driving transistor and the second driving transistor are both electrically connected to the first node; the gate of the first transistor is connected to the first control terminal, and the gate of the second transistor is connected to the second control terminal. In the first brightness mode, both the first node and the first control terminal are at the on level, and the first driving transistor and the first transistor are connected to the first power line and the first pole of the light-emitting element. In the second brightness mode, both the first node and the second control terminal are at the on level, and the second driving transistor and the second transistor are connected to the first power line and the first electrode of the light-emitting element.

3. The display panel according to claim 2, characterized in that, The first terminal of the first driving transistor and the first terminal of the second driving transistor are both electrically connected to the second node. The second terminal of the first driving transistor is electrically connected to the first terminal of the first transistor. The second terminal of the first transistor is electrically connected to the third node. The second terminal of the second driving transistor is electrically connected to the first terminal of the second transistor. The second terminal of the second transistor is electrically connected to the third node. The pixel driving circuit further includes a data writing module and a threshold compensation module. The threshold compensation module is electrically connected to the first node, the third node, and the first scan signal terminal, respectively. The data writing module is electrically connected to the second node, the data signal terminal, and the first scan signal terminal, respectively.

4. The display panel according to claim 2, characterized in that, The first control terminal is electrically connected to the first control signal line, and the second control terminal is electrically connected to the second control signal line; In the first brightness mode, the first control signal line provides a conduction level, and the second control signal line provides a cutoff level; In the second brightness mode, the second control signal line provides an on level, and the first control signal line provides an off level.

5. The display panel according to claim 4, characterized in that, The display panel includes multiple pixel driving circuits arranged in an array; The first control terminals of at least one row of pixel driving circuits are all electrically connected to the same first control signal line; At least one of the pixel driving circuits has its second control terminal electrically connected to the same second control signal line.

6. The display panel according to claim 2, characterized in that, It also includes an inverting module; The first control terminal is electrically connected to the third control signal line, and the third control signal line is electrically connected to the second control terminal through the inverting module; In the first brightness mode, the third control signal line provides a conduction level; In the second brightness mode, the third control signal line provides a cutoff level; Alternatively, the second control terminal is electrically connected to the third control signal line, and the third control signal line is electrically connected to the first control terminal through the inverting module; In the first brightness mode, the third control signal line provides a cutoff level; In the second brightness mode, the third control signal line provides a conduction level.

7. The display panel according to claim 6, characterized in that, The inverting module includes a third transistor and a fourth transistor; The gate of the third transistor and the gate of the fourth transistor are both electrically connected to the third control signal line. The first terminal of the third transistor is electrically connected to the first power supply terminal. The second terminal of the third transistor and the first terminal of the fourth transistor are both electrically connected to the first control terminal or the second control terminal. The second terminal of the fourth transistor is electrically connected to the second power supply terminal. The inverting module is used to invert the level provided by the third control signal line; The third transistor is a second type transistor, and the fourth transistor is a first type transistor; One of the third transistor and the fourth transistor is a P-type transistor, and the other is an N-type transistor.

8. The display panel according to claim 6, characterized in that, The display panel includes multiple pixel driving circuits arranged in an array; The first control terminals of at least one row of pixel driving circuits are all electrically connected to the same third control signal line; At least one row of the pixel driving circuits has its second control terminal electrically connected to the same third control signal line through the inverting module; Alternatively, at least one of the second control terminals of the pixel driving circuits described in the first row is electrically connected to the same third control signal line; The first control terminal of at least one row of pixel driving circuits is electrically connected to the same third control signal line through the inverting module.

9. The display panel according to claim 1, characterized in that, The first driving transistor is a low-temperature polysilicon transistor; The second driving transistor is an indium gallium zinc oxide thin film transistor.

10. The display panel according to claim 1, characterized in that, The channel width-to-length ratio of the first driving transistor is greater than that of the second driving transistor.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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