Display panel and display device
By introducing auxiliary signal lines with impedance lower than that of the output signal lines in a different layer into the display panel, the problem of signal inconsistency between the edge and center areas of the display panel is solved, resulting in better display uniformity and effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI VISIONOX TECH CO LTD
- Filing Date
- 2024-12-26
- Publication Date
- 2026-05-26
Smart Images
Figure CN119626125B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] With the development of display technology, people have increasingly higher requirements for the performance of display panels.
[0003] Display panels typically include pixel circuits and gate drive circuits. The gate drive circuits output gate drive signals to the pixel circuits to drive them. However, existing display panels have shortcomings in display quality. Summary of the Invention
[0004] This invention provides a display panel and a display device to improve the display effect of the display panel.
[0005] According to one aspect of the present invention, a display panel is provided, comprising:
[0006] A substrate on which multiple pixel circuits are arranged in an array;
[0007] A gate driving circuit and multiple output signal lines are provided, wherein the gate driving circuit is connected to the corresponding output signal lines, and the output signal lines are used to output the gate control signal generated by the gate driving circuit.
[0008] Multiple auxiliary signal lines are connected between the output signal lines and the pixel circuit. The auxiliary signal lines are used to transmit the gate control signal on the output signal lines to the pixel circuit.
[0009] In this configuration, at least a portion of the auxiliary signal lines are disposed on different layers from the output signal lines, and the impedance of the auxiliary signal lines is less than the impedance of the output signal lines.
[0010] Optionally, the display panel includes a display area and a non-display area disposed around at least a portion of the display area, the gate driving circuit and the output signal line are located in the non-display area, and the pixel circuit is located in the display area;
[0011] The auxiliary signal lines extend from the non-display area to the display area, and extend along a first direction in the display area; the plurality of auxiliary signal lines are arranged along a second direction; wherein the first direction intersects the second direction.
[0012] Optionally, the multiple auxiliary signal lines are arranged on the same layer.
[0013] Optionally, the display panel further includes multiple gate control signal lines, which are disposed on different layers from the auxiliary signal lines. The auxiliary signal lines are connected to the gate control signal lines through a switching hole, and the gate control signal lines are connected to the pixel circuit.
[0014] Optionally, at least a portion of the auxiliary signal line's orthographic projection on the substrate covers at least a portion of the gate control signal line's orthographic projection on the substrate, thereby achieving the self-shielding effect of the auxiliary signal line and ensuring the stability of the gate control signal it transmits.
[0015] Optionally, along the first direction, the length of the auxiliary signal line is greater than the length of the gate control signal line, which helps to reduce the impedance change of the auxiliary signal line at the line switching connection and ensure the uniformity of the impedance of the auxiliary signal line.
[0016] Optionally, the plurality of auxiliary signal lines extend along the first direction and are arranged along the second direction, wherein the first direction intersects the second direction;
[0017] Optionally, multiple gate control signal lines are arranged on the same layer;
[0018] Optionally, the auxiliary signal line is connected to the output signal line through the cable switching hole;
[0019] Optionally, the display panel further includes an active layer, the pixel circuit includes a plurality of transistors, the gate control signal line overlaps with the active layer to form the gate of the transistor, and the auxiliary signal line is connected to the gate of the transistor through the switching hole;
[0020] Optionally, the gate control signal lines connected to the same auxiliary signal line between adjacent pixel circuits can be either a single integrated structure or segmented independent structures.
[0021] Optionally, the display panel includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially on one side of the substrate;
[0022] The output signal line is located in the first metal layer and / or the second metal layer, the gate control signal line is located in the first metal layer, and the auxiliary signal line is located in the third metal layer;
[0023] Optionally, both the first metal layer and the second metal layer include a molybdenum layer, and the third metal layer includes a first titanium layer, an aluminum layer, and a second titanium layer stacked together.
[0024] Optionally, the gate control signal line includes a first gate control signal line, the auxiliary signal line includes a first auxiliary signal line, the output signal line includes a first output signal line, one end of the first auxiliary signal line is connected to the first output signal line through the switching hole, and the other end of the first auxiliary signal line is connected to the first gate control signal line through the switching hole.
[0025] The pixel circuit includes a driving transistor and a data writing transistor. The first gate control signal line overlaps with the active layer to form the data writing transistor. The data writing transistor is connected between the data line and the second electrode of the driving transistor.
[0026] Optionally, the pixel circuit further includes a compensation transistor, wherein the first gate control signal line overlaps with the active layer to form the compensation transistor, and the compensation transistor is connected between the gate of the driving transistor and the first electrode;
[0027] Optionally, the pixel circuit further includes a storage capacitor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to a fixed voltage; alternatively, the gate of the driving transistor is reused as the first terminal of the storage capacitor.
[0028] Optionally, the orthographic projection of the first auxiliary signal line on the substrate and the orthographic projection of the first gate control signal line on the substrate do not overlap;
[0029] Optionally, the first gate control signal line includes a main body, a first branch, and a second branch. The main body extends along a first direction, the first branch extends along a second direction, and the second branch extends in the opposite direction to the second direction. The main body overlaps with the active layer to form the data write transistor, the first branch overlaps with the active layer to form the compensation transistor, and the second branch is connected to the first auxiliary signal line through the switching hole.
[0030] Optionally, the orthographic projection of the first auxiliary signal line on the substrate covers at least a portion of the orthographic projection of the first gate control signal line on the substrate;
[0031] Optionally, the first gate control signal line includes a main body and a first branch. The main body extends along a first direction, and the first branch extends along a second direction. The main body overlaps with the active layer to form the data write transistor, and the first branch and / or the main body overlaps with the active layer to form the compensation transistor. The main body and / or the first branch are connected to the first auxiliary signal line through the switching hole.
[0032] Optionally, the gate control signal line further includes a second gate control signal line, the auxiliary signal line further includes a second auxiliary signal line, and the output signal line further includes a second output signal line. One end of the second auxiliary signal line is connected to the second output signal line through the switching hole, and the other end of the second auxiliary signal line is connected to the second gate control signal line through the switching hole.
[0033] Optionally, the orthographic projection of the second auxiliary signal line on the substrate covers at least a portion of the orthographic projection of the second gate control signal line on the substrate;
[0034] Optionally, the display panel further includes a first initialization signal line, which is disposed on a different layer from the second auxiliary signal line;
[0035] The pixel circuit further includes a first initialization transistor, wherein the second gate control signal line overlaps with the active layer to form the first initialization transistor, and the first initialization transistor is connected between the first initialization signal line and the gate of the driving transistor.
[0036] Optionally, the gate control signal line further includes a third gate control signal line, the auxiliary signal line further includes a third auxiliary signal line, and the output signal line further includes a third output signal line. One end of the third auxiliary signal line is connected to the third output signal line through the line switching hole, and the other end of the third auxiliary signal line is connected to the third gate control signal line through the line switching hole.
[0037] The orthographic projection of the third auxiliary signal line on the substrate covers at least a portion of the orthographic projection of the third gate control signal line on the substrate;
[0038] Optionally, the display panel further includes a second initialization signal line, which is disposed on the same layer as the first initialization signal line;
[0039] The pixel circuit further includes a second initialization transistor, wherein the third gate control signal line overlaps with the active layer to form the second initialization transistor, and the second initialization transistor is connected between the second initialization signal line and the light-emitting element;
[0040] Optionally, the gate control signal line further includes a light emission control signal line, the auxiliary signal line further includes a fourth auxiliary signal line, the output signal line further includes a fourth output signal line, one end of the fourth auxiliary signal line is connected to the fourth output signal line through the line switching hole, and the other end of the fourth auxiliary signal line is connected to the light emission control signal line through the line switching hole.
[0041] The orthographic projection of the fourth auxiliary signal line onto the substrate covers at least a portion of the orthographic projection of the light-emitting control signal line onto the substrate;
[0042] Optionally, the display panel further includes a first power line and a second power line, and the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The light-emitting control signal line overlaps with the active layer to form the first light-emitting control transistor and the second light-emitting control transistor, respectively. The first light-emitting control transistor is connected between the first power line and the second terminal of the driving transistor, and the second light-emitting control transistor is connected between the first terminal of the driving transistor and the first terminal of the light-emitting element. The second terminal of the light-emitting element is connected to the second power line.
[0043] Optionally, the orthographic projection of the first auxiliary signal line on the substrate is located between the orthographic projection of the second auxiliary signal line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the fourth auxiliary signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the third auxiliary signal line on the substrate.
[0044] Optionally, the display panel further includes an active layer, the pixel circuit includes multiple transistors, and the auxiliary signal line overlaps with the active layer to form the gate of the transistor, which can reduce the number of signal lines and thus optimize the layout.
[0045] Optionally, the auxiliary signal line is connected to the gate of the transistor.
[0046] According to another aspect of the present invention, a display device is provided, which includes a display panel provided in any embodiment of the present invention.
[0047] The technical solution provided in this embodiment of the invention connects the output signal line and the pixel circuit through an auxiliary signal line to transmit the gate control signal output by the gate driving circuit to the pixel circuit. The impedance of the auxiliary signal line is less than that of the output signal line to reduce the impedance of the signal line transmitting the gate control signal. This helps to reduce the transmission voltage drop of the gate control signal, ensures the consistency of the gate control signal between the edge and middle areas of the display panel, reduces the display difference between the edge and middle areas of the display panel, and improves display uniformity and display effect.
[0048] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0050] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention;
[0051] Figure 2 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;
[0052] Figure 3 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;
[0053] Figure 4 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;
[0054] Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;
[0055] Figure 6 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;
[0056] Figure 7 A cross-sectional structural diagram of another display panel provided in an embodiment of the present invention;
[0057] Figure 8 A cross-sectional structural diagram of another display panel provided in an embodiment of the present invention;
[0058] Figure 9 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;
[0059] Figure 10 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;
[0060] Figure 11 This is a waveform diagram of a gate control signal provided in the prior art;
[0061] Figure 12 A waveform diagram of a gate control signal provided in an embodiment of the present invention;
[0062] Figure 13 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;
[0063] Figure 14This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation
[0064] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0065] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0066] Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, specifically... Figure 1 The cross-sectional structure of the display panel shown is obtained along the section line AA', for reference. Figure 1 and Figure 2 The display panel provided in this embodiment includes:
[0067] Substrate 10, on which multiple pixel circuits PX are arranged in an array;
[0068] The gate drive circuit GD and multiple output signal lines 100 are connected to each other. The output signal lines 100 are used to output the gate control signal generated by the gate drive circuit GD.
[0069] Multiple auxiliary signal lines 200 (e.g.) Figure 1 (As shown by the red line in the middle), the auxiliary signal line 200 is connected between the output signal line 100 and the pixel circuit PX. The auxiliary signal line 200 is used to transmit the gate control signal on the output signal line 100 to the pixel circuit PX.
[0070] In this configuration, at least a portion of the auxiliary signal lines 200 are disposed on different layers from the output signal lines 100, and the impedance of the auxiliary signal lines 200 is less than the impedance of the output signal lines 100.
[0071] Through long-term research during the development of this invention, the inventors discovered that in the prior art, the gate driving circuit GD and the pixel circuit PX are connected via an output signal line 100. The gate driving circuit GD transmits gate control signals to the pixel circuit PX through the output signal line 100 to drive the pixel circuit PX to operate. However, on medium to large-sized display panels, the length of the output signal line 100 is relatively long. When the gate control signal is transmitted from the edge of the panel to the middle, the large transmission voltage drop causes inconsistency between the gate control signals at the edge and the middle of the panel, resulting in differences in display effects between the edge and middle areas and reducing the display uniformity of the display panel.
[0072] In this embodiment, the display panel further includes auxiliary signal lines 200. Multiple auxiliary signal lines 200 are arranged along a second direction Y and extend along a first direction X. The first direction X intersects the second direction Y and are all perpendicular to the thickness direction Z of the display panel. The auxiliary signal lines 200 are used to connect the output signal line 100 and the pixel circuit PX, transmitting gate control signals to the pixel circuit PX via the auxiliary signal lines 200. The auxiliary signal lines 200 and the output signal line 100 are disposed on different layers. For example, the auxiliary signal line 200 can be connected to the output signal line 100 through vias and also to the pixel circuit PX through vias. An insulating layer is provided between the auxiliary signal lines 200 and the output signal line 100 to isolate them.
[0073] Furthermore, since the auxiliary signal line 200 and the output signal line 100 are located on different film layers, they can be configured to have different impedances. Here, the impedance of the auxiliary signal line 200 is designed to be less than that of the output signal line 100. By using the auxiliary signal line 200 with lower impedance to transmit the gate control signal to the in-plane pixel circuit PX, the transmission voltage drop of the gate control signal can be reduced. This helps to ensure the consistency of the gate control signal between the edge area and the middle area of the display panel, thereby reducing the display difference between the edge area and the middle area of the display panel and improving display uniformity.
[0074] The technical solution provided in this embodiment of the invention connects the output signal line 100 and the pixel circuit PX through an auxiliary signal line 200 to transmit the gate control signal output by the gate drive circuit GD to the pixel circuit PX. The impedance of the auxiliary signal line 200 is less than that of the output signal line 100 to reduce the impedance of the signal line transmitting the gate control signal. This helps to reduce the transmission voltage drop of the gate control signal, ensures the consistency of the gate control signal between the edge and middle areas of the display panel, reduces the display difference between the edge and middle areas of the display panel, and improves display uniformity and display effect.
[0075] Figure 3 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 3 Based on the above embodiments, optionally, the display panel includes a display area AA and a non-display area NA disposed around at least a portion of the display area AA, the gate driving circuit GD and the output signal line 100 are located in the non-display area NA, and the pixel circuit PX is located in the display area AA; the auxiliary signal line 200 extends from the non-display area NA to the display area AA, and extends in the display area AA along the first direction X, and the multiple auxiliary signal lines 200 are arranged along the second direction Y.
[0076] The gate drive circuits GD can be multiple. For example, there are two gate drive circuits GD, namely a first gate drive circuit 1 and a second gate drive circuit 2. The output signal line 100 includes a first output signal line 101 and a second output signal line 102. The first gate drive circuit 1 transmits the first gate control signal through the first output signal line 101. The first output signal line 101 and the first auxiliary signal line 201 ( Figure 3 (As shown by the green line in the diagram) The first gate control signal on the first output signal line 101 is transmitted to the pixel circuit PX of the display area AA via the first auxiliary signal line 201. The impedance of the first auxiliary signal line 201 is less than the impedance of the first output signal line 101 to reduce the transmission voltage drop of the first gate control signal.
[0077] The second gate driving circuit 2 transmits the second gate control signal through the second output signal line 102. The second output signal line 102 and the second auxiliary signal line 202 ( Figure 3 (As shown by the blue line in the diagram) The second gate control signal on the second output signal line 102 is transmitted to the pixel circuit PX of the display area AA via the second auxiliary signal line 202. The impedance of the second auxiliary signal line 202 is less than the impedance of the second output signal line 102 to reduce the transmission voltage drop of the second gate control signal.
[0078] It should be noted that each gate drive circuit (GD) can be driven simultaneously from both the left and right sides to meet the driving requirements of medium and large-sized display panels.
[0079] Optionally, multiple auxiliary signal lines 200 can be arranged on the same layer, such as the first auxiliary signal line 201 and the second auxiliary signal line 202 being arranged on the same layer.
[0080] Optionally, the display panel also includes multiple gate control signal lines, which are arranged on different layers from the auxiliary signal lines 200. The auxiliary signal lines 200 are connected to the gate control signal lines through a wire switching hole, and the gate control signal lines are connected to the pixel circuit PX. Figure 4 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 4 The gate control signal line includes a first gate control signal line 301, one end of the first auxiliary signal line 201 is connected to the first output signal line 101 via a line switching hole, and the other end of the first auxiliary signal line 201 is connected to the first gate control signal line 301 via a line switching hole.
[0081] The display panel also includes an active layer, and the pixel circuit PX includes multiple transistors. The gate control signal line overlaps with the active layer to form the gate of the transistor, and the auxiliary signal line 200 is connected to the gate of the transistor through a switching hole. Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 5 The pixel circuit PX includes a driving transistor Q1 and a data writing transistor Q2. The data writing transistor Q2 is connected between the data line and the driving transistor Q1 and is used to transmit the data voltage Vdata on the data line to the driving transistor Q1.
[0082] Optionally, the pixel circuit PX also includes a compensation transistor Q3, which is connected between the gate and the first terminal of the driving transistor Q1, and a data write transistor Q2 is connected to the second terminal of the driving transistor Q1. The compensation transistor Q3 is used to compensate for the threshold voltage of the driving transistor Q1.
[0083] Specifically, the first gate control signal line 301 overlaps with the active layer 11 to form a data writing transistor Q2 and a compensation transistor Q3 (the compensation transistor Q3 can be a dual-gate transistor). The first auxiliary signal line 201 can transmit the first scan signal S1 on the first output signal line 101 to the first gate control signal line 301 to drive the data writing transistor Q2 and the compensation transistor Q3.
[0084] For example, the first gate control signal line 301 includes a main body 311, a first branch 312, and a second branch 313. The main body 311 extends along a first direction X, the first branch 312 extends along a second direction Y, and the second branch 313 extends in the opposite direction of the second direction Y. The main body 311 overlaps with the active layer 11 to form a data writing transistor Q2, the first branch 312 overlaps with the active layer 11 to form a compensation transistor Q3, and the second branch 313 is connected to the first auxiliary signal line 201 through a switching hole.
[0085] Optionally, the orthographic projection of the first auxiliary signal line 201 on the substrate 10 does not overlap with the orthographic projection of the first gate control signal line 301 on the substrate 10, which is beneficial to improving the flexibility of wiring. The first auxiliary signal line 201 includes a first segment 211 extending in the opposite direction of the second direction Y in the non-display area NA, and a second segment 212 extending in the first direction X from the non-display area NA to the display area AA. The first segment 211 is used to connect to the first output signal line 101, and the second segment 212 is used to connect to the first gate control signal line 301, specifically, the first scan line 301.
[0086] Of course, in other embodiments, the orthographic projection of the first auxiliary signal line 201 on the substrate 10 overlaps with the orthographic projection of at least a portion of the first gate control signal line 301 on the substrate 10, such as... Figure 6 As shown, Figure 6 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. (Reference) Figure 6 The first gate control signal line 301 includes a main body 311 and a first branch 312. The main body 311 extends along a first direction X, and the first branch 312 extends along a second direction Y. The main body 311 overlaps with the active layer 11 to form a data writing transistor Q2. The first branch 312 and / or the main body 311 overlaps with the active layer 11 to form a compensation transistor Q3 (the compensation transistor Q3 can be a dual-gate transistor). The main body 311 and / or the first branch 312 are connected to the first auxiliary signal line 201 through a switching hole. Since the first auxiliary signal line 201 is connected to the first scan signal S1 and is connected to the first gate control signal line 301, the potentials of both the first auxiliary signal line 201 and the first gate control signal line 301 are not floating. By shielding the first gate control signal line 301 with the first auxiliary signal line 201, the first auxiliary signal line 201 can act as a self-shielding device, preventing the transmitted first scan signal S1 from being interfered with and fluctuating. Furthermore, by overlapping the orthographic projection of the first auxiliary signal line 201 on the substrate 10 with the orthographic projection of at least a portion of the first gate control signal line 301 on the substrate 10, wiring space for the first auxiliary signal line 201 can be saved, thus saving layout area.
[0087] Optionally, the pixel circuit PX also includes a storage capacitor C1. The first terminal of the storage capacitor C1 is connected to the gate of the driving transistor Q1, and the second terminal of the storage capacitor C1 is connected to a fixed voltage. The gate of the driving transistor Q1 is reused as the first terminal of the storage capacitor C1.
[0088] Continue to refer to Figure 4 Based on the above embodiments, the gate control signal line further includes a second gate control signal line 302. One end of the second auxiliary signal line 202 is connected to the second output signal line 102 via a line switching hole, and the other end of the second auxiliary signal line 202 is connected to the second gate control signal line 302 via a line switching hole.
[0089] Specifically, in combination Figure 5 The second output signal line 102 is connected to the second auxiliary signal line 202. The second scan signal S2 on the second output signal line 102 is transmitted to the first initialization transistor Q4 in the pixel circuit PX via the second auxiliary signal line 202. The first initialization transistor Q4 is connected between the first initialization signal line (not shown in the figure) and the gate of the driving transistor Q1, and is used to transmit the first initialization voltage Vref1 on the first initialization signal line to the gate of the driving transistor Q1 to initialize the gate of the driving transistor Q1. The impedance of the second auxiliary signal line 202 is less than the impedance of the second output signal line 102 to reduce the transmission voltage drop of the second scan signal S2 and reduce the difference in the second scan signal S2 between the edge area and the middle area of the display panel.
[0090] In this embodiment, the orthographic projection of the second auxiliary signal line 202 on the substrate 10 covers at least a portion of the orthographic projection of the second gate control signal line 302 on the substrate 10. Since the second auxiliary signal line 202 is connected to the second gate control signal and is also connected to the second gate control signal line 302, neither the second auxiliary signal line 202 nor the second gate control signal line 302 has a floating potential. By shielding the second gate control signal line 302 with the second auxiliary signal line 202, the second auxiliary signal line 202 can act as a self-shielding element, preventing the transmitted second scan signal S2 from being interfered with and fluctuating.
[0091] Optionally, the orthogonal projection of the second auxiliary signal line 202 on the substrate 10 can completely cover the orthogonal projection of the second gate control signal line 302 on the substrate 10 to enhance the self-shielding effect.
[0092] The technical solution provided by the embodiments of the present invention achieves the self-shielding effect of the auxiliary signal line 200 by setting at least a portion of the orthogonal projection of the auxiliary signal line 200 on the substrate 10 to cover at least a portion of the orthogonal projection of the gate control signal line on the substrate 10, thereby ensuring the stability of the gate control signal transmitted thereon.
[0093] Figure 7 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present invention, specifically... Figure 4 The cross-sectional structure of the display panel shown is obtained along the cutting line BB'. Figure 8 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present invention, specifically... Figure 4 The cross-sectional structure of the display panel shown is obtained along the cutting line CC', for reference. Figure 4 , Figure 7 and Figure 8 The display panel includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially on one side of a substrate 10. A first insulating layer 20 is disposed between the first and second metal layers, a second insulating layer 30 is disposed between the second and third metal layers, and a third insulating layer 40 is disposed on the side of the third metal layer away from the substrate 10. A buffer layer 50 is disposed between the substrate 10 and the first metal layer. Output signal lines 100 (such as the first output signal line 101 and the second output signal line 102) are located on the first metal layer and / or the second metal layer. Gate control signal lines (such as the first gate control signal line 301 and the second gate control signal line 302) are located on the first metal layer. Auxiliary signal lines 200 (such as the first auxiliary signal line 201 and the second auxiliary signal line 202) are located on the third metal layer. The first auxiliary signal line 201 is connected to the first scan line 301 via a switching hole.
[0094] On the output signal line 100 side, the output signal line 100 is connected to the auxiliary signal line 200 through a switching hole to prevent antenna effects and avoid electrostatic discharge. For example, the first output signal line 101 located in the first metal layer is connected to the first auxiliary signal line 201 located in the third metal layer through a switching hole, and the second output signal line 102 located in the second metal layer is connected to the second auxiliary signal line 202 located in the third metal layer through a switching hole. Alternatively, the second output signal line 102 can be disposed on the same layer as the first output signal line 101.
[0095] Optionally, both the first and second metal layers include a molybdenum layer, and the third metal layer includes a first titanium layer, an aluminum layer, and a second titanium layer stacked together (Ti-Al-Ti). Since the impedance of Ti-Al-Ti is lower than that of molybdenum, the auxiliary signal line 200 formed through the Ti-Al-Ti layer can effectively reduce the transmission voltage drop of the gate control signal, which is beneficial to improving the consistency of the gate control signal in the edge and middle areas of the display panel.
[0096] Optionally, continue to refer to Figure 4 and Figure 5The gate control signal line also includes a third gate control signal line 303, the auxiliary signal line 200 also includes a third auxiliary signal line 203, the output signal line 100 also includes a third output signal line 103, one end of the third auxiliary signal line 203 is connected to the third output signal line 103 through a wire switching hole, and the other end of the third auxiliary signal line 203 is connected to the third gate control signal line 303 through a wire switching hole.
[0097] Specifically, the third output signal line 103 is connected to the third auxiliary signal line 203. The third scan signal S3 on the third output signal line 103 is transmitted to the second initialization transistor Q7 in the pixel circuit PX via the third auxiliary signal line 203. The second initialization transistor Q7 is connected between the second initialization signal line (not shown in the figure) and the first terminal of the light-emitting element D1, and is used to transmit the second initialization voltage Vref2 on the second initialization signal line to the first terminal of the light-emitting element D1 to initialize the first terminal of the light-emitting element D1. The impedance of the third auxiliary signal line 203 is less than the impedance of the third output signal line 103 to reduce the transmission voltage drop of the third scan signal S3, thereby reducing the difference in the third scan signal S3 between the edge area and the middle area of the display panel.
[0098] In this embodiment, the orthographic projection of the third auxiliary signal line 203 on the substrate 10 covers at least a portion of the orthographic projection of the third gate control signal line on the substrate 10. Therefore, the third auxiliary signal line 203 also has a self-shielding function, preventing the transmitted third scan signal S3 from fluctuating due to interference from external signals. For the specific working principle, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.
[0099] Optionally, the orthogonal projection of the third auxiliary signal line 203 on the substrate 10 can completely cover the orthogonal projection of the third gate control signal line on the substrate 10 to enhance the self-shielding effect.
[0100] Continue to refer to Figure 4 and Figure 5 The gate control signal line also includes a light emission control signal line 304, the auxiliary signal line 200 also includes a fourth auxiliary signal line 204, the output signal line 100 also includes a fourth output signal line 104, one end of the fourth auxiliary signal line 204 is connected to the fourth output signal line 104 through a wire switching hole, and the other end of the fourth auxiliary signal line 204 is connected to the light emission control signal line 304 through a wire switching hole.
[0101] Specifically, the display panel also includes a first power line and a second power line (not shown in the figure), and the pixel circuit PX also includes a first light-emitting control transistor Q5 and a second light-emitting control transistor Q6. The light-emitting control signal line 304 overlaps with the active layer 11 to form the first light-emitting control transistor Q5 and the second light-emitting control transistor Q6 respectively. The first light-emitting control transistor Q5 is connected between the first power line and the second terminal of the driving transistor Q1, and the second light-emitting control transistor Q6 is connected between the first terminal of the driving transistor Q1 and the first terminal of the light-emitting element D1. The second terminal of the light-emitting element D1 is connected to the second power line.
[0102] The fourth auxiliary signal line 204 is connected to the fourth output signal line 104 through a cable replacement hole. The light emission control signal EM on the fourth output signal line 104 is transmitted via the fourth auxiliary signal line 204 to the first light emission control transistor Q5 and the second light emission control transistor Q6 in the pixel circuit PX. The first light emission control transistor Q5 and the second light emission control transistor Q6 are used to respond to the light emission control signal EM to connect the path between the first power line and the second power line, so that the driving transistor Q1 drives the light emission element D1 to emit light. The first power line can be used to transmit the first power supply voltage VDD, and the second power line can be used to transmit the second power supply voltage VSS. Here, the impedance of the fourth auxiliary signal line 204 is less than the impedance of the fourth output signal line 104 to reduce the transmission voltage drop of the light emission control signal EM, thereby reducing the difference in the light emission control signal EM between the edge area and the middle area of the display panel.
[0103] In this embodiment, the orthographic projection of the fourth auxiliary signal line 204 onto the substrate 10 covers at least a portion of the orthographic projection of the light emission control signal line 304 onto the substrate 10. Therefore, the fourth auxiliary signal line 204 also has a self-shielding function, preventing the transmitted light emission control signal EM from fluctuating due to interference from external signals. For the specific working principle, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.
[0104] Of course, in other embodiments, the orthogonal projection of the fourth auxiliary signal line 204 on the substrate 10 can completely cover the orthogonal projection of the light emission control signal line 304 on the substrate 10 to enhance the self-shielding effect.
[0105] Optionally, the orthographic projection of the first auxiliary signal line 201 on the substrate 10 is located between the orthographic projection of the second auxiliary signal line 202 on the substrate 10 and the orthographic projection of the gate of the driving transistor Q1 on the substrate 10, and the orthographic projection of the fourth auxiliary signal line 204 on the substrate 10 is located between the orthographic projection of the gate of the driving transistor Q1 on the substrate 10 and the orthographic projection of the third auxiliary signal line 203 on the substrate 10, which facilitates the layout of the pixel circuit PX.
[0106] It should be understood that in this embodiment, the output signal line 100 is not directly connected to the gate control signal line with higher impedance. Instead, it is connected to the gate control signal line through the auxiliary signal line 200 with lower impedance. In other words, the direct connection between the original output signal line 100 and the gate control signal line is severed, and the output signal line 100 is connected to the auxiliary signal line 200. The gate control signal is transmitted through the auxiliary signal line 200, which is then connected to the gate control signal line through a switching hole. This eliminates the need to change the layout structure within the display area AA, simplifying the process and reducing manufacturing difficulty. For example, the first output signal line 101 located in the first metal layer is switched to the third metal layer through a switching hole to connect to the first auxiliary signal line 201 located in the third metal layer. The first auxiliary signal line 201 is then connected to the first gate control signal line 301 through a switching hole. The first gate control signal line 301 overlaps with the active layer 11 to form a corresponding transistor. Similarly, the connection methods of other output signal lines are similar to those of the first output signal line 101 and will not be described in detail.
[0107] It should be noted that in the above embodiments, each output signal line is connected to the corresponding gate drive circuit GD. Different gate control signals can be output by different groups of gate drive circuits GD, or some gate control signals can be output by the same group of gate drive circuits GD.
[0108] Optionally, along the first direction X, the length of the auxiliary signal line 200 is greater than the length of the gate control signal line.
[0109] Specifically, Figure 9 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. In conjunction with the above embodiments, the gate control signal lines connected to the same auxiliary signal line 200 between adjacent pixel circuits PX are integrated into a single structure (e.g., Figure 4 (as shown) or segmented independent structure (such as Figure 9 (As shown). In other words, the same gate control signal line within the display area AA can be a continuous signal line or multiple independent signal lines. Each independent signal line is only placed at the location where the corresponding transistor is formed; gate control signal lines are not placed at other locations where transistors are not formed. By setting the length of the auxiliary signal line 200 to be greater than the length of the gate control signal line, it is beneficial to reduce the impedance change of the auxiliary signal line 200 at the line switching connection, ensuring the uniformity of the impedance of the auxiliary signal line 200. For cases where the auxiliary signal line 200 and the gate control signal line do not overlap, it also saves wiring space for the gate control signal line and prevents the gate control signal line from interfering with other signal lines on the same layer.
[0110] Figure 10This is a top view schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 10 Based on the above embodiments, the display panel further includes a first initialization signal line 411 and a second initialization signal line 412. Both the first initialization signal line 411 and the second initialization signal line 412 extend along a first direction X and are alternately arranged along a second direction. The first initialization signal line 411 is used to provide a first initialization voltage Vref1 to the pixel circuit PX, and the second initialization signal line 412 is used to provide a second initialization voltage Vref2 to the pixel circuit PX. The first initialization signal line 411 is connected to the first initialization transistor Q4, and the second initialization signal line 412 is connected to the second initialization transistor Q7.
[0111] Optionally, the first initialization signal line 411 is disposed near the second auxiliary signal line 302, and the first initialization signal line 411 and the second auxiliary signal line 302 are disposed on different layers. For example, the first initialization signal line 411 is located in the second metal layer, and the second auxiliary signal line 302 is located in the third metal layer.
[0112] Optionally, the second initialization signal line 412 is positioned close to the third auxiliary signal line 203, and the second initialization signal line 412 is positioned on the same layer as the first initialization signal line 411.
[0113] Optionally, continue to refer to Figure 5 and Figure 10 The display panel also includes a data line 61, which extends along a second direction Y and is arranged along a first direction X. The data line 61 is connected to a data write transistor Q2 for transmitting a data voltage Vdata.
[0114] Figure 11 This is a waveform diagram of a gate control signal provided in the prior art, for reference. Figure 11 In existing technologies, due to the high impedance of the gate control signal line, the rising and falling edges of the gate control signal account for a large proportion of the signal's time, resulting in a very short effective time (the duration of the waveform's peaks or troughs). For example, for the first scan signal S1, its waveform rising edge time is 1.5884µs and falling edge time is 1.3273µs. The short effective time of the first scan signal S1 leads to a short pixel charging time, resulting in insufficient charging and affecting display brightness.
[0115] Figure 12 This is a waveform diagram of a gate control signal provided in an embodiment of the present invention, with reference to... Figure 12In this embodiment, because the impedance of the auxiliary signal line 200 is relatively small, the transmission voltage drop of the gate control signal is reduced, thus significantly reducing the proportion of the rising and falling edges of the gate control signal. Similarly, for the first scan signal S1, its waveform rising edge time is 818.09ns and falling edge time is 848.22ns. The effective time of the first scan signal S1 is relatively long, which allows for more complete pixel charging and ensures that the display brightness meets the standard.
[0116] Optionally, for other gate control signals, such as the second scan signal S2, the third scan signal S3, and the light emission control signal EM, the technical solution provided in this embodiment can also reduce the transmission voltage drop of the signal, thereby reducing the proportion of rising and falling edges and thus improving the display effect.
[0117] Figure 13 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 13 Based on the above embodiments, the gate control signal line can be omitted, and the gate of the transistor can be formed by the overlap of the auxiliary signal line 200 and the active layer 11. For example, the first auxiliary signal line 201 overlaps with the active layer 11 to form the data writing transistor Q2 and the compensation transistor Q3, the second auxiliary signal line 202 overlaps with the active layer 11 to form the first initialization transistor Q4, the third auxiliary signal line 203 overlaps with the active layer to form the second initialization transistor Q7, and the fourth auxiliary signal line 204 overlaps with the active layer 11 to form the first light-emitting control transistor Q5 and the second light-emitting control transistor Q6. The auxiliary signal line 200 is connected to the gate of each transistor. By multiplexing the auxiliary signal line 200 as the gate control signal line, the transmission voltage drop of the gate control signal can be reduced, the number of signal lines can be reduced, and the layout can be optimized.
[0118] Optionally, such as Figure 10 and Figure 13 As shown, the display panel also has redundant vias 70 on the output signal line side, which can be used to balance the static electricity accumulation of the display panel, prevent electrostatic discharge, and improve the protection of lines and devices.
[0119] Optionally, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device also possesses the beneficial effects described in any of the above embodiments. The display panel can be a flexible display panel or a rigid display panel. Figure 14This is a schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 300 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. The present invention does not impose any special limitations on these.
[0120] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0121] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A display panel, characterized in that, include: A substrate on which multiple pixel circuits are arranged in an array; A gate driving circuit and multiple output signal lines are provided, wherein the gate driving circuit is connected to the corresponding output signal lines, and the output signal lines are used to output the gate control signal generated by the gate driving circuit. Multiple auxiliary signal lines are connected between the output signal lines and the pixel circuit. The auxiliary signal lines are used to transmit the gate control signal on the output signal lines to the pixel circuit. Wherein, at least a portion of the auxiliary signal lines are disposed on a different layer from the output signal lines, and the impedance of the auxiliary signal lines is less than the impedance of the output signal lines; The display panel includes a display area and a non-display area disposed around at least a portion of the display area, the gate driving circuit and the output signal line are located in the non-display area, and the pixel circuit is located in the display area; The auxiliary signal lines extend from the non-display area to the display area, and extend along a first direction in the display area; the plurality of auxiliary signal lines are arranged along a second direction; wherein the first direction intersects the second direction. The display panel also includes an active layer; The pixel circuit includes a first initialization transistor; The display panel further includes a first initialization signal line extending along the first direction, the active layer includes a first portion extending along the first direction, the first portion is connected to the first initialization transistor in a plurality of pixel circuits arranged along the first direction, and the first portion is also connected to the first initialization signal line; the first initialization signal line and the first portion are disposed in different layers. And / or, The pixel circuit includes a second initialization transistor; The display panel further includes a second initialization signal line extending along the first direction, and the active layer further includes a second portion extending along the first direction. The second portion is connected to the second initialization transistors in a plurality of pixel circuits arranged along the first direction. The second portion is also connected to the second initialization signal line. The second initialization signal line and the second portion are disposed on different layers. The display panel also includes multiple gate control signal lines, which are disposed on different layers from the auxiliary signal lines. The auxiliary signal lines are connected to the gate control signal lines through a switching hole, and the gate control signal lines are connected to the pixel circuit. The gate control signal line includes a first gate control signal line, the auxiliary signal line includes a first auxiliary signal line, the output signal line includes a first output signal line, one end of the first auxiliary signal line is connected to the first output signal line through the switching hole, and the other end of the first auxiliary signal line is connected to the first gate control signal line through the switching hole. The pixel circuit includes a driving transistor and a data writing transistor. The first gate control signal line overlaps with the active layer to form the data writing transistor. The data writing transistor is connected between the data line and the second electrode of the driving transistor. The first gate control signal line has a segmented independent structure; The pixel circuit further includes a compensation transistor, and the first gate control signal line overlaps with the active layer to form the compensation transistor. The compensation transistor is connected between the gate of the driving transistor and the first electrode. In the same first gate control signal line, the first gate control signal lines corresponding to the data write transistor and the compensation transistor in the same pixel circuit are arranged in segments continuously; Within the same first gate control signal line, the first gate control signal lines corresponding to adjacent pixel circuits along the first direction are segmented and separated.
2. The display panel according to claim 1, characterized in that, The multiple auxiliary signal lines are arranged on the same layer.
3. The display panel according to claim 1, characterized in that, At least a portion of the auxiliary signal line's orthogonal projection onto the substrate overlaps at least a portion of the gate control signal line's orthogonal projection onto the substrate.
4. The display panel according to claim 1, characterized in that, Along the first direction, the length of the auxiliary signal line is greater than the length of the gate control signal line.
5. The display panel according to claim 1, characterized in that, The orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the first portion on the substrate overlap; And / or, the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the second portion on the substrate overlap.
6. The display panel according to claim 1, characterized in that, Multiple gate control signal lines are arranged on the same layer.
7. The display panel according to claim 1, characterized in that, The auxiliary signal line is connected to the output signal line through the switching hole.
8. The display panel according to claim 1, characterized in that, The pixel circuit includes multiple transistors, the gate control signal line overlaps with the active layer to form the gate of the transistor, and the auxiliary signal line is connected to the gate of the transistor through the switching hole.
9. The display panel according to claim 1, characterized in that, Between adjacent pixel circuits, the gate control signal line connected to the same auxiliary signal line has a segmented independent structure.
10. The display panel according to claim 1, characterized in that, The display panel includes a first metal layer, a second metal layer, and a third metal layer that are stacked sequentially on one side of the substrate. The output signal line is located in the first metal layer and / or the second metal layer, the gate control signal line is located in the first metal layer, and the auxiliary signal line is located in the third metal layer.
11. The display panel according to claim 10, characterized in that, Both the first metal layer and the second metal layer include a molybdenum layer, and the third metal layer includes a first titanium layer, an aluminum layer, and a second titanium layer stacked together.
12. The display panel according to claim 1, characterized in that, The pixel circuit also includes a storage capacitor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to a fixed voltage.
13. The display panel according to claim 12, characterized in that, The gate of the driving transistor is reused as the first terminal of the storage capacitor.
14. The display panel according to claim 1, characterized in that, The orthographic projection of the first auxiliary signal line on the substrate does not overlap with the orthographic projection of the first gate control signal line on the substrate.
15. The display panel according to claim 1, characterized in that, The first gate control signal line includes a main body, a first branch, and a second branch. The main body extends along a first direction, the first branch extends along a second direction, and the second branch extends in the opposite direction to the second direction. The main body overlaps with the active layer to form the data write transistor, and the first branch overlaps with the active layer to form the compensation transistor. The second branch is connected to the first auxiliary signal line through the switching hole.
16. The display panel according to claim 1, characterized in that, The orthographic projection of the first auxiliary signal line on the substrate covers at least a portion of the orthographic projection of the first gate control signal line on the substrate.
17. The display panel according to claim 1, characterized in that, The first gate control signal line includes a main body and a first branch. The main body extends along a first direction, and the first branch extends along a second direction. The main body overlaps with the active layer to form the data write transistor. The first branch and / or the main body overlaps with the active layer to form the compensation transistor. The main body and / or the first branch are connected to the first auxiliary signal line through the switching hole.
18. The display panel according to claim 1, characterized in that, The gate control signal line further includes a second gate control signal line, the auxiliary signal line further includes a second auxiliary signal line, and the output signal line further includes a second output signal line. One end of the second auxiliary signal line is connected to the second output signal line through the switching hole, and the other end of the second auxiliary signal line is connected to the second gate control signal line through the switching hole.
19. The display panel according to claim 18, characterized in that, The orthogonal projection of the second auxiliary signal line onto the substrate covers at least a portion of the orthogonal projection of the second gate control signal line onto the substrate.
20. The display panel according to claim 18, characterized in that, The first initialization signal line and the second auxiliary signal line are configured on different layers; The second gate control signal line overlaps with the active layer to form the first initialization transistor, and the first initialization transistor is connected between the first initialization signal line and the gate of the driving transistor.
21. The display panel according to claim 18, characterized in that, The gate control signal line further includes a third gate control signal line, the auxiliary signal line further includes a third auxiliary signal line, the output signal line further includes a third output signal line, one end of the third auxiliary signal line is connected to the third output signal line through the line switching hole, and the other end of the third auxiliary signal line is connected to the third gate control signal line through the line switching hole. The orthogonal projection of the third auxiliary signal line onto the substrate covers at least a portion of the orthogonal projection of the third gate control signal line onto the substrate.
22. The display panel according to claim 21, characterized in that, The second initialization signal line is configured on the same layer as the first initialization signal line; The third gate control signal line overlaps with the active layer to form the second initialization transistor, and the second initialization transistor is connected between the second initialization signal line and the light-emitting element.
23. The display panel according to claim 21, characterized in that, The gate control signal line also includes a light emission control signal line, the auxiliary signal line also includes a fourth auxiliary signal line, the output signal line also includes a fourth output signal line, one end of the fourth auxiliary signal line is connected to the fourth output signal line through the line switching hole, and the other end of the fourth auxiliary signal line is connected to the light emission control signal line through the line switching hole. The orthogonal projection of the fourth auxiliary signal line onto the substrate covers at least a portion of the orthogonal projection of the light-emitting control signal line onto the substrate.
24. The display panel according to claim 22, characterized in that, The display panel further includes a first power line and a second power line. The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The light-emitting control signal line overlaps with the active layer to form the first light-emitting control transistor and the second light-emitting control transistor, respectively. The first light-emitting control transistor is connected between the first power line and the second electrode of the driving transistor. The second light-emitting control transistor is connected between the first electrode of the driving transistor and the first electrode of the light-emitting element. The second electrode of the light-emitting element is connected to the second power line.
25. The display panel according to claim 23, characterized in that, The light emission control signal line has a segmented and independent structure.
26. The display panel according to claim 24, characterized in that, In the same light emission control signal line, the light emission control signal lines corresponding to the first light emission control transistor and the second light emission control transistor in the same pixel circuit are segmented and separated; and / or, In the same light emission control signal line, the light emission control signal lines corresponding to adjacent pixel circuits along the first direction are segmented and separated.
27. The display panel according to claim 23, characterized in that, The orthographic projection of the first auxiliary signal line on the substrate is located between the orthographic projection of the second auxiliary signal line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the fourth auxiliary signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the third auxiliary signal line on the substrate.
28. The display panel according to claim 1, characterized in that, The display panel further includes an active layer, the pixel circuit includes a plurality of transistors, and the auxiliary signal line overlaps with the active layer to form the gate of the transistor.
29. The display panel according to claim 28, characterized in that, The auxiliary signal line is connected to the gate of the transistor.
30. The display panel according to claim 1, characterized in that, The display panel also has redundant vias on one side of the output signal line, which are used to balance the static electricity accumulation of the display panel.
31. The display panel according to claim 1, characterized in that, The auxiliary signal line includes a first segment located in the non-display area and a second segment located at least partially in the display area. The first segment extends in the non-display area in the opposite direction to the second direction, and the second segment extends in the first direction from the non-display area to the display area. The first segment is used to connect to the output signal line, and the second segment is used to connect to the gate control signal line, wherein the gate control signal line is used to transmit the gate control signal.
32. The display panel according to claim 18, characterized in that, The second gate control signal line has a segmented independent structure.
33. A display device, characterized in that, Includes the display panel as described in any one of claims 1-32.