Dual-chip oam board card module, accelerator module and accelerated computing server

Abstract

The present disclosure relates to the field of artificial intelligence computing hardware, in particular to a double-chip OAM board card module, an accelerator module and an accelerated computing server, the double-chip OAM board card module comprising: an OAM substrate; two acceleration chips arranged on the OAM substrate along a first direction; and two optical engine modules arranged on the OAM substrate along a second direction, and the two optical engine modules are respectively located on two sides of the two acceleration chips, and the second direction intersects the first direction. The present disclosure helps to simplify the wiring of the high-speed electrical interconnection link from the high-speed input / output interface of the acceleration chip to the optical engine module in the OAM substrate, and helps to solve the problem of signal integrity of the physical link from the high-speed input / output interface to the optical engine module, thereby helping to improve the data transmission speed of the acceleration chip, and helping to break through the computing power bottleneck of the accelerated computing server.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence computing hardware, and in particular to a dual-chip OAM board module, an accelerator module, and an accelerated computing server. Background Technology

[0002] OAM (Open Accelerator Module) is an open standard specification for accelerator modules developed by the OCP (Open Compute Project) organization. Through standardized physical dimensions, electrical interfaces, and thermal design, it enables accelerator chips manufactured by different companies, such as AI (Artificial Intelligence) chips, to be deployed in standardized servers.

[0003] For example, in computing-intensive accelerated computing servers such as artificial intelligence servers, the speed of data processing is crucial. Equally important is the speed of data transmission between chips. In fact, the speed of data transmission between chips is becoming, or has become, a bottleneck affecting or even restricting the ability of accelerated computing servers to achieve higher computing power. Summary of the Invention

[0004] In view of this, this disclosure provides a dual-chip OAM board module, an accelerator module, and an accelerated computing server to help improve the data transmission speed of the accelerated chip, thereby helping to overcome the computing power bottleneck of the accelerated computing server.

[0005] According to one aspect of the embodiments of this disclosure, a dual-chip OAM board module is provided, comprising:

[0006] OAM substrate;

[0007] An acceleration chip, wherein there are two acceleration chips, and the two acceleration chips are arranged along a first direction on the OAM substrate;

[0008] The light engine module comprises two light engine modules, which are arranged along a second direction on the OAM substrate and are respectively located on both sides of the two acceleration chips. The second direction intersects with the first direction.

[0009] In one possible implementation, each of the two optical engine modules is coupled to the two acceleration chips via a high-speed electrical interconnect link in the OAM substrate.

[0010] In one possible implementation, the two light engine modules include a first light engine module and a second light engine module;

[0011] The high-speed input / output interface of the two acceleration chips, the one closer to the first optical engine module, is coupled to the first optical engine module.

[0012] The high-speed input / output interface of the two acceleration chips, the one closer to the second optical engine module, is coupled to the second optical engine module.

[0013] In one possible implementation, the two acceleration chips are arranged edge-aligned on the OAM substrate.

[0014] In one possible implementation, the two light engine modules are located in the extension direction of the spacer region between the two acceleration chips.

[0015] In one possible implementation, the fiber optic outlets of the two optical engine modules are oriented in opposite directions.

[0016] In one possible implementation, the fiber optic outlets of the two optical engine modules face the same direction.

[0017] According to another aspect of the embodiments of this disclosure, an accelerator module is provided, comprising:

[0018] Universal substrate;

[0019] At least one dual-chip OAM board module as described in any of the preceding claims, wherein the dual-chip OAM board module is plugged into the universal substrate.

[0020] In one possible implementation, the space occupied by the OAM substrate on the general substrate is the same as the space occupied by two adjacent single-accelerator chip OAM substrates.

[0021] In one possible implementation, the position of the connector on the general-purpose substrate for inserting the OAM substrate is the same as the position of the connector for inserting two adjacent single-acceleration chip OAM substrates.

[0022] In one possible implementation, the size of the OAM substrate is the same as the total size of two adjacent single-accelerator chip OAM substrates and their gap, and the area on the OAM substrate corresponding to the gap is used for device layout and / or wiring.

[0023] In one possible implementation, all OAM board modules in the accelerator module are the dual-chip OAM board modules; or...

[0024] The accelerator module also includes at least one single-accelerator chip OAM board module.

[0025] According to another aspect of the embodiments of this disclosure, an accelerated computing server is provided, including a dual-chip OAM board module as described in any of the preceding claims.

[0026] As can be seen from the above scheme, in the dual-chip OAM board module, accelerator module, and accelerated computing server disclosed herein, two acceleration chips are simultaneously arranged on one OAM substrate. Thus, the dual-chip OAM board module of this disclosure is equivalent to two single-acceleration chip OAM board modules in related technologies, and can realize the functions of two single-acceleration chip OAM board modules in related technologies. At the same time, the dual-chip OAM board module of this disclosure arranges two optical engine modules, which is equivalent to a single-acceleration chip OAM board module in related technologies arranging one optical engine module. Furthermore, in the dual-chip OAM board module of this disclosure, the two optical engine modules are located on both sides of the acceleration chip, which is equivalent to a single-acceleration chip OAM board module in related technologies arranging two optical engine modules. Therefore, the dual-chip OAM board module disclosed herein combines the advantages of related technologies: from the perspective of one of the accelerator chips, optical engine modules are arranged on both its left and right sides. This allows the high-speed input / output interfaces on the left and right sides to connect to the optical engine modules respectively, greatly reducing the complexity of wiring in the OAM substrate and thus lowering the difficulty of OAM substrate wiring. From the perspective of one of the optical engine modules, the high-speed input / output interfaces of both accelerator chips are close to the optical engine module, so all interface pins connecting the optical engine module to the accelerator chips can be fully utilized to maximize the capabilities of the optical engine module. Therefore, overall, the cost-effectiveness of the dual-chip OAM board module disclosed herein far exceeds that of the combination of two single-accelerator chip OAM board modules in related technologies. Thus, the dual-chip OAM board module, accelerator module, and accelerated computing server disclosed herein help simplify the wiring of the high-speed electrical interconnect links from the high-speed input / output interfaces of the accelerator chips to the optical engine modules in the OAM substrate, and help solve the signal integrity problem of the physical links from the high-speed input / output interfaces to the optical engine modules, thereby helping to improve the data transmission speed of the accelerator chips and helping to overcome the computing power bottleneck of the accelerated computing server. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the layout structure of an OAM board module in related technologies to realize the southbound connection function;

[0028] Figure 2 This is a schematic diagram of the layout structure of another OAM board module in related technologies to realize the southbound connection function;

[0029] Figure 3 This is a top view schematic diagram of the layout structure of a dual-chip OAM board module according to an illustrative embodiment;

[0030] Figure 4 This is a schematic diagram of the split structure of a board-to-board sandwich connector according to an illustrative embodiment;

[0031] Figure 5 This is a schematic diagram showing a comparison between an OAM substrate and two single-accelerator chip OAM substrates in an embodiment of the present disclosure, according to an illustrative embodiment.

[0032] Figure 6A This is a schematic diagram of the layout structure in which a dual-chip OAM board module and six single-acceleration chip OAM board modules of this disclosure are arranged simultaneously on a general-purpose substrate.

[0033] Figure 6B This is a schematic diagram of the layout structure in which two dual-chip OAM board modules and four single-acceleration chip OAM board modules of this disclosure are arranged on a general-purpose substrate at the same time.

[0034] Figure 6C This is a schematic diagram of the layout structure in which three dual-chip OAM board modules and two single-acceleration chip OAM board modules of this disclosure are arranged on a general-purpose substrate at the same time.

[0035] Figure 6D This is a schematic diagram of the layout structure of four dual-chip OAM board modules according to the present disclosure arranged simultaneously on a general-purpose substrate.

[0036] In the attached diagram, the component names represented by each number are as follows:

[0037] 11. OAM substrate,

[0038] 12. Accelerator chip,

[0039] 13. Light Engine Module

[0040] 41. Mezzanine connector socket,

[0041] 42. Pin array,

[0042] 51. Dual-acceleration chip OAM substrate,

[0043] 52. Single-accelerator chip OAM substrate,

[0044] 61. Dual-chip OAM board module,

[0045] 62. Single-accelerator chip OAM board module,

[0046] 63. Universal substrate. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0049] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0050] Accelerated computing servers based on the OAM specification, such as artificial intelligence servers, typically consist of several OAM cards (usually eight) plugged into a Universal Baseboard (UBB). The UBB is connected to the motherboard containing components such as the CPU, memory, and network interface card (NIC) via PCIe connectors and / or cables. Therefore, for the acceleration chips on the OAM cards to work collaboratively with other acceleration chips, data exchange requires passing through multiple nodes, including the OAM cards, the UBB, the PCIe connectors, and even the NIC and CPU. If data exchange is required between acceleration chips located on two separate acceleration servers within a server cluster, it may even need to pass through routing devices such as gateways within the server cluster, causing significant latency in data transmission and creating a bottleneck that severely impacts the computing power of the accelerated computing servers and server clusters.

[0051] To address this issue, a southbound connectivity scheme has been proposed in related technologies. This scheme bypasses the aforementioned path dependency by networking the individual acceleration chips in the accelerated computing server independently using devices such as PCIe modules and switches. This eliminates the need for data exchange between acceleration chips via links on the motherboard side and bypasses gateways and other routing devices between accelerated computing servers, thus improving data transmission efficiency to some extent. However, because this data exchange scheme essentially involves the transmission of electrical signals, it suffers from signal attenuation, electromagnetic interference, and significant bandwidth limitations. Therefore, there is still room for further improvement in the data transmission efficiency between acceleration chips.

[0052] In response to problems such as signal attenuation, electromagnetic interference, and bandwidth limitations during data transmission, optical signals have a natural advantage over electrical signals. Therefore, related technologies are attempting to introduce optical modules to accelerate southbound connections between chips. However, the solutions to these technologies also have problems that need to be overcome.

[0053] Figure 1 This is a schematic diagram of the layout structure of an OAM board module for implementing southbound connectivity in related technologies, such as... Figure 1 As shown, the OAM board module includes an OAM substrate 11 and an acceleration chip 12 located on the OAM substrate 11. A light engine module 13 is mounted on one side of the acceleration chip 12 on the OAM substrate 11. The light engine module 13 is coupled to the high-speed input / output interface of the acceleration chip 12 through wiring (not shown in the figure) in the OAM substrate 11, so that the data of the acceleration chip 12 can be transmitted and received through the light engine module 13. Another acceleration chip 12 on an OAM substrate 11 that also contains a light engine module 13 (which may be located in the same accelerated computing server as the OAM substrate 11 or in another accelerated computing server) can realize data interaction with the acceleration chip 12 on the OAM substrate 11. However, Figure 1 In this scheme, because the light engine module 13 is arranged on one side of the acceleration chip 12 (e.g. Figure 1 As shown on the left side), the high-speed input / output interfaces of the accelerator chip 12 are not located on one side of the accelerator chip 12. The pads corresponding to the high-speed input / output interfaces are usually distributed on both sides of the pad area. This results in different physical distances between different high-speed input / output interfaces and the optical engine module 13, leading to a larger insertion loss. In order to ensure the consistency of signal integrity of the physical links from different high-speed input / output interfaces in the OAM substrate 11 to the optical engine module 13, it is necessary to consider that the length of each physical link is basically consistent. This leads to a sharp increase in the wiring complexity in the OAM substrate 11. Furthermore, there are different signal interferences between different physical links. Therefore, even if the length of each physical link is basically consistent, it is difficult to guarantee the consistency of signal integrity of each physical link. Continuous optimization and improvement are required, resulting in a sharp increase in development and production difficulty.

[0054] To overcome this problem, another layout structure has been proposed in related technologies. Figure 2 This is a schematic diagram of the layout structure of another OAM board module in related technologies for implementing southbound connectivity. (Example) Figure 2 As shown, in this layout structure, a light engine module 13 is arranged on each side of the acceleration chip 12, so that, Figure 2The left-side optical engine module 13 shown can be responsible for connecting only the high-speed input / output interface on the left side of the acceleration chip 12, and the right-side optical engine module 13 can be responsible for connecting only the high-speed input / output interface on the right side of the acceleration chip 12. This greatly reduces the complexity of the wiring in the OAM substrate 11, thereby reducing the difficulty of wiring the OAM substrate 11. Furthermore, based on this design, since the high-speed input / output interfaces on the left and right sides of the acceleration chip 12 are led out and connected through different optical engine modules 13, the relevant southbound network topology can be designed according to different computing task requirements. This allows the high-speed input / output interfaces on the left and right sides of the acceleration chip 12 to be connected to two other different acceleration chips 12, or they can all be connected to the same acceleration chip 12, thereby improving configuration flexibility and adapting to more computing needs. However, this improvement is based on adding an extra optical engine module 13. Compared to using only one optical engine module 13, this results in a waste of the capacity of a single optical engine module 13. Furthermore, because the optical engine module 13 itself is expensive, it significantly increases the cost of the accelerated computing server.

[0055] In view of this, the present disclosure provides a dual-chip OAM board module, an accelerator module, and an accelerated computing server to help improve the data transmission speed of the acceleration chip, thereby helping to overcome the computing power bottleneck of the accelerated computing server. Furthermore, while being compatible with conventional OAM specifications, it simultaneously achieves full utilization of the optical engine module's capabilities and reduces the wiring difficulty in the OAM substrate, thereby suppressing the cost increase of the accelerated computing server and improving its cost-effectiveness.

[0056] Figure 3 This is a top view schematic diagram illustrating the layout structure of a dual-chip OAM board module according to an illustrative embodiment. For example... Figure 3 As shown in the illustrative embodiment, the dual-chip OAM board module of this disclosure mainly includes an OAM substrate 11, an accelerator chip 12, and a light engine module 13. There are two accelerator chips 12, arranged along a first direction on the OAM substrate 11. There are also two light engine modules 13, arranged along a second direction on the OAM substrate 11, with each module located on either side of one of the two accelerator chips 12. The second direction intersects the first direction.

[0057] Combination Figure 3As shown, the second direction intersects with the first direction to avoid placing the two light engine modules 13 on opposite sides of the two acceleration chips 12 along the y-axis. If the two light engine modules 13 were placed on opposite sides of the two acceleration chips 12 along the y-axis, then for any one acceleration chip 12, it would be isolated from one of the light engine modules 13 by the other acceleration chip 12, and for any one of the light engine modules 13, it would be isolated from one of the acceleration chips 12 by the other acceleration chip 12. This is consistent with... Figure 1 The layout of the OAM board modules shown is similar, making it difficult to solve. Figure 1 The OAM board module faces several problems, making it even more difficult to connect a light engine module 13 to two accelerator chips 12 simultaneously. By setting the second direction to intersect the first direction, it is possible to arrange the two light engine modules 13 on both sides of the two accelerator chips 12 in directions other than the y-axis (e.g., the x-axis direction). This helps to eliminate the situation where either accelerator chip 12 is isolated from the light engine module 13 by the other accelerator chip 12, and also helps to eliminate the situation where either light engine module 13 is isolated from the other accelerator chip 12, thereby helping to reduce the complexity and difficulty of wiring in the OAM board.

[0058] In a preferred embodiment, the second direction is perpendicular to the first direction, wherein the first direction is, for example... Figure 3 The y-axis direction shown, the second direction, for example Figure 3 The x-axis direction is shown in the diagram. This method allows for maximizing the proximity of any one optical engine module 13 to both acceleration chips 12 simultaneously, significantly reducing the complexity and difficulty of wiring in the OAM substrate.

[0059] from Figure 3 As can be seen, the dual-chip OAM board module of this disclosure arranges two acceleration chips 12 simultaneously in one OAM substrate 11. Therefore, the dual-chip OAM board module of this disclosure is equivalent to two OAM board modules in the related technology (for the sake of description, the OAM board module in the related technology can be called a single acceleration chip OAM board module), and can realize the functions of two single acceleration chip OAM board modules in the related technology. At the same time, the dual-chip OAM board module of this disclosure arranges two optical engine modules 13, which is equivalent to one optical engine module 13 arranged in one single acceleration chip OAM board module in the related technology. Figure 1The scheme is as follows: In the dual-chip OAM board module of this disclosure embodiment, the two optical engine modules 13 are respectively located on both sides of the acceleration chip 12, which is equivalent to a single acceleration chip OAM board module in the related art arranging two optical engine modules 13. Figure 2 Therefore, the dual-chip OAM board module of this disclosure combines the advantages of related technologies: from the perspective of one of the acceleration chips 12, optical engine modules 13 are arranged on both its left and right sides. In this way, the high-speed input / output interfaces on the left and right sides can be connected to the optical engine modules 13 on the left and right sides respectively. This can greatly reduce the complexity of the wiring in the OAM substrate 11, thereby reducing the difficulty of wiring in the OAM substrate 11; from the perspective of one of the optical engine modules 13, the high-speed input / output interfaces of the two acceleration chips 12 are close to the optical engine module 13, so all the interface pins of the optical engine module 13 connecting to the acceleration chip 12 can be fully utilized to maximize the capabilities of the optical engine module 13. Therefore, overall, the cost-effectiveness of the dual-chip OAM board module of this disclosure is far superior to that of related technologies (…). Figure 1 , Figure 2 The combination of two single-acceleration chip OAM board modules.

[0060] In the illustrative embodiment, each of the two optical engine modules 13 is coupled to the two accelerator chips 12 via a high-speed electrical interconnect link (not shown) in the OAM substrate 11. Specifically, since the optical engine module 13 is added to enable the external data transmission and interaction of the accelerator chip 12, the optical engine module 13 is connected to the high-speed input / output interface of the accelerator chip 12. In this way, the data sent and received by the accelerator chip 12 through the high-speed input / output interface can be transmitted through the optical signal link established by the optical engine module 13. Based on this, the OAM substrate 11 needs to be specifically designed to implement the high-speed electrical interconnect link between the high-speed input / output interface of the accelerator chip 12 and the optical engine module 13.

[0061] It should be noted that because the high-speed electrical interconnect links in the OAM substrate 11 are electrical signal links, they inherently have signal integrity issues. To maximize the integrity of the signals transmitted in the high-speed electrical interconnect links, the optimal solution is to keep the length of the high-speed electrical interconnect links (i.e., the length of the physical traces) as short as possible. Based on this, in a preferred embodiment, where normal wiring design can be implemented in the OAM substrate 11, the optical engine module 13 and the acceleration chip 12 are placed as close as possible. Therefore, in the illustrative embodiment, the optical engine module 13 and the acceleration chip 12 are adjacent to each other.

[0062] In an illustrative embodiment, the two light engine modules 13 include a first light engine module and a second light engine module, wherein, as shown... Figure 3 As shown, the first optical engine module is, for example, the optical engine module 13 on the left, and the second optical engine module is, for example, the optical engine module 13 on the right. The high-speed input / output interface of the two accelerator chips 12, the one closer to the first optical engine module, is coupled to the first optical engine module. The high-speed input / output interface of the two accelerator chips 12, the one closer to the second optical engine module, is coupled to the second optical engine module. This facilitates short-distance connections between the high-speed input / output interfaces of each of the two accelerator chips 12 and the adjacent optical engine module 13. That is, the high-speed input / output interface on the left side of each of the two accelerator chips 12 is connected to the adjacent left-side optical engine module 13 (the first optical engine module), and the high-speed input / output interface on the right side of each of the two accelerator chips 12 is connected to the adjacent right-side optical engine module 13 (the second optical engine module), rather than the high-speed input / output interface on the right side of the accelerator chip 12 being connected to the left-side optical engine module 13, or vice versa.

[0063] In the illustrative embodiment, two accelerator chips 12 are arranged edge-aligned on the OAM substrate 11, i.e. Figure 3 As shown, the left edges of the two accelerator chips 12 are aligned with each other, and the right edges of the two accelerator chips 12 are aligned with each other. This makes the positions of the two optical engine modules 13 mirror symmetrical with respect to the accelerator chips 12 (the two optical engine modules 13 are mirror symmetrical with respect to the common midline along the y-axis of the two accelerator chips 12), which facilitates the symmetry of the wiring structure of the high-speed electrical interconnect links between the accelerator chips 12 and the two left and right optical engine modules 13, thereby reducing the complexity and difficulty of wiring the high-speed electrical interconnect links.

[0064] In the illustrative embodiment, the two light engine modules 13 are located along the extension direction of the spaced region between the two acceleration chips 12. More specifically, as Figure 3 As shown, the two light engine modules 13 are located along the extension direction of the centerline of the gap region between the two acceleration chips 12. The centerline of the gap region between the two acceleration chips 12 refers to a straight line equidistant from the opposite edges of the two acceleration chips 12, i.e., as shown... Figure 3 As shown, the center line ( Figure 3 The distance between the center line (the dashed line in the diagram) and the lower edge of the upper acceleration chip 12 is equal to the distance between the center line and the upper edge of the lower acceleration chip 12. This layout structure between the light engine module 13 and the acceleration chip 12 ensures that the distance between any one light engine module 13 and the two acceleration chips 12 is the same, and that the positions of the two acceleration chips 12 relative to any one light engine module 13 are mirror symmetrical (i.e., the two acceleration chips 12 are mirror symmetrical). Figure 3The dashed lines in the diagram are mirror-symmetrical, which facilitates the symmetry of the wiring structure for the high-speed electrical interconnect links between the engine module and the two accelerator chips 12, thereby reducing the complexity and difficulty of wiring the high-speed electrical interconnect links. Furthermore, the positions of the two accelerator chips 12 relative to any one of the optical engine modules 13 do not necessarily have mirror symmetry. In this embodiment, the selection of the positions of the two accelerator chips 12 relative to the optical engine module 13 prioritizes satisfying the wiring requirements of the high-speed signal traces between the accelerator chips 12 and the optical engine module 13 in the OAM substrate 11. In practical applications, the positions of the two accelerator chips 12 relative to the optical engine module 13 only need to ensure that the wiring of the high-speed signal traces between the accelerator chips 12 and the optical engine module 13 in the OAM substrate 11 meets the design requirements for the data transmission rate and reliability between the accelerator chips 12 and the optical engine module 13.

[0065] From the above description of the layout structure of the two acceleration chips 12 and the two light engine modules 13 in the embodiments of this disclosure, it can be seen that in the embodiments of this disclosure, in the first direction (e.g. Figure 3 The y-axis direction shown can be referred to as the width direction of the OAM substrate 11 or the dual-chip OAM board module, and the second direction (e.g.) Figure 3 The symmetrical layout of the two accelerator chips 12 and the two optical engine modules 13 along the x-axis direction (which can be referred to as the length direction of the OAM substrate 11 or the dual-chip OAM board module) helps to simplify the wiring of the high-speed electrical interconnect link from the high-speed input / output interface of the accelerator chip 12 to the optical engine module 13 in the OAM substrate 11, and also helps to solve the signal integrity problem of the physical link from the high-speed input / output interface to the optical engine module 13, thus ensuring the practicality of the dual-chip OAM board module of this disclosure embodiment.

[0066] In the illustrative embodiment, the fiber optic outlets of the two optical engine modules 13 face opposite directions. For example, Figure 3 As shown, the fiber optic outlet of the first optical engine module (optical engine module 13 on the left) faces the positive direction of the first direction (e.g., Figure 3 The optical fiber outlet of the second optical engine module (optical engine module 13 on the right) faces the opposite direction of the first direction (e.g., the positive y-axis direction shown in the diagram). Figure 3 The y-axis shown is in the opposite direction (as shown), or conversely, the fiber optic outlet of the first optical engine module (optical engine module 13 on the left) faces the opposite direction of the first direction (e.g., the opposite direction of the first direction). Figure 3 (As shown, the y-axis is in the opposite direction), the fiber optic outlet of the second optical engine module (optical engine module 13 on the right) faces the positive direction of the first direction (e.g., the y-axis is in the opposite direction). Figure 3(The positive y-axis direction is shown in the diagram). In the illustrative embodiment, the fiber optic outlets of the two optical engine modules 13 can be parallel to the surface of the OAM substrate 11 or at a certain preset angle to the surface of the OAM substrate 11. When the fiber optic outlets of the two optical engine modules 13 are at a certain preset angle to the surface of the OAM substrate 11, the projections of the fiber optic outlets of the two optical engine modules 13 onto the surface of the OAM substrate 11 can point in opposite directions. This facilitates the organization of fiber optic cabling inside the AI ​​server chassis where the dual-chip OAM board module is located, improving the tidiness of the AI ​​server and reducing the difficulty of organization.

[0067] The fiber optic outlets of the two optical engine modules 13 face opposite directions, a design based on a layout within the AI ​​server chassis. In practical applications, this design, where the fiber optic outlets of the two optical engine modules 13 face opposite directions, is not unique. In the illustrative embodiment, if the layout of the AI ​​server chassis allows, the fiber optic outlets of the two optical engine modules 13 can also face the same direction. Furthermore, provided the internal space and layout of the AI ​​server chassis permit, the fiber optic outlets of the two optical engine modules 13 can face any direction, or be perpendicular to the surface of the OAM substrate 11, parallel to the surface of the OAM substrate 11, or at an angle to the surface of the OAM substrate 11.

[0068] In an illustrative embodiment, the optical engine module 13 can be installed on the OAM substrate 11 in a pluggable manner. Based on this, the dual-chip OAM board module of this disclosure embodiment may further include two board-to-board mezzanine connectors, wherein the two optical engine modules 13 are respectively plugged into the OAM substrate 11 through their respective matching board-to-board mezzanine connectors.

[0069] Figure 4 This is a schematic diagram of a split structure of a board-to-board interlayer connector according to an illustrative embodiment, as shown below. Figure 4 As shown in the illustrative embodiment, the board-to-board mezzanine connector includes a mezzanine connector socket 41 and a pin array 42. The mezzanine connector socket 41 is disposed on the OAM substrate 11, and is aligned and bonded to a pad array (not shown) disposed on the surface of the OAM substrate 11. The pin array 42 is disposed on the side of the optical engine module 13 facing the mezzanine connector socket 41, and the optical engine module 13 is inserted into the mezzanine connector socket 41, thereby forming an electrical connection between the pin array 42 and the pad array.

[0070] In an illustrative embodiment, an accelerator module is also provided, which includes a general-purpose substrate and at least one dual-chip OAM board module as described in any of the above embodiments, wherein the dual-chip OAM board module is plugged into the general-purpose substrate, and more specifically, the OAM board in the dual-chip OAM board module is plugged into the general-purpose substrate.

[0071] In the illustrative embodiment, the OAM substrate of the dual-chip OAM board module of this disclosure occupies the same space on a general-purpose substrate as the OAM substrate of two adjacent single-accelerator chip OAM boards. In the illustrative embodiment, the occupied space refers to the space occupied in the width direction of the OAM substrate.

[0072] Figure 5 This is a schematic diagram comparing the OAM substrate and two single-accelerator chip OAM substrates in an embodiment of this disclosure, according to an exemplary embodiment. Figure 5 As shown, for illustrative purposes, the OAM substrate of this embodiment can be referred to as a dual-accelerator chip OAM substrate 51. The y-axis direction is the width direction of the OAM substrate. For standardization, the OAM specification defines the width of the single-accelerator chip OAM substrate 52, denoted as 'a'. Furthermore, for the scalability of the OAM substrate, the OAM specification does not specify the length of the OAM substrate. Therefore, the OAM substrate can be appropriately increased in length to accommodate additional functional components. On a general-purpose substrate, adjacent single-accelerator chip OAM substrates 52 have a certain spacing, denoted as 'b', typically set to 1 mm. Based on this, the total width of two adjacent single-accelerator chip OAM substrates 52 in the width direction is a + b + a. Figure 5 As shown, the width of the OAM substrate (i.e., the dual-accelerator chip OAM substrate 51) in this embodiment is designed as a+b+a. In this way, the width of the OAM substrate (dual-accelerator chip OAM substrate 51) on the general substrate is the same as the total width of the two adjacent single-accelerator chip OAM substrates 52, thereby achieving compatibility with the OAM specification and facilitating the arrangement of this embodiment on the general substrate.

[0073] In the illustrative embodiment, the position of the connector on the universal substrate for inserting the OAM substrate is the same as the position of the connector for inserting two adjacent single-accelerator chip OAM substrates. Using this method, the universal substrate does not require additional specific modifications to the dual-chip OAM board module of this disclosure. In the dual-chip OAM board module of this disclosure, apart from improvements to the two optical engine modules, the connection and interaction between the two accelerator chips and the universal substrate remain unchanged. The corresponding connection positions on the OAM substrate and the universal substrate do not need to be modified. Therefore, it can still be inserted into the original universal substrate and work normally, ensuring structural and functional compatibility with related technologies.

[0074] In the illustrative embodiment, the size of the OAM substrate of this disclosure is the same as the total size of two adjacent single-accelerator chip OAM substrates and the gap between them. That is, the size of the OAM substrate of this disclosure is the same as the total size of two adjacent single-accelerator chip OAM substrates and the gap between them. For example, in the above description, the width dimension of the dual-accelerator chip OAM substrate 51 is the same as the total size of the width direction of two adjacent single-accelerator chip OAM substrates 52 and the gap between them. The area on the OAM substrate corresponding to the gap is used for device layout and / or wiring. Therefore, the dual-chip OAM board module of this disclosure, compared to the single-accelerator chip OAM board module of the related art, increases the space for device layout and / or wiring, providing convenient conditions for reducing wiring difficulty and further increasing the number of devices.

[0075] The dual-chip OAM board module and accelerator module of this disclosure are compatible with OAM accelerator modules of related technologies.

[0076] The dual-chip OAM board module of this disclosure can be an improvement on the OAM board module based on NPO (Near Packaged Optics) technology. NPO technology is an advanced packaging technology developed against the backdrop of the explosive growth in AI computing power demand leading to increasingly prominent bottlenecks in the bandwidth and power consumption of traditional electrical interconnects. NPO technology places the optical engine module directly on the OAM substrate, bringing it as close as possible to the accelerator chip, and achieves electrical interconnection through board-to-board mezzanine connectors, thereby replacing the remote connection method of traditional pluggable optical modules. The core of NPO technology lies in shortening the electrical signal transmission distance (significantly reducing the trace length from the chip to the optical engine) and relocating the optical I / O (input / output) ports from the motherboard or switch panel to the vicinity of the accelerator chip. NPO technology can significantly reduce insertion loss and signal attenuation in SerDes (serializer / deserializer) channels, improve signal integrity (SI), support reliable transmission at higher baud rates (such as 112G / 224G PAM4), reduce power consumption and the number of layers and area of ​​circuit boards (such as OAM substrates) required for high-speed electrical interconnects, and enable flexible configuration and maintenance of optical interfaces through modular optical engine design, thereby improving the overall bandwidth density and energy efficiency of AI server clusters.

[0077] In illustrative embodiments, the OAM board modules in the accelerator module of this disclosure can all be dual-chip OAM board modules of this disclosure. Alternatively, in illustrative embodiments, the accelerator module of this disclosure may also include at least one single-accelerator chip OAM board module; that is, the accelerator module of this disclosure can mix and match the accelerator module of this disclosure and single-accelerator chip OAM board modules of related technologies. This will be specifically explained below in conjunction with the 8-card conventional mode based on the OAM specification.

[0078] Figure 6A This is a schematic diagram of the layout structure in which a dual-chip OAM board module and six single-acceleration chip OAM board modules of this disclosure are arranged simultaneously on a general-purpose substrate. Figure 6B This is a schematic diagram of the layout structure in which two dual-chip OAM board modules and four single-acceleration chip OAM board modules of this disclosure are arranged simultaneously on a general-purpose substrate. Figure 6C This is a schematic diagram of the layout structure in which three dual-chip OAM board modules and two single-acceleration chip OAM board modules according to the present disclosure are arranged on a general-purpose substrate. Figure 6D This is a schematic diagram of the layout structure of four dual-chip OAM board modules according to the present disclosure arranged simultaneously on a general-purpose substrate.

[0079] Based on the OAM specification, in a standard setup, eight single-accelerator chip OAM board modules can be arranged on a general-purpose substrate 63. Therefore, as follows... Figure 6A As shown, a dual-chip OAM board module 61 and six single-accelerator chip OAM board modules 62 of this disclosure embodiment can be arranged on a general-purpose substrate 63. That is, the accelerator module may include a general-purpose substrate 63, a dual-chip OAM board module 61 and six single-accelerator chip OAM board modules 62, and the dual-chip OAM board module 61 and the six single-accelerator chip OAM board modules 62 are all plugged into the general-purpose substrate 63. Figure 6A The illustration is merely illustrative. The dual-chip OAM board module 61 can be arranged at any OAM board module mounting position on the universal substrate 63 as needed. Because the dual-chip OAM board module 61 includes two acceleration chips, one dual-chip OAM board module 61 is equivalent to two single-acceleration chip OAM board modules 62 in related technologies. Therefore, arranging one dual-chip OAM board module 61 and six single-acceleration chip OAM board modules 62 on the universal substrate 63 is equivalent to arranging eight single-acceleration chip OAM board modules 62 on the universal substrate 63. Furthermore, based on the dual-chip OAM board module 61, data interaction of the optical communication link between acceleration chips can also be realized. Figure 6B As shown, two dual-chip OAM board modules 61 and four single-acceleration chip OAM board modules 62 can also be arranged on the general-purpose substrate 63. That is to say, the accelerator module can include the general-purpose substrate 63, two dual-chip OAM board modules 61 and four single-acceleration chip OAM board modules 62, and the two dual-chip OAM board modules 61 and the four single-acceleration chip OAM board modules 62 are all plugged into the general-purpose substrate 63. Figure 6B The illustration is merely illustrative. The dual-chip OAM board module 61 can be arranged at any OAM board module mounting position on the universal substrate 63 as needed. Two dual-chip OAM board modules 61 are equivalent to four single-acceleration chip OAM board modules 62 in related technologies. Therefore, arranging two dual-chip OAM board modules 61 and four single-acceleration chip OAM board modules 62 on the universal substrate 63 is equivalent to arranging eight single-acceleration chip OAM board modules 62 on the universal substrate 63. Furthermore, based on the dual-chip OAM board module 61, data interaction of the optical communication link between acceleration chips can also be realized. Figure 6C As shown, three dual-chip OAM board modules 61 and two single-acceleration chip OAM board modules 62 can also be arranged on the general-purpose substrate 63. That is, the accelerator module can include the general-purpose substrate 63, three dual-chip OAM board modules 61 and two single-acceleration chip OAM board modules 62, and all three dual-chip OAM board modules 61 and two single-acceleration chip OAM board modules 62 are plugged into the general-purpose substrate 63. Figure 6CThe illustration is merely illustrative. The dual-chip OAM board module 61 can be arranged at any OAM board module mounting position on the universal substrate 63 as needed. Three dual-chip OAM board modules 61 are equivalent to six single-acceleration chip OAM board modules 62 in related technologies. Therefore, arranging three dual-chip OAM board modules 61 and two single-acceleration chip OAM board modules 62 on the universal substrate 63 is equivalent to arranging eight single-acceleration chip OAM board modules 62 on the universal substrate 63. Furthermore, based on the dual-chip OAM board module 61, data interaction of the optical communication link between acceleration chips can also be realized. Figure 6D As shown, four dual-chip OAM board modules 61 can also be arranged on the general-purpose substrate 63. That is, the accelerator module can include the general-purpose substrate 63 and four dual-chip OAM board modules 61. All four dual-chip OAM board modules 61 are plugged into the general-purpose substrate 63, and the accelerator module may not include single-accelerator chip OAM board modules. The four dual-chip OAM board modules 61 are equivalent to eight single-accelerator chip OAM board modules in the related technology. Therefore, arranging four dual-chip OAM board modules 61 on the general-purpose substrate 63 is also equivalent to arranging eight single-accelerator chip OAM board modules on the general-purpose substrate 63. Furthermore, based on the dual-chip OAM board modules 61, data interaction of the optical communication link between the acceleration chips can also be realized.

[0080] In the illustrative embodiment, the single-acceleration chip OAM board module 62 described above can be a common OAM board module in the related art, that is, an OAM board module that does not contain a light engine module, or it can be as follows: Figure 1 , Figure 2 The OAM board module shown contains one or two light engine modules 13.

[0081] In an illustrative embodiment, an accelerated computing server is also provided, which includes a dual-chip OAM board module as described in any of the preceding embodiments. The accelerated computing server's switching board is provided with an external optical module interface. Inside the accelerated computing server, the optical module interface is connected to the optical fiber output of the optical engine module 13 via optical fiber. Thus, other devices (such as other accelerated computing servers) can connect to the acceleration chip 12 in the dual-chip OAM board module of this disclosure and directly interact with the acceleration chip 12 by connecting the optical fiber from outside the accelerated computing server to the optical module interface.

[0082] In this embodiment, the optical engine module 13 refers to a photoelectric conversion subsystem for converting electrical signals to optical signals. It receives high-speed electrical signals from the accelerator chip 12 and converts them into optical signals, or converts received optical signals into electrical signals and transmits them to the accelerator chip 12. In this embodiment, the optical engine module 13 may not contain a DSP (Digital Signal Processor) module, and its power supply and electrical signal drive are provided by the OAM substrate 11.

[0083] In the illustrative embodiment, the acceleration chip in the dual-chip OAM board module of this disclosure is applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0084] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A dual-chip OAM board module, characterized in that, include: OAM substrate; An acceleration chip, wherein there are two acceleration chips, and the two acceleration chips are arranged along a first direction on the OAM substrate; The light engine module comprises two light engine modules, which are arranged along a second direction on the OAM substrate and are respectively located on both sides of the two acceleration chips. The second direction intersects with the first direction.

2. The dual-chip OAM board module according to claim 1, characterized in that: Each of the two optical engine modules is coupled to the two acceleration chips via a high-speed electrical interconnect link in the OAM substrate.

3. The dual-chip OAM board module according to claim 1, characterized in that: The two light engine modules include a first light engine module and a second light engine module; The high-speed input / output interface of the two acceleration chips, the one closer to the first optical engine module, is coupled to the first optical engine module. The high-speed input / output interface of the two acceleration chips, the one closer to the second optical engine module, is coupled to the second optical engine module.

4. The dual-chip OAM board module according to claim 1, characterized in that: The two acceleration chips are arranged edge-aligned on the OAM substrate.

5. The dual-chip OAM board module according to claim 1, characterized in that: The two light engine modules are located in the extension direction of the spacer region between the two acceleration chips.

6. The dual-chip OAM board module according to claim 1, characterized in that: The fiber optic outlets of the two optical engine modules face opposite directions.

7. The dual-chip OAM board module according to claim 1, characterized in that: The fiber optic outlets of the two optical engine modules face the same direction.

8. An accelerator module, characterized in that, include: Universal substrate; At least one dual-chip OAM board module as described in any one of claims 1 to 6, wherein the dual-chip OAM board module is plugged into the universal substrate.

9. The accelerator module according to claim 8, characterized in that: The space occupied by the OAM substrate on the general substrate is the same as the space occupied by two adjacent single-accelerator chip OAM substrates.

10. The accelerator module according to claim 8, characterized in that: The position of the connector on the general-purpose substrate for inserting the OAM substrate is the same as the position of the connector for inserting two adjacent single-acceleration chip OAM substrates.

11. The accelerator module according to claim 8, characterized in that: The size of the OAM substrate is the same as the total size of two adjacent single-accelerator chip OAM substrates and their gap. The area on the OAM substrate corresponding to the gap is used for device layout and / or wiring.

12. The accelerator module according to claim 8, characterized in that: All OAM board modules in the accelerator module are the dual-chip OAM board modules; or... The accelerator module also includes at least one single-accelerator chip OAM board module.

13. An accelerated computing server, characterized in that, Includes the dual-chip OAM board module as described in any one of claims 1 to 7.

Images