Data configuration method, memory storage device and memory control circuit unit

Abstract

This invention proposes a data configuration method, a memory storage device, and a memory control circuit unit. The data configuration method is used for a rewritable non-volatile memory module including multiple memory modules, and includes: dividing the memory module into multiple regions, including a first region and a second region, based on the distance between these memory modules and the memory control circuit unit, wherein the distance between the memory modules in the first region and the memory control circuit unit is greater than the distance between the memory modules in the second region and the memory control circuit unit; for a given data, determining whether the data is high-frequency read data or low-frequency read data; if the data is high-frequency read data, writing the data to the memory module in the first region; and if the data is low-frequency read data, writing the data to the memory module in the second region.

Description

Technical Field

[0001] This disclosure relates to a data configuration mechanism, and more particularly to a data configuration method, a memory storage device, and a memory control circuit unit for configuring data based on the distance between a storage module and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their characteristics such as data non-volatility, low power consumption, small size, and lack of mechanical structure.

[0003] In rewritable non-volatile memory modules, memory cells store data by changing a critical voltage. When a memory cell operates or stores data in a high-temperature environment, electrons in its charge trapping layer are more prone to leakage, causing the critical voltage of the memory cell to shift. This results in decreased data retention and an increased bit error rate. When the number of erroneous bits in the read data exceeds the range that the error checking and correction circuitry can correct, the controller must execute error handling procedures such as read retry, adjusting the read voltage level, or switching to computationally intensive software decoding. This increases read latency and affects the service quality of the memory device. Summary of the Invention

[0004] This disclosure proposes a data configuration method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple memory modules. This data configuration method includes: dividing the memory modules into multiple regions based on the distance between these memory modules and memory control circuitry units, wherein these regions include a first region and a second region, the distance between the memory modules in the first region and the memory control circuitry units is greater than the distance between the memory modules in the second region and the memory control circuitry units; for data, determining whether the data is high-frequency read data or low-frequency read data; if the data is high-frequency read data, writing the data to the memory modules in the first region; and if the data is low-frequency read data, writing the data to the memory modules in the second region.

[0005] In one embodiment of this disclosure, the step of determining whether the data belongs to high-frequency read data or low-frequency read data includes: calculating the data disorder of the data; if the data disorder is greater than a threshold, determining that the data belongs to low-frequency read data; and if the data disorder is less than or equal to the threshold, determining that the data belongs to high-frequency read data.

[0006] In one embodiment of this disclosure, the step of determining whether the data belongs to high-frequency read data or low-frequency read data includes: obtaining the compression ratio of the data; if the compression ratio is greater than a threshold, determining that the data belongs to high-frequency read data; and if the compression ratio is less than or equal to the threshold, determining that the data belongs to low-frequency read data.

[0007] In one embodiment of this disclosure, the step of determining whether the data belongs to high-frequency read data or low-frequency read data includes: determining whether the data belongs to the same bit data of the error correction code, which is generated when the storage module performs a full stripe write; if the data belongs to the same bit data of the error correction code, determining that the data belongs to low-frequency read data; and if the data does not belong to the same bit data of the error correction code, determining that the data belongs to high-frequency read data.

[0008] In one embodiment of this disclosure, the above-described data configuration method further includes: initiating a data consolidation procedure, selecting a source physical unit from these storage modules, and reading the data from the source physical unit.

[0009] In one embodiment of this disclosure, the above-described data configuration method further includes: receiving a write instruction from a host system, the write instruction being used to write the data.

[0010] In one embodiment of this disclosure, the data configuration method further includes at least one of the following steps: setting the decoding capability of the error correction code applied by the storage module in the second area to be greater than the decoding capability of the error correction code applied by the storage module in the first area; setting the refresh frequency of the storage module in the second area to be greater than the refresh frequency of the storage module in the first area; or setting the erase limit of the storage module in the second area to be less than the erase limit of the storage module in the first area.

[0011] In one embodiment disclosed herein, the temperature of the storage module in the first region is lower than the temperature of the storage module in the second region.

[0012] In one embodiment disclosed herein, each storage module includes a temperature sensor for measuring multiple temperatures corresponding to these storage modules. The data configuration method described above further includes dynamically adjusting the storage modules contained in the multiple regions based on these temperatures.

[0013] This disclosure proposes a memory storage device including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The rewritable non-volatile memory module includes multiple memory modules. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module to perform multiple steps: dividing the memory modules into multiple regions based on the distance between them and the memory control circuit unit, wherein these regions include a first region and a second region, the distance between the memory modules in the first region and the memory control circuit unit is greater than the distance between the memory modules in the second region and the memory control circuit unit; for data, determining whether the data is high-frequency read data or low-frequency read data; if the data is high-frequency read data, writing the data to the memory module in the first region; and if the data is low-frequency read data, writing the data to the memory module in the second region.

[0014] This disclosure proposes a memory control circuit unit for controlling a rewritable non-volatile memory module. This memory control circuit unit includes a host interface, a memory interface, and memory management circuitry. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module, which includes multiple memory modules. The memory management circuitry, coupled to the host interface and the memory interface, performs several steps: dividing the memory modules into multiple zones based on the distance between them and the memory control circuit unit, including a first zone and a second zone, wherein the distance between the memory modules in the first zone and the memory control circuit unit is greater than the distance between the memory modules in the second zone and the memory control circuit unit; for data, determining whether the data is high-frequency or low-frequency read data; if the data is high-frequency read data, writing the data to the memory module in the first zone; and if the data is low-frequency read data, writing the data to the memory module in the second zone.

[0015] In the aforementioned data configuration method, memory storage device, and memory control circuit unit, data that is read more frequently can be stored in a storage module with a relatively low temperature, thereby reducing the number of erroneous bits during reading and the cost of error correction, and improving the read latency and reliability of the memory storage device. Attached Figure Description

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0023] Figure 7 This is a flowchart illustrating a data configuration method according to an exemplary embodiment of the present invention. Detailed Implementation

[0024] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered identical or similar when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of systems and methods within the scope of the present invention's patent application.

[0025] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0026] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as control circuitry). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0027] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0028] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0029] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0030] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0031] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0032] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0033] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0034] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0035] The interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the interface unit 41. In one exemplary embodiment, the interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside the chip containing the memory control circuit unit 42.

[0036] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0037] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one cell), a quadruple-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one cell), other flash memory modules, or other memory modules with the same characteristics.

[0038] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus the one or more bits stored in that memory cell can be retrieved.

[0039] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0040] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of each physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage units that are erased. For example, a physical erase unit is a physical block.

[0041] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0042] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0043] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0044] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0045] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0046] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to acquire and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. Furthermore, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 can also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0047] Memory interface 53 is coupled to memory management circuitry 51 and used to access rewritable non-volatile memory module 43. For example, memory management circuitry 51 can access rewritable non-volatile memory module 43 through memory interface 53. That is, data to be written to rewritable non-volatile memory module 43 is converted by memory interface 53 into a format acceptable to rewritable non-volatile memory module 43. Specifically, if memory management circuitry 51 needs to access rewritable non-volatile memory module 43, memory interface 53 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by memory management circuitry 51 and transmitted to rewritable non-volatile memory module 43 through memory interface 53. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0048] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, a power management circuit 56, and a compression circuit 57.

[0049] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 obtains a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 can use various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code to encode and decode data.

[0050] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0051] Compression circuit 57 is coupled to memory management circuit 51 and is used to perform compression and decompression operations on data. Specifically, when memory management circuit 51 wants to write data to rewritable non-volatile memory module 43, compression circuit 57 can first perform a compression operation on the data to generate compressed data, thereby reducing the amount of data actually written to rewritable non-volatile memory module 43, thus saving storage space and reducing the number of times the memory cell is programmed. When memory management circuit 51 reads compressed data from rewritable non-volatile memory module 43, compression circuit 57 can perform a corresponding decompression operation on the compressed data to restore the original data. In one exemplary embodiment, the compression algorithm used by the compression circuit 57 is a lossless compression algorithm, such as run-length encoding (RLE), Huffman coding, arithmetic coding, dictionary coding, LZ77 algorithm, LZ78 algorithm, LZW (Lempel-Ziv-Welch) algorithm, etc. In one exemplary embodiment, the compression circuit 57 may also use a compression algorithm with distortion. In one exemplary embodiment, the compression circuit 57 may be implemented as a hardware compression engine independent of the memory management circuit 51, or it may be integrated into the memory management circuit 51, or it may be executed by the memory management circuit 51 in the form of firmware or program code; the present invention is not limited thereto.

[0052] In one exemplary embodiment, after performing a compression operation on the data, the compression circuit 57 obtains a compression ratio for the data and transmits this compression ratio to the memory management circuit 51. Herein, compression ratio is a parameter representing the degree to which the amount of data is reduced after compression. In one exemplary embodiment, the compression ratio is expressed as the ratio of the data size before compression to the data size after compression. For example, if a piece of data is 4 kilobytes (KB) in size before compression and 1 kilobyte in size after compression, then the compression ratio of this data is 4. In other embodiments, the compression ratio may have other definitions, and this invention is not limited thereto.

[0053] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0054] Figure 6This is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The rewritable non-volatile memory module 43 includes multiple memory modules 601-606. The memory control circuit unit 42 and the rewritable non-volatile memory module 43 are disposed in the memory storage device 10, and the memory control circuit unit 42 is connected via... Figure 5 The memory interface 53 is coupled to the memory modules 601-606 to perform operations such as writing, reading, and erasing data on the memory modules 601-606. It should be noted that... Figure 6 The number of storage modules shown is merely an example. In other exemplary embodiments, the number of storage modules included in the rewritable non-volatile memory module 43 may be two, four, eight, sixteen, or more. This invention does not limit the number of storage modules.

[0055] In one exemplary embodiment, each of the storage modules 601-606 may include one or more chips, each chip including multiple dies, and each die including multiple physical units. In one exemplary embodiment, a storage module may also refer to a package, a die, or one or more chips connected to the same channel or the same chip enable signal.

[0056] In one exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In another exemplary embodiment, a physical unit may also consist of multiple consecutive or non-consecutive physical addresses. In yet another exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In one exemplary embodiment, a virtual block may include one or more physical erase units. For example, a virtual block may consist of multiple physical erase units located on different dies or connected to different channels, allowing the memory control circuitry unit 42 to perform parallel access operations on these physical erase units to improve access performance.

[0057] Please continue to refer to Figure 6 The distances between storage modules 601-606 and memory control circuit unit 42 are not the same. Specifically, in Figure 6In the exemplary embodiment, storage modules 601-606 are arranged sequentially, with storage module 601 being closest to the memory control circuit unit 42 and storage module 606 being furthest from the memory control circuit unit 42. The memory management circuit 51 can divide the storage modules 601-606 into multiple zones based on the distance between them and the memory control circuit unit 42, for example, into a first zone 610 and a second zone 620. Figure 6 In an exemplary embodiment, the second region 620 includes storage modules 601-603, while the first region 610 includes storage modules 604-606. The distance between the storage modules (i.e., storage modules 604-606) in the first region 610 and the memory control circuit unit 42 is different from the distance between the storage modules (i.e., storage modules 601-603) and the memory control circuit unit 42 in the second region 620.

[0058] In one exemplary embodiment, the distance between the storage module and the memory control circuit unit 42 in the first region 610 is greater than the distance between the storage module and the memory control circuit unit 42 in the second region 620. In other words, the first region 610 is relatively far away from the memory control circuit unit 42, while the second region 620 is relatively close to the memory control circuit unit 42.

[0059] During operation, the memory control circuit unit 42 performs numerous calculations, including mapping between logical and physical addresses, encoding and decoding error correction codes, data compression and decompression, and high-speed signal transmission. Therefore, the memory control circuit unit 42 is one of the main heat sources inside the memory storage device 10. The heat generated by the memory control circuit unit 42 is conducted to the surrounding storage modules via the copper foil of the circuit board, the encapsulation material, and the air inside the memory storage device 10. Since the path length of heat conduction increases with distance, the storage modules closer to the memory control circuit unit 42 have higher temperatures, while those farther away have lower temperatures. Accordingly, when the memory storage device 10 continues to operate and reaches thermal equilibrium, a steady-state temperature gradient forms inside the memory storage device 10, causing the temperature of storage modules 604-606 in the first region 610 to be lower than the temperature of storage modules 601-603 in the second region 620.

[0060] Generally, when the memory cells in the rewritable non-volatile memory module 43 operate or store data in a high-temperature environment, electrons in their charge trapping layer are more prone to leakage, causing the critical voltage of the memory cell to shift. This results in a decrease in data retention capacity and an increase in the raw bit error rate (RBER). Therefore, in an exemplary embodiment, the memory management circuit 51 allocates frequently accessed data to the memory module in the relatively low-temperature first region 610 and less frequently accessed data to the relatively high-temperature second region 620, thereby reducing the read load and error correction costs borne by the higher-temperature memory modules.

[0061] In this document, high-frequency read data refers to data that is read relatively frequently, while low-frequency read data refers to data that is read relatively infrequently. For example, file system metadata, file configuration tables, directory structures, journals, mapping tables between logical and physical addresses, and operating system boot files are considered high-frequency read data because they are repeatedly read by the host system 11. Conversely, backup data, archived data, video files, and parity data for error correction codes are considered low-frequency read data because they are read less frequently under normal operating conditions. It should be noted that high-frequency and low-frequency read data are relative concepts, and the criteria for their determination can be adjusted according to the actual usage scenario of the memory storage device 10; this invention does not impose any limitations on these criteria.

[0062] Figure 7 This is a flowchart illustrating a data configuration method according to an exemplary embodiment of the present invention. Please refer to... Figure 7 In step 701, the memory management circuit 51 divides the memory modules 601-606 into multiple zones based on the distance between the memory modules 601-606 and the memory control circuit unit 42, for example... Figure 6 Zone 1, 610 and Zone 2, 620.

[0063] In one exemplary embodiment, the distance in step 701 is any measure sufficient to reflect the length of the thermal conduction path between the storage module and the memory control circuit unit 42, including but not limited to: (1) the physical straight-line distance between the storage module and the memory control circuit unit 42 on the circuit board; (2) the equivalent distance calculated based on the thermal conduction path; and (3) an order value derived from the package location number, channel number, or chip enable number of the storage module to indicate relative proximity.

[0064] In one exemplary embodiment, the number of zones into which storage modules 601-606 are divided is not limited to two. For example, the memory management circuit 51 may divide storage modules 601-606 into three or more zones, such as a first zone, a second zone, and a third zone, wherein the distance between the storage modules in each zone and the memory control circuit unit 42 increases sequentially, and the memory management circuit 51 may allocate data to one of the zones according to the frequency of data being read. In one exemplary embodiment, the number of storage modules contained in each zone may also be different. For example, when the total number of storage modules is six, the first zone 610 may contain four storage modules and the second zone 620 may contain two storage modules; the present invention is not limited thereto.

[0065] In one exemplary embodiment, the configuration of storage modules 601-606 is not limited to... Figure 6 The diagram shows a single-row arrangement. For example, storage modules 601-606 can be distributed on the front and back of the circuit board. Storage modules located on the back of the circuit board opposite the memory control circuit unit 42 can be classified into the second area 620 because they are separated from the memory control circuit unit 42 only by the circuit board. In an exemplary embodiment, storage modules 601-606 can also be distributed around the memory control circuit unit 42, in which case the memory management circuit 51 can divide the storage modules 601-606 into multiple areas based on the radial distance between each storage module and the memory control circuit unit 42. In an exemplary embodiment, storage modules 601-606 can also be stacked or distributed on multiple circuit boards.

[0066] In one exemplary embodiment, the operation of dividing storage modules 601-606 into multiple zones can be predetermined based on the circuit board layout information before the memory storage device 10 leaves the factory. The partitioning results are recorded in tabular form in the system of the rewritable non-volatile memory module 43. The partitioning results can be used to reflect the corresponding temperature range or the relative distance between each storage module and the corresponding memory controller, and are loaded into the buffer memory 55 when the memory storage device 10 is powered on. In one exemplary embodiment, each storage module 601-606 includes a temperature sensor to measure the temperature corresponding to these storage modules 601-606. The memory management circuit 51 can also dynamically adjust the storage modules contained in these zones based on these temperatures. For example, when the measured temperature of a storage module in the first zone 610 is consistently higher than a preset temperature threshold, the memory management circuit 51 can reclassify this storage module to the second zone 620.

[0067] In step 702, the memory management circuit 51 acquires data. In an exemplary embodiment, this data comes from the host system 11. Specifically, the memory management circuit 51 can receive a write command from the host system 11 via the host interface 52. This write command is used to write the data, and the memory management circuit 51 can temporarily store this data in the buffer memory 55 to await subsequent configuration and writing. In an exemplary embodiment, this data can also be system data generated internally by the memory storage device 10, such as a mapping table between logical addresses and physical addresses, parity data of error correction codes, or statistical information recorded by the memory management circuit 51.

[0068] In one exemplary embodiment, the memory management circuit 51 may also obtain this data by executing a data merging procedure, also known as a garbage collection (GC) procedure. In the data merging procedure, the memory management circuit 51 selects one or more source physical units from storage modules 601-606 and reads the data from the source physical units. The memory management circuit 51 writes the data read from the source physical units to a target physical unit, updates the mapping between logical addresses and physical addresses, and then performs an erase operation on the source physical unit, restoring it to a writable, idle physical unit. Subsequent steps 704 and 705 determine which region the target physical unit belongs to.

[0069] In step 703, the memory management circuit 51 determines whether the data belongs to high-frequency or low-frequency read data. In an exemplary embodiment, the memory management circuit 51 makes this determination based on the content characteristics of the data itself, without relying on information provided by the host system 11 or additional hardware for counting accesses, thus reducing implementation costs. Several methods for determining whether the data belongs to high-frequency or low-frequency read data are described below. These methods can be executed individually or in combination, and the present invention is not limited thereto.

[0070] In one exemplary embodiment, the memory management circuit 51 calculates a data disorder of the data. If the data disorder is greater than a threshold, the data is determined to be low-frequency read data; if the data disorder is less than or equal to the threshold, the data is determined to be high-frequency read data. In this document, data disorder refers to a parameter reflecting the randomness or irregularity of the data content. In one exemplary embodiment, data disorder is the entropy of the data. For example, the memory management circuit 51 can treat each or more bytes in the data as a symbol, count the probability of each symbol appearing in the data, and calculate the entropy of the data according to the definition of Shannon entropy. The more evenly the distribution of symbols in the data and the lower the repetition, the higher its entropy value; conversely, the lower the entropy value, the more repetitive the data contains, or the more regular the pattern.

[0071] File system intermediate data, logs, directory structures, and mapping tables typically have fixed field formats and contain a large number of zero values ​​or repetitive patterns, resulting in relatively low data disorder. On the other hand, compressed or encrypted audio / video files, archived files, and other data have content that is nearly randomly distributed, leading to relatively high data disorder. The memory management circuit 51 can classify data with a disorder level less than or equal to a threshold as high-frequency read data and data with a disorder level greater than the threshold as low-frequency read data. It should be noted that calculating the data disorder of this data does not necessarily require compression. In other words, the memory management circuit 51 can directly perform statistical operations on uncompressed data to obtain the data disorder without first initiating compression circuit 57 to perform compression operations on the data.

[0072] In one exemplary embodiment, the memory management circuit 51 obtains a compression ratio of the data and determines whether the data is high-frequency or low-frequency read data based on the compression ratio. Specifically, the memory management circuit 51 can transmit the data to the compression circuit 57, which performs a compression operation on the data and transmits the obtained compression ratio back to the memory management circuit 51. Since the compression circuit 57 performs compression operations on the data during the data writing process or data merging process, the compression ratio is a low-cost signal that can be provided by existing circuitry, and the memory management circuit 51 does not need to add additional hardware to determine the frequency of data reading. Since the compressibility of data is positively correlated with the repetitiveness of the data content, data with a higher compression ratio is usually highly repetitive intermediate data or log data, which is read relatively frequently. Data with a lower compression ratio is usually already compressed or encrypted data, which is read relatively infrequently. Accordingly, the memory management circuit 51 can determine data with a compression ratio greater than a threshold as high-frequency read data and data with a compression ratio less than or equal to the threshold as low-frequency read data.

[0073] In one exemplary embodiment, the memory management circuit 51 determines whether the data belongs to a co-bit of an error correction code. If the data belongs to the co-bit of an error correction code, it is determined that the data is low-frequency read data; if the data does not belong to the co-bit of an error correction code, it is determined that the data is high-frequency read data. In this document, co-bit data refers to protection data generated from multiple data entries and used to restore a portion of the data when some bits cannot be read correctly. In some embodiments, co-bit data is generated when a full-stripe write is performed on memory modules 601-606. For example, the error checking and correction circuit 54 writes multiple data entries, and performing an exclusive OR (XOR) operation on these data entries generates co-bit data. These written data entries and co-bit data entries are distributed across all memory modules 601-606. When one of the multiple data entries cannot be corrected due to an excessive number of error bits, the memory management circuit 51 can restore the data entry based on the remaining data and this co-bit data.

[0074] Since the parity data is only read during data restoration and is rarely read under normal operating conditions of the memory storage device 10, it is considered low-frequency read data. The memory management circuit 51 allocates the parity data to the storage modules in the second zone 620, reserving the storage modules in the relatively cooler first zone 610 for more frequently read data. In an exemplary embodiment, the aforementioned parity data is generated during a full-stripe write operation on multiple storage modules.

[0075] In one exemplary embodiment, the memory management circuit 51 may also use other methods to determine whether the data belongs to high-frequency or low-frequency read data. For example, the memory management circuit 51 may maintain a read counter for each logical address or each physical unit, and determine whether the data belongs to high-frequency or low-frequency read data based on whether the count value of the read counter is greater than a threshold. In one exemplary embodiment, the memory management circuit 51 may make the determination based on the size of the data, for example, classifying data with a small amount of data and discontinuous logical addresses as high-frequency read data, and classifying data with a large amount of data and contiguous logical addresses as low-frequency read data. In one exemplary embodiment, the memory management circuit 51 may also input multiple features of the data into a machine learning model to determine whether the data belongs to high-frequency or low-frequency read data, wherein the machine learning model may be a decision tree, random forest, support vector machine (SVM), deep neural network (DNN), or convolutional neural network (CNN), etc.

[0076] It should be noted that the thresholds used in the various judgment methods described above can be preset fixed values, or they can be values ​​dynamically adjusted by the memory management circuit 51 based on the operating status of the memory storage device 10 (e.g., the remaining available space in the first area 610, the measured temperature of the memory storage device 10, or the access status of the host system 11). In an exemplary embodiment, the memory management circuit 51 can also simultaneously employ multiple judgment methods described above, and perform weighted or voting calculations based on the results obtained from each judgment method to determine whether the data belongs to high-frequency read data or low-frequency read data. Furthermore, in an exemplary embodiment, when the storage module in the first area 610 has insufficient available space, the memory management circuit 51 can also write the data judged as high-frequency read data to the storage module in the second area 620 first, and then move this data to the storage module in the first area 610 in the subsequent data merging process. This invention does not impose any limitations.

[0077] If the determination result of step 703 indicates that the data belongs to high-frequency read data, in step 704, the memory management circuit 51 writes this data to the storage module in the first area 610. In other words, data with a relatively high read frequency will be written to storage modules 604-606 that are relatively far away from the memory control circuit unit 42 and have a relatively low temperature.

[0078] If the determination result of step 703 indicates that the data belongs to low-frequency read data, in step 705, the memory management circuit 51 writes this data to the storage module in the second area 620. In other words, data read at a relatively low frequency will be written to the storage modules 601-603, which are relatively close to the memory control circuit unit 42 and have a relatively high temperature.

[0079] In one exemplary embodiment, step 706 may be additionally executed after step 705. In step 706, the memory management circuit 51 executes one or more protection procedures. Because the storage module in the second region 620 has a relatively high temperature and relatively poor data retention capability, the memory management circuit 51 can provide relatively strong protection to the storage module in the second region 620 to compensate for the reliability difference caused by the high temperature. Several protection procedures are described below.

[0080] In one exemplary embodiment, the memory management circuit 51 sets the decoding capability of the error correction code applied by the memory module in the second region 620 to be greater than that of the error correction code applied by the memory module in the first region 610. Here, decoding capability refers to the maximum number of error bits that the error checking and correction circuit 54 can correct when performing a decoding operation on a codeword based on the error correction code. For example, if an error correction code can correct up to 40 error bits in a codeword, then the decoding capability of this error correction code is 40 bits. In one exemplary embodiment, the memory management circuit 51 can improve the decoding capability by increasing the number of co-occurring bits in each codeword (i.e., reducing the code rate of the error correction code). For example, the memory management circuit 51 can set the code rate of the error correction code applied to the storage module in the first area 610 to 0.9 and the code rate of the error correction code applied to the storage module in the second area 620 to 0.8, so that the error correction code applied to the storage module in the second area 620 has a higher decoding capability. In an exemplary embodiment, the memory management circuit 51 can also improve the decoding capability by changing the decoding method, such as changing hard decoding to soft decoding, increasing the number of decoding iterations of the low-density parity check code, or adopting a coding algorithm with stronger correction capability. In an exemplary embodiment, the memory management circuit 51 can also additionally establish parity data for the data stored in the storage module in the second area 620 to provide additional protection.

[0081] In one exemplary embodiment, the memory management circuit 51 sets a refresh frequency for the storage modules in the second region 620 to be greater than a refresh frequency for the storage modules in the first region 610. Here, refresh refers to the operation where the memory management circuit 51 reads data stored in a physical unit, checks the number of error bits, and, if the number of error bits exceeds a preset number, moves the data and rewrites it to another physical unit. This operation is also called a data scrub or read patrol. The refresh frequency refers to the number of times the above refresh operation is performed on the storage modules per unit time. For example, the memory management circuit 51 may be set to perform a refresh operation on the storage modules in the second region 620 once every day, and to perform a refresh operation on the storage modules in the first region 610 once every two days. By increasing the refresh frequency of the storage modules in the second region 620, data can be moved to other physical units before error bits accumulate to a point where they cannot be corrected, thus reducing the risk of data loss.

[0082] In one exemplary embodiment, the memory management circuit 51 sets the erase limit of the storage modules in the second region 620 to be less than the erase limit of the storage modules in the first region 610. Here, the erase limit refers to the upper limit of the number of erase operations allowed to be performed by the physical erase units in the storage modules. For example, the memory management circuit 51 may set the erase limit of the storage modules in the first region 610 to 3000 times and the erase limit of the storage modules in the second region 620 to 2000 times, such that when the erase count of a physical erase unit in the second region 620 reaches 2000 times, the memory management circuit 51 will no longer write data to this physical erase unit, or will mark this physical erase unit as only for storing data with low frequency of changes. Since storage units experience significant wear and tear when operating in high-temperature environments, reducing the erase limit of the storage modules in the second region 620 can prevent the storage modules operating in high-temperature environments from being overused and failing prematurely, thus extending the overall lifespan of the memory storage device 10.

[0083] It should be noted that the above-mentioned protection procedures, such as setting the decoding capability of the error correction code, setting the refresh frequency, and setting the erase limit, can be executed one by one, or two or all of them can be executed simultaneously; this invention is not limited to this. In an exemplary embodiment, the memory management circuit 51 can also adjust the strength of the protection procedures applicable to the memory modules in each area step by step based on the distance between each memory module and the memory control circuit unit 42, the measured temperature of each memory module, or the accumulated number of erases of each memory module. In an exemplary embodiment, the memory management circuit 51 can also determine whether to execute step 706 based on the measured temperature of the memory storage device 10. For example, step 706 is not executed when the measured temperature of the memory storage device 10 is lower than a preset temperature, thereby reducing the performance loss caused by additional calculations and relocation.

[0084] Figure 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 7 Each step can be implemented as multiple program codes or circuits, but this invention is not limited thereto. Furthermore, Figure 7 The method can be used in conjunction with the above embodiments or alone; in other words, Figure 7 Other steps can also be added between the various steps.

[0085] In summary, in the data configuration method, memory storage device, and memory control circuit unit provided in the exemplary embodiments of the present invention, writing high-frequency read data to a storage module in a first region that is far from the memory control circuit unit and has a relatively low temperature can reduce the number of error bits that occur when such data is repeatedly read. Furthermore, compared to a method that reduces operating speed only after the temperature rises, the above-described data configuration method actively maps data to a storage module with an appropriate temperature during the data writing stage, thus effectively improving the reliability differences between storage modules caused by temperature gradients.

[0086] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A data configuration method, characterized in that, A method for configuring a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple memory modules, and the data configuration method includes: The plurality of storage modules are divided into multiple zones based on the distance between the plurality of storage modules and the memory control circuit unit, wherein the plurality of zones include a first zone and a second zone, and the distance between the storage modules and the memory control circuit unit in the first zone is greater than the distance between the storage modules and the memory control circuit unit in the second zone; For the data, determine whether the data belongs to high-frequency reading data or low-frequency reading data; If the data belongs to the high-frequency read data, the data is written to the storage module in the first area; and If the data belongs to the low-frequency read data, the data is written to the storage module in the second area.

2. The data configuration method according to claim 1, characterized in that, The steps for determining whether the data belongs to the high-frequency read data or the low-frequency read data include: Calculate the data disorder of the data; If the data disorder exceeds a threshold, the data is determined to belong to the low-frequency read data; and If the data disorder is less than or equal to the threshold, the data is determined to belong to the high-frequency read data.

3. The data configuration method according to claim 1, characterized in that, The steps for determining whether the data belongs to the high-frequency read data or the low-frequency read data include: Obtain the compression ratio of the data; If the compression ratio is greater than the threshold, the data is determined to belong to the high-frequency read data; and If the compression ratio is less than or equal to the threshold, the data is determined to belong to the low-frequency read data.

4. The data configuration method according to claim 1, characterized in that, The steps for determining whether the data belongs to the high-frequency read data or the low-frequency read data include: Determine whether the data belongs to the parity data of the error correction code, wherein the parity data is generated when the multiple storage modules are performed full stripe write; If the data belongs to the same bit as the error correction code, then the data is determined to belong to the low-frequency read data; and If the data does not belong to the same bit data of the error correction code, it is determined that the data belongs to the high-frequency read data.

5. The data configuration method according to claim 1, characterized in that, Also includes: Initiate the data consolidation process, select a source physical unit from the plurality of storage modules, and read the data from the source physical unit.

6. The data configuration method according to claim 1, characterized in that, Also includes: Receive a write command from the host system, the write command being used to write the data.

7. The data configuration method according to claim 1, characterized in that, It also includes at least one of the following steps: The decoding capability of the error correction code applied by the storage module in the second area is set to be greater than the decoding capability of the error correction code applied by the storage module in the first area; The refresh rate of the storage module in the second area is set to be greater than the refresh rate of the storage module in the first area; or The erase limit of the storage module in the second area is set to be less than the erase limit of the storage module in the first area.

8. The data configuration method according to claim 1, characterized in that, The temperature of the storage module in the first area is lower than the temperature of the storage module in the second area.

9. The data configuration method according to claim 1, characterized in that, Each of the plurality of storage modules includes a temperature sensor for measuring multiple temperatures corresponding to the plurality of storage modules, and the data configuration method further includes: The storage modules contained in the multiple zones are dynamically adjusted according to the multiple temperatures.

10. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple memory modules; as well as A memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, is used to perform multiple steps: The plurality of storage modules are divided into multiple zones based on the distance between the plurality of storage modules and the memory control circuit unit, wherein the plurality of zones include a first zone and a second zone, and the distance between the storage modules and the memory control circuit unit in the first zone is greater than the distance between the storage modules and the memory control circuit unit in the second zone; For the data, determine whether the data belongs to high-frequency reading data or low-frequency reading data; If the data belongs to the high-frequency read data, the data is written to the storage module in the first area; as well as If the data belongs to the low-frequency read data, the data is written to the storage module in the second area.

11. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is also used for: Calculate the data disorder of the data; If the data disorder is greater than the threshold, the data is determined to belong to the low-frequency read data; as well as If the data disorder is less than or equal to the threshold, the data is determined to belong to the high-frequency read data.

12. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is also used for: Obtain the compression ratio of the data; If the compression ratio is greater than the threshold, the data is determined to belong to the high-frequency read data; and If the compression ratio is less than or equal to the threshold, the data is determined to belong to the low-frequency read data.

13. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is also used for: Determine whether the data belongs to the parity data of the error correction code, wherein the parity data is generated when the multiple storage modules are performed full stripe write; If the data belongs to the same bit data of the error correction code, it is determined that the data belongs to the low-frequency read data; as well as If the data does not belong to the same bit data of the error correction code, it is determined that the data belongs to the high-frequency read data.

14. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is also used for: Initiate the data consolidation process, select a source physical unit from the plurality of storage modules, and read the data from the source physical unit.

15. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is also used for: Receive a write command from the host system, the write command being used to write the data.

16. The memory storage device according to claim 10, characterized in that, The memory control circuit unit is also configured to perform at least one of the following steps: The decoding capability of the error correction code applied by the storage module in the second area is set to be greater than the decoding capability of the error correction code applied by the storage module in the first area; The refresh rate of the storage module in the second area is set to be greater than the refresh rate of the storage module in the first area; or The erase limit of the storage module in the second area is set to be less than the erase limit of the storage module in the first area.

17. The memory storage device according to claim 10, characterized in that, The temperature of the storage module in the first area is lower than the temperature of the storage module in the second area.

18. The memory storage device according to claim 10, characterized in that, Each of the plurality of storage modules includes a temperature sensor for measuring multiple temperatures corresponding to the plurality of storage modules. The memory control circuit unit is further configured to dynamically adjust the memory modules contained in the plurality of zones according to the plurality of temperatures.

19. A memory control circuit unit, characterized in that, The memory control circuit unit is used to control the rewritable non-volatile memory module and includes: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple memory modules; A memory management circuit, coupled to the host interface and the memory interface, is used to perform multiple steps: The plurality of storage modules are divided into multiple zones based on the distance between the plurality of storage modules and the memory control circuit unit, wherein the plurality of zones include a first zone and a second zone, and the distance between the storage modules and the memory control circuit unit in the first zone is greater than the distance between the storage modules and the memory control circuit unit in the second zone; For the data, determine whether the data belongs to high-frequency reading data or low-frequency reading data; If the data belongs to the high-frequency read data, the data is written to the storage module in the first area; and If the data belongs to the low-frequency read data, the data is written to the storage module in the second area.

20. The memory control circuit unit according to claim 19, characterized in that, The memory management circuit is also used for: Calculate the data disorder of the data; If the data disorder is greater than the threshold, the data is determined to belong to the low-frequency read data; as well as If the data disorder is less than or equal to the threshold, the data is determined to belong to the high-frequency read data.

21. The memory control circuit unit according to claim 19, characterized in that, The memory management circuit is also used for: Obtain the compression ratio of the data; If the compression ratio is greater than the threshold, the data is determined to belong to the high-frequency read data; and If the compression ratio is less than or equal to the threshold, the data is determined to belong to the low-frequency read data.

22. The memory control circuit unit according to claim 19, characterized in that, The memory management circuit is also used for: Determine whether the data belongs to the parity data of the error correction code, wherein the parity data is generated when the multiple storage modules are performed full stripe write; If the data belongs to the same bit data of the error correction code, it is determined that the data belongs to the low-frequency read data; as well as If the data does not belong to the same bit data of the error correction code, it is determined that the data belongs to the high-frequency read data.

23. The memory control circuit unit according to claim 19, characterized in that, The memory management circuit is also used for: Initiate the data consolidation process, select a source physical unit from the plurality of storage modules, and read the data from the source physical unit.

24. The memory control circuit unit according to claim 19, characterized in that, The memory management circuit is also used for: Receive a write command from the host system, the write command being used to write the data.

25. The memory control circuit unit according to claim 19, characterized in that, The memory management circuitry is also configured to perform at least one of the following steps: The decoding capability of the error correction code applied by the storage module in the second area is set to be greater than the decoding capability of the error correction code applied by the storage module in the first area; The refresh rate of the storage module in the second area is set to be greater than the refresh rate of the storage module in the first area; or The erase limit of the storage module in the second area is set to be less than the erase limit of the storage module in the first area.

26. The memory control circuit unit according to claim 19, characterized in that, The temperature of the storage module in the first area is lower than the temperature of the storage module in the second area.

27. The memory control circuit unit according to claim 19, characterized in that, Each of the plurality of storage modules includes a temperature sensor for measuring multiple temperatures corresponding to the plurality of storage modules. The memory management circuit is further configured to dynamically adjust the memory modules contained in the plurality of zones according to the plurality of temperatures.

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