Vector processing circuit and vector processing method
Patent Information
- Application Number
- CN202510543932.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2025-04-28
- Publication Date
- 2026-09-29
AI Technical Summary
然而,这种扩展方式受到矢量暂存器档(vector register file,VRF)读写端口数量的限制,导致数据在传输至功能单元(function unit, FU)时的效率降低,进而影响整体运算效能
[0003]为了解决上述问题,本揭示提出一种矢量处理电路以及矢量处理方法。
Smart Images
Figure CN122838356A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a vector processor and a vector processing method using a two-dimensional temporary register. Background Technology
[0002] With the rapid growth in demand for high computing power, expanding computing capabilities within existing processor architectures has become a pressing issue. In vector processors, to improve computational performance, functionality is typically expanded by adding matrix multiplication units. However, this expansion method is limited by the number of read / write ports on the vector register file (VRF), leading to reduced efficiency in data transfer to function units (FUs), thus impacting overall computational performance. Traditional vector processors rely on vector register files for data, but due to the limited number of read / write ports, data access bandwidth becomes a bottleneck when performing matrix operations. Therefore, effectively addressing this issue within the existing architecture has become a crucial topic in the development of vector processors. Summary of the Invention
[0003] To address the aforementioned problems, this disclosure proposes a vector processing circuit and a vector processing method.
[0004] This disclosure proposes a vector processing circuit comprising a one-dimensional vector register, a two-dimensional register, and an arithmetic circuit. The one-dimensional vector register stores first data. The two-dimensional register stores second data, wherein the size of the second data may be greater than or equal to the size of the first data. The arithmetic circuit is electrically connected to the one-dimensional vector register and the two-dimensional register, and is used to perform a first matrix multiplication operation on the first data and the second data. After performing the first matrix multiplication operation, the one-dimensional vector register stores third data to replace the first data, and the arithmetic circuit performs a second matrix multiplication operation on the third data and the second data, wherein the first data is different from the third data.
[0005] In one embodiment disclosed herein, the first data belongs to the first row of the first matrix, and the second data belongs to multiple columns of the second matrix.
[0006] In one embodiment disclosed herein, the aforementioned third data belongs to the second row of the first matrix, which is different from the first row.
[0007] In one embodiment disclosed herein, the number of the first row is equal to 1, and the first row belongs to the last row of the first matrix.
[0008] In one embodiment disclosed herein, the number of the first rows is greater than or equal to 2, and the first rows do not include the last row of the first matrix.
[0009] In one embodiment disclosed herein, the aforementioned two-dimensional temporary register includes multiple first two-dimensional temporary registers and multiple second two-dimensional temporary registers, and the second data includes first sub-data and second sub-data. The first sub-data is stored in the first two-dimensional temporary register, and the second sub-data is stored in the second two-dimensional temporary register. The arithmetic circuits perform first matrix multiplication operations and second matrix multiplication operations on the first sub-data and the second sub-data in an alternating manner.
[0010] In one embodiment of this disclosure, the number of the first two-dimensional registers is the same as the length multiplier, which is used to combine multiple vectors into a virtual vector.
[0011] In one embodiment disclosed herein, the aforementioned one-dimensional vector register, two-dimensional register, and arithmetic circuit belong to a first core, which is used to transmit first data or second data to a second core.
[0012] In one embodiment disclosed herein, the aforementioned two-dimensional registers can be either schema registers or non-schematic registers. When designed as schema registers, these registers are visible to the compiler or programmer.
[0013] In one embodiment disclosed herein, the second data is stored in the two-dimensional temporary register for a longer period than the first data is stored in the vector temporary register.
[0014] From another perspective, embodiments of the present invention propose a vector processing method applicable to vector processing circuits. This vector processing method includes: loading first data into a one-dimensional vector register; loading second data into a two-dimensional register, wherein the size of the second data may be greater than or equal to the size of the first data; performing a first matrix multiplication operation on the first data and the second data through a vector processing circuit; and after performing the first matrix multiplication operation, loading third data into the one-dimensional vector register to replace the first data, and performing a second matrix multiplication operation on the third data and the second data through an arithmetic circuit, wherein the first data is different from the third data.
[0015] In one embodiment disclosed herein, the aforementioned two-dimensional temporary register includes multiple first two-dimensional temporary registers and multiple second two-dimensional temporary registers. The second data includes first sub-data and second sub-data, with the first sub-data stored in the first two-dimensional temporary register and the second sub-data stored in the second two-dimensional temporary register. The vector processing method further includes: performing a first matrix multiplication operation and a second matrix multiplication operation on the first sub-data and the second sub-data in an alternating manner using arithmetic circuits.
[0016] In one embodiment disclosed herein, the aforementioned one-dimensional vector register, two-dimensional register, and arithmetic circuit belong to the first core. The vector processing method further includes: transmitting first data or second data from the first core to the second core.
[0017] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0018] Figure 1 This is a block diagram of a processor according to one embodiment;
[0019] Figure 2 This is a schematic diagram illustrating virtual code performing matrix multiplication according to one embodiment;
[0020] Figure 3 This is a schematic diagram illustrating data for performing matrix multiplication according to one embodiment;
[0021] Figure 4 This is a schematic diagram illustrating data for performing matrix multiplication according to one embodiment;
[0022] Figures 5 to 7 A schematic diagram of matrix multiplication is shown when the length multiplier is set to 1;
[0023] Figure 8 and Figure 9 A schematic diagram of matrix multiplication is shown when the length multiplier is set to 2;
[0024] Figure 10 This diagram illustrates vector multiplication by a matrix when the length multiplier is set to 1.
[0025] Figure 11 This diagram illustrates vector multiplication by a matrix when the length multiplier is set to 8.
[0026] Figure 12 This is a schematic diagram illustrating multiple cores according to one embodiment;
[0027] Figure 13 This is a flowchart illustrating a vector processing method according to an embodiment. Detailed Implementation
[0028] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered identical or similar when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of the systems and methods described in the patent claims of the present invention.
[0029] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.
[0030] Figure 1 This is a block diagram of a processor according to one embodiment. Please refer to... Figure 1 The processor 100 includes a vector instruction queue 110, an issue unit 112, a vector temporary register 120, a forwarding and chaining unit 130, a vector processing circuit 140, and a vector load / store control unit 150. The processor 100 can be a central processing unit, a graphics processing unit, a deep-learning processing unit (DPU), a neural network processing unit (NPU), a tensor processing unit (TPU), etc., and this invention is not limited thereto.
[0031] Vector instruction queue 110 is used to store vector instructions. Transmitting unit 112 is electrically connected to vector instruction queue 110 and is used to decode vector instructions from vector instruction queue 110. For simplicity, ... Figure 1 Only one transmitting unit 112 is shown, but this disclosure does not limit the number of transmitting units. Vector register file 120 contains multiple vector registers, some of which are one-dimensional and some are two-dimensional. In this architecture, the vector registers in vector register file 120 serve as the basic units for processing data. Feedforward and linking units 130 are electrically connected to vector register file 120 to implement feedforward and linking. Feedforward allows the output of the arithmetic circuit to be directly used as the input to the next instruction without having to write the result back to the register and then read it. Linking allows multiple functional units to perform collaborative operations.
[0032] The vector processing circuit 140 is electrically connected to the feedforward and link unit 130. The vector processing circuit 140 includes one-dimensional vector registers vs1[0]~vs1[3], two-dimensional registers vs2[0]~vs2[3], vs4[0]~vs4[3], vector registers vd0~vd3, and arithmetic circuit 142. Figure 1This is merely an example; this disclosure does not limit the number or naming of various registers. One-dimensional vector registers vs1[0]~vs1[3] consist of multiple vector registers arranged in a one-dimensional structure and only support row-wise access operations. Two-dimensional registers vs2[0]~vs2[3], vs4[0]~vs4[3] are formed by combining multiple vector registers into a two-dimensional structure. Depending on the data format, they may only support row-wise access (e.g., if there is instruction or hardware support for transpose operation), or they may support both row-wise and column-wise access operations.
[0033] The arithmetic circuit 142 is electrically connected to one-dimensional vector registers vs1[0]~vs1[3], two-dimensional registers vs2[0]~vs2[3], vs4[0]~vs4[3], and vector registers vd0~vd3 to perform matrix multiplication operations. Figure 1 The arithmetic circuit 142 includes a multiplexer, a multiplication unit, an addition unit, a buffer, etc., but these diagrams are only illustrative, and the present invention does not limit the use of those units to implement matrix multiplication operations. In some embodiments, the arithmetic circuit 142 is also referred to as a functional unit, but this disclosure does not limit the naming of the arithmetic circuit 142. The vector loading and storage control unit 150 is electrically connected to the feedforward and linking unit 130 and the vector temporary register 120 for loading data from memory or storing data in memory.
[0034] In some embodiments, the operation to be performed is the multiplication of two matrices, referred to as the first matrix (or matrix A) and the second matrix (or matrix B). The data stored in the one-dimensional vector registers vs1[0]~vs1[3] (referred to as the first data) belongs to the first matrix, while the data stored in the two-dimensional registers vs2[0]~vs2[3] and vs4[0]~vs4[3] (referred to as the second data) belongs to the second matrix. The size of the second data is greater than or equal to the size of the first data. In particular, the time that the second data is stored in the two-dimensional registers vs2[0]~vs2[3] and vs4[0]~vs4[3] is greater than the time that the first data is stored in the vector registers vs1[0]~vs1[3]. For example, depending on the computing power, the first data may be stored in the vector registers vs1[0]~vs1[3] for one or more clock cycles, while the second data may be stored in the two-dimensional registers vs2[0]~vs2[3] and vs4[0]~vs4[3] for a longer period of time (e.g., 10 clock cycles). After the arithmetic circuit 142 performs matrix multiplication on the first data and the second data, the second data will remain in the two-dimensional register, but the first data will be replaced (e.g., replaced with the third data). After the first data is replaced with the third data, the arithmetic circuit 142 will perform matrix multiplication on the third data and the second data. The third data is different from the first data. When the intermediate results of the matrix multiplication operation are used by subsequent or other instructions, these intermediate results may be transferred to the vector register file 120; otherwise, the intermediate results of the matrix multiplication operation will not be transferred to the vector register file 120. In other words, the entire matrix multiplication operation can be completed in the vector processing circuit 140. Between two matrix multiplication operations, the second data will remain in the two-dimensional register. In this way, the second data can be reused without frequent reading and writing from the vector register file 120, which can reduce data exchange and latency.
[0035] Figure 2 This is a schematic diagram illustrating virtual code for performing matrix multiplication operations according to one embodiment. Figure 3 and Figure 4 This is a schematic diagram illustrating the data used in performing matrix multiplication, according to one embodiment. Please refer to... Figures 1 to 3 . Figure 2The virtual code 200 has 10 lines. In the first line, the length multiplier is set. This length multiplier is used to combine multiple vectors into a virtual vector. In this embodiment, the length multiplier is 4. Therefore, 4 vector registers vs1[0]~vs1[3] form a vector register vs1, 4 two-dimensional registers vs2[0]~vs2[3] form a two-dimensional register vs2, and 4 two-dimensional registers vs4[0]~vs4[3] form a two-dimensional register vs4.
[0036] In the second row of virtual code 200, the vector load storage control unit 150 loads data from memory into the two-dimensional temporary register vs2. The data stored in the two-dimensional temporary register vs2 belongs to the first part of matrix B, which corresponds to multiple columns of matrix B. In the third row of virtual code 200, the vector load storage control unit 150 loads data from memory into the two-dimensional temporary register vs4. The data stored in the two-dimensional temporary register vs4 belongs to the second part of matrix B, which corresponds to multiple columns of matrix B, and the second part is different from the first part mentioned above. In other words, the second data mentioned above belongs to multiple columns of matrix B, and the second data includes first sub-data and second sub-data corresponding to different columns. For example, the first sub-data corresponds to columns 1-8, and the second sub-data corresponds to columns 9-16, where the first sub-data is stored in the two-dimensional temporary register vs2, and the second sub-data is stored in the two-dimensional temporary register vs4.
[0037] In line 4 of virtual code 200, an inner loop is entered. This inner loop is used to process the first and second parts of matrix B. In an outer loop, the data in the two-dimensional temporary registers vs2 and vs4 are replaced with the other parts of matrix B.
[0038] In line 5 of virtual code 200, the vector load storage control unit 150 loads first data from memory into vector register vs1. The first data stored in vector register vs1 belongs to the first part of matrix A, which contains at least one row of matrix A. Figure 3 In the embodiment, the vector register vs1 stores two rows of data (shown in gray), but in other embodiments it may store more or fewer rows of data.
[0039] In line 6 of virtual code 200, the arithmetic circuit 142 performs matrix multiplication on the data stored in vector register vs1 and the data stored in two-dimensional register vs2, and stores the result in vector register vd0 (represented in gray). In line 7 of virtual code 200, the arithmetic circuit 142 performs matrix multiplication on the data stored in vector register vs1 and the data stored in two-dimensional register vs4, and stores the result in vector register vd1 (represented in gray).
[0040] Please refer to Figure 2 and Figure 4 In line 8 of virtual code 200, the vector load storage control unit 150 loads the third data from memory into the vector temporary register vs1. This third data belongs to the second part of matrix A, which stores two rows of data (shown in gray), and the third data and Figure 3 The first data in the array belongs to a different row. For example, the first data belongs to rows 1-2, and the third data belongs to rows 3-4.
[0041] In line 9 of virtual code 200, arithmetic circuit 142 performs matrix multiplication on the data stored in vector register vs1 and the data stored in two-dimensional register vs2, and stores the result in vector register vd2 (represented in gray). In line 10 of virtual code 200, arithmetic circuit 142 performs matrix multiplication on the data stored in vector register vs1 and the data stored in two-dimensional register vs4, and stores the result in vector register vd3 (represented in gray). Next, the data in vector register vs1 can be replaced (e.g., replaced with the next two rows of matrix A), and the above operations can be repeated.
[0042] exist Figures 2 to 4 In this embodiment, the arithmetic circuit 142 performs multiple matrix multiplication operations on the first sub-data in the two-dimensional register vs2 and the second sub-data in the two-dimensional register vs4 in an alternating manner. In other words, the two-dimensional registers are divided into two groups, which correspond to different columns of matrix B, and the number of two-dimensional registers in each group is the same as the length multiplier (e.g., 4). In some hardware configurations, this configuration has a higher computational density than dividing all the two-dimensional registers into one group.
[0043] exist Figure 3 and Figure 4 In this embodiment, the length multiplier is set to 4, but in other embodiments it can also be set to 1, 2, 8, or other values. For example, Figure 5 and Figure 6 This diagram illustrates matrix multiplication when the length multiplier is set to 1. Figure 5 In the table, vector register vs1[0] stores the first data, and two-dimensional registers vs2[0] and vs4[0] store the second data. After performing matrix multiplication on the first and second data, the first data is replaced with the third data, such as... Figure 6 Therefore, the second data remains in the two-dimensional temporary registers vs2[0] and vs4[0], while the third data will be multiplied by the second data. In other words, the second data can be reused, which reduces data exchange.
[0044] In other embodiments, in Figure 5 After the matrix multiplication operation, the data in the vector temporary register vs1[0] can be replaced with the subsequent data in the same row of matrix A. For example Figure 7 As shown, at this time, the vector register vs1[0] stores the data in columns 9-16 and rows 1-2. In this case, matrix multiplication is performed on the data in the two-dimensional registers vs2[1] and vs4[1]. The result of the matrix multiplication operation can be stored in the vector registers vd2 and vd3, or it can be accumulated to... Figure 5 The vector temporary registers vd0 and vd1 are used to add the results of the two matrix multiplication operations. After the data of the first and second rows of matrix A is processed, the data of the third and fourth rows will be loaded into the vector temporary register vs1[0]. At this time, the data in the two-dimensional temporary registers vs2[0] and vs4[0] can be reused.
[0045] Figure 8 and Figure 9 This diagram illustrates matrix multiplication when the length multiplier is set to 2. Figure 8 In the first data, vector registers vs1[0] and vs1[1] store the first data, and two-dimensional registers vs2[0], vs2[1], vs4[0], and vs4[1] store the second data. After performing matrix multiplication on the first and second data, the first data is replaced with the third data, such as... Figure 9 The second data remains in the two-dimensional temporary registers vs2[0], vs2[1], vs4[0], vs4[1], while the third data will be multiplied by the second data.
[0046] The "matrix multiplication operation" mentioned in this disclosure can include the multiplication of two matrices, or the multiplication of a vector and a matrix. For example, when processing rows other than the last row in matrix A, the vector register vs1 can store data from multiple rows; when processing the last row of matrix A, the vector register vs1 can store data from a single row (i.e., the last row), or the vector register vs1 can store data from multiple rows but only perform matrix multiplication on the last row. Specifically, in the above embodiment, the data stored in the vector register vs1 corresponds to two rows of matrix A, and matrix A has m rows, where m is a positive integer. When the positive integer m is even, the vector register vs1 stores two rows of data each time, which is just enough to process the last row of matrix A. However, when the positive integer m is odd, the vector register vs1[0] can also be set to store only the last row of matrix A. Figure 10 This diagram illustrates vector multiplication by a matrix when the length multiplier is set to 1. Please refer to... Figure 10 The first data stored in the vector temporary register vs1[0] belongs to the last row of matrix A. Figure 11This diagram illustrates vector multiplication by a matrix when the length multiplier is set to 8. Please refer to... Figure 11 The data stored in the vector temporary registers vs1[0]~vs1[7] belong to the last row of matrix A.
[0047] exist Figure 11 The length multiplier is set to 8, so eight two-dimensional registers vs1[0]~vs1[7] form a virtual two-dimensional register. In such an embodiment, all two-dimensional registers are grouped together, and this group of two-dimensional registers corresponds to the same multiple columns in matrix B. However, as Figures 3 to 10 In one embodiment, these two-dimensional registers can also be divided into two groups. In other embodiments, all the two-dimensional registers can also be divided into 3, 4 or more groups, with each group of two-dimensional registers corresponding to different columns in matrix B. For example, the first group corresponds to columns 1-8, the second group corresponds to columns 9-16, the third group corresponds to columns 17-24, and so on.
[0048] The above embodiment is a vertical scaling up within a core, but the above techniques can also be used for horizontal scaling out. Figure 12 This is a schematic diagram illustrating multiple cores according to one embodiment. Figure 12Multiple cores 1201 to 1204 are shown. After one core obtains data, it can transfer the data to other cores to avoid other cores repeatedly loading data from memory. For example, the vector registers vs1[0] to vs1[3] of core 1201 are used to store the data in rows 1-2 of matrix A. After receiving the data, it can be transferred to the vector registers vs1[0] to vs1[3] in core 1202. The vector registers vs1[0] to vs1[3] of core 1203 are used to store the data in rows 3-4 of matrix A. After receiving the data, it can be transferred to the vector registers vs1[0] to vs1[3] in core 1204. On the other hand, the two-dimensional registers vs2[0] to vs2[3] of core 1201 are used to store the data in columns 1-8 of matrix B. The data can be transferred to the two-dimensional registers vs2[0] to vs2[3] of core 1203. The two-dimensional registers vs4[0]~vs4[3] of core 1201 are used to store the data in columns 9-16 of matrix B. This data can be transferred to the two-dimensional registers vs4[0]~vs4[3] of core 1203. The two-dimensional registers vs2[0]~vs2[3] of core 1202 are used to store the data in columns 17-24 of matrix B. This data can be transferred to the two-dimensional registers vs2[0]~vs2[3] of core 1204. The two-dimensional registers vs4[0]~vs4[3] of core 1202 are used to store the data in columns 25-32 of matrix B. This data can be transferred to the two-dimensional registers vs4[0]~vs4[3] of core 1204. In this way, cores 1201~1204 can process in parallel, and simultaneously process the multiplication of matrix A and matrix B.
[0049] From another perspective, multiple cores 1201~1204 can be divided into multiple rows and multiple columns. The data stored in the vector registers vs1[0]~vs1[3] in a certain core can be transferred to the vector registers vs1[0]~vs1[3] in other cores in the same row. The data stored in the two-dimensional registers vs2[0]~vs2[3], vs4[0]~vs4[3] in a certain core can be transferred to the two-dimensional registers vs2[0]~vs2[3], vs4[0]~vs4[3] in other cores in the same column.
[0050] Please refer to Figure 2 and Figure 3In this embodiment, the two-dimensional registers vs2 and vs4 can be accessed by the code. However, in some embodiments, the two-dimensional registers vs2 and vs4 can be designed so that they cannot be accessed by the code; such registers are called shadow registers or non-architecture registers. When using a non-architecture register design, the compiler needs to know about the existence of the two-dimensional registers vs2 and vs4. For example, the programmer... Figure 2 The virtual code 200 may use schema registers with other names instead of vs2 and vs4. Data in these schema registers will be mapped to registers vs2 and vs4. Therefore, matrix multiplication will still use the two-dimensional registers vs2 and vs4. From another perspective, when the two-dimensional registers vs2 and vs4 are schema registers, the first instruction can access them; when they are non-schematic registers, the second instruction, in conjunction with the compiler, can access them. The first instruction differs from the second instruction; the first instruction specifies the two-dimensional registers vs2 and vs4, but the second instruction does not.
[0051] When the two-dimensional temporary registers vs2 and vs4 are non-architectural temporary registers, and as... Figures 3 to 10 When the schema registers are divided into multiple groups as in the previous implementation, the size and number of these groups will be mapped to vector register files. For example, one schema register is mapped to the first group, another schema register is mapped to the second group, and so on. When the two-dimensional registers vs2 and vs4 are schema registers and are divided into multiple groups, the size and number of these groups will be determined based on implementation factors (such as cost and coding space).
[0052] Figure 13 This is a flowchart illustrating a vector processing method according to an embodiment. Please refer to... Figure 13 This vector processing method is suitable for Figure 1 The processor performs the following steps: In step 1301, first data is loaded into a vector register. In step 1302, second data is loaded into multiple two-dimensional registers, wherein the size of the second data is greater than or equal to the size of the first data. In step 1303, a first matrix multiplication operation is performed on the first data and the second data by a vector processing circuit. In step 1304, after performing the first matrix multiplication operation, third data is loaded into the vector register to replace the first data, and a second matrix multiplication operation is performed on the third data and the second data by an arithmetic circuit, wherein the first data is different from the third data. Figure 13 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 13Each step can be implemented as multiple codes or circuits, but this invention is not limited thereto. Furthermore, Figure 13 The method can be used in conjunction with the above embodiments or alone; in other words, Figure 13 Other steps can also be added between the various steps.
[0053] In the vector processing circuit and vector processing method described above, the data stored in the two-dimensional temporary register can be reused, thereby reducing data exchange and lowering the read / write port requirements of the vector temporary register file.
[0054] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A vector processing circuit, characterized in that... The vector processing circuit, located in the processor, includes: A vector temporary register is used to store the first data; Multiple two-dimensional registers are used to store second data, wherein the size of the second data is greater than or equal to the size of the first data; and The arithmetic circuit, electrically connected to the vector register and the plurality of two-dimensional registers, is used to perform a first matrix multiplication operation on the first data and the second data. After performing the first matrix multiplication operation, the vector register is used to store third data to replace the first data, and the arithmetic circuit is used to perform a second matrix multiplication operation on the third data and the second data, wherein the first data is different from the third data.
2. The vector processing circuit according to claim 1, characterized in that... The first data belongs to the first row of the first matrix, and the second data belongs to multiple columns of the second matrix.
3. The vector processing circuit according to claim 2, characterized in that... The third data belongs to the second row of the first matrix, and the second row is different from the first row.
4. The vector processing circuit according to claim 2, characterized in that... The first row has a quantity of 1, and the first row belongs to the last row of the first matrix.
5. The vector processing circuit according to claim 2, characterized in that... The number of first rows is greater than or equal to 2, and the plurality of first rows does not include the last row of the first matrix.
6. The vector processing circuit according to claim 2, characterized in that... The plurality of two-dimensional registers include a plurality of first two-dimensional registers and a plurality of second two-dimensional registers. The second data includes a first sub-data and a second sub-data, wherein the first sub-data is stored in the plurality of first two-dimensional registers and the second sub-data is stored in the plurality of second two-dimensional registers. The arithmetic circuits perform the first matrix multiplication operation and the second matrix multiplication operation on the first sub-data and the second sub-data in an alternating manner. The arithmetic circuits perform the second matrix multiplication operation on the first sub-data and the second sub-data in an alternating manner.
7. The vector processing circuit according to claim 6, characterized in that... The number of the plurality of first two-dimensional registers is the same as the length multiplier, which is used to combine the plurality of vectors into a virtual vector.
8. The vector processing circuit according to claim 1, characterized in that... The vector register, the plurality of two-dimensional registers, and the arithmetic circuit belong to the first core, which is used to transmit the first data or the second data to the second core.
9. The vector processing circuit according to claim 1, characterized in that... The multiple two-dimensional temporary registers mentioned therein are non-architectural temporary registers.
10. The vector processing circuit according to claim 1, characterized in that... The second data is stored in the plurality of two-dimensional registers for a longer period than the first data is stored in the vector register.
11. A vector processing method, characterized in that... Applicable to vector processing circuits, the vector processing method includes: Load the first data into the vector register; The second data is loaded into multiple two-dimensional temporary registers, wherein the size of the second data is greater than or equal to the size of the first data. The vector processing circuit performs a first matrix multiplication operation on the first data and the second data; and After performing the first matrix multiplication operation, the third data is loaded into the vector register to replace the first data, and the second matrix multiplication operation is performed on the third data and the second data through the arithmetic circuit, wherein the first data is different from the third data.
12. The vector processing method according to claim 11, characterized in that... The first data belongs to the first row of the first matrix, and the second data belongs to multiple columns of the second matrix.
13. The vector processing method according to claim 12, characterized in that... The third data belongs to the second row of the first matrix, and the second row is different from the first row.
14. The vector processing method according to claim 12, characterized in that... The first row has a quantity of 1, and the first row belongs to the last row of the first matrix.
15. The vector processing method according to claim 12, characterized in that... The number of first rows is greater than or equal to 2, and the plurality of first rows does not include the last row of the first matrix.
16. The vector processing method according to claim 12, characterized in that... The plurality of two-dimensional registers include a plurality of first two-dimensional registers and a plurality of second two-dimensional registers. The second data includes first sub-data and second sub-data. The first sub-data is stored in the plurality of first two-dimensional registers, and the second sub-data is stored in the plurality of second two-dimensional registers. The vector processing method further includes: The first matrix multiplication operation and the second matrix multiplication operation are performed alternately on the first sub-data and the second sub-data by the arithmetic circuit; and The second matrix multiplication operation is performed on the first sub-data and the second sub-data in an alternating manner through the arithmetic circuit.
17. The vector processing method according to claim 16, characterized in that... The number of the plurality of first two-dimensional registers is the same as the length multiplier, which is used to combine the plurality of vectors into a virtual vector.
18. The vector processing method according to claim 11, characterized in that... The vector temporary register, the plurality of two-dimensional temporary registers, and the arithmetic circuit belong to the first core. The vector processing method further includes: The first core transmits either the first data or the second data to the second core.
19. The vector processing method according to claim 11, characterized in that... The multiple two-dimensional temporary registers mentioned therein are non-architectural temporary registers.
20. The vector processing method according to claim 11, characterized in that... The second data is stored in the plurality of two-dimensional registers for a longer period than the first data is stored in the vector register.