Average measurement circuit of periodic irregular voltage and switching power supply

Abstract

The application relates to the technical field of electronic measurement and analog signal processing, and particularly discloses a periodic irregular voltage average value measurement circuit and a switching power supply, which comprises a first signal channel, a second signal channel, a frequency comparison counting module and a digital-to-analog conversion module; the first signal channel processes a to-be-measured periodic irregular input voltage to obtain a first oscillation signal; the second signal channel processes an adjustable direct current voltage to obtain a second oscillation signal; the frequency comparison counting module determines an adjustment signal of the adjustable direct current voltage according to a frequency comparison result of the first oscillation signal and the second oscillation signal; the digital-to-analog conversion module outputs a corresponding adjustable direct current voltage according to the adjustment signal, and when the loop is locked, the output adjustable direct current voltage represents the average value of the to-be-measured periodic irregular input voltage. The periodic irregular voltage average value measurement circuit provided by the application has a simple structure, does not need complex timing and can directly output a high-precision analog average voltage.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement and analog signal processing technology, and in particular to an average value measurement circuit for periodic irregular voltages and a switching power supply. Background Technology

[0002] In industrial automation, power electronics, and sensor signal processing, it is often necessary to measure the true average voltage of periodic irregular waveforms such as PWM waveforms, inverter output voltages, or sensor outputs. Traditional average value measurement schemes are mainly divided into two categories: (1) Analog low-pass filtering or synchronous integration method: ripple is filtered out through RC networks or integration circuits. However, low-pass filtering has a contradiction between response speed and ripple suppression (a large time constant results in a slow response, and a small time constant results in a large ripple); synchronous integration requires strict timing control, and the analog integration capacitor has leakage current, resulting in poor long-term stability. (2) Digital sampling and microprocessor operation: the signal is sampled by an ADC and then sent to an MCU / DSP for window averaging calculation. Although this method has high accuracy, the system is complex, and the ADC sampling rate needs to be much higher than the signal frequency, resulting in high power consumption and high cost. It is also ineffective in high-frequency or strong common-mode interference scenarios.

[0003] Therefore, how to provide a measurement scheme with a simple circuit structure, no need for complex timing, and the ability to directly output high-precision analog average voltage has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides an average value measurement circuit and switching power supply for periodic irregular voltages, solving the technical problem in related technologies that it is difficult to simultaneously meet the requirements of fast response, low cost, and high stability in average value measurement.

[0005] As a first aspect of the present invention, an average value measurement circuit for periodic irregular voltage is provided, characterized in that it includes: a first signal channel, a second signal channel, a frequency comparison and counting module, and a digital-to-analog conversion module, wherein the first signal channel and the second signal channel are both connected to the frequency comparison and counting module, the frequency comparison and counting module is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is also connected to the second signal channel;

[0006] The first signal channel is used to process the periodic irregular input voltage to be measured to obtain a first oscillation signal whose instantaneous frequency is proportional to the instantaneous value of the periodic irregular input voltage to be measured.

[0007] The second signal channel is used to process the adjustable DC voltage to obtain a second oscillation signal whose frequency is proportional to the adjustable DC voltage;

[0008] The frequency comparison counting module is used to determine an adjustment signal for the adjustable DC voltage based on the frequency comparison result between the first oscillation signal and the second oscillation signal. The adjustment signal is used to adjust the adjustable DC voltage so that the frequency of the second oscillation signal approaches the average frequency of the first oscillation signal until the loop is locked.

[0009] The digital-to-analog converter module is used to output the corresponding adjustable DC voltage according to the adjustment signal, and when the loop is locked, the adjustable DC voltage output by the digital-to-analog converter module is used to characterize the average value of the periodic irregular input voltage to be measured.

[0010] Furthermore, the first signal channel includes a first voltage-to-current conversion circuit and a first oscillation circuit. The input terminal of the first voltage-to-current conversion circuit is the input terminal of the first signal channel, the output terminal of the first voltage-to-current conversion circuit is connected to the input terminal of the first oscillation circuit, and the output terminal of the first oscillation circuit is the output terminal of the first signal channel.

[0011] The first voltage-to-current conversion circuit is used to convert the periodic irregular input voltage to be measured into a transient first charging current in a proportional manner;

[0012] The first oscillation circuit is used to charge and discharge under the drive of the first charging current to generate the first oscillation signal.

[0013] Furthermore, the first voltage-to-current conversion circuit includes a first resistor, a first comparator, a first N-type MOSFET, a first P-type MOSFET, and a second P-type MOSFET.

[0014] The non-inverting input terminal of the first comparator is used to input the periodic irregular input voltage to be measured. The inverting input terminal of the first comparator is connected to one end of the first resistor, the other end of the first resistor is connected to signal ground, and the output terminal of the first comparator is connected to the gate terminal of the first N-type MOS transistor.

[0015] The source terminal of the first N-type MOSFET is connected to one end of the first resistor, and the drain terminal of the first N-type MOSFET is connected to the source terminal of the first P-type MOSFET.

[0016] The drain terminal of the first P-type MOSFET is connected to the drain terminal of the second P-type MOSFET, and the gate terminal of the first P-type MOSFET is connected to the gate terminal of the second P-type MOSFET.

[0017] The source terminal of the second P-type MOS transistor is the output terminal of the first voltage-to-current conversion circuit, used to output the first charging current, wherein the first charging current is the ratio of the periodic irregular input voltage to be measured to the resistance value of the first resistor;

[0018] The first oscillation circuit includes a first capacitor, a second comparator, a third N-type MOSFET, a first inverter, and a second inverter.

[0019] One end of the first capacitor is connected to the output terminal of the first voltage-to-current conversion circuit, and the other end of the first capacitor is connected to the signal ground.

[0020] The non-inverting input of the second comparator is connected to the output of the first voltage-to-current conversion circuit. The inverting input of the second comparator is used to input a preset reference voltage. The output of the second comparator is connected to the input of the first inverter. The output of the first inverter is the output of the first oscillation circuit. The output of the first oscillation circuit is used to output the first oscillation signal.

[0021] The source terminal of the third N-type MOS transistor is connected to the signal ground, the drain terminal of the third N-type MOS transistor is connected to one end of the first capacitor, the gate terminal of the third N-type MOS transistor is connected to the output terminal of the second inverter, and the input terminal of the second inverter is connected to the output terminal of the first inverter.

[0022] Furthermore, the second signal channel includes a second voltage-to-current conversion circuit and a second oscillation circuit. The input terminal of the second voltage-to-current conversion circuit is the input terminal of the second signal channel, the output terminal of the second voltage-to-current conversion circuit is connected to the input terminal of the second oscillation circuit, and the output terminal of the second oscillation circuit is the output terminal of the second signal channel.

[0023] The second voltage-to-current conversion circuit is used to convert the adjustable DC voltage into a steady-state second charging current;

[0024] The second oscillation circuit is used to generate the second oscillation signal under the drive of the second charging current.

[0025] Furthermore, the second voltage-to-current conversion circuit includes a second resistor, a third comparator, a second N-type MOSFET, a third P-type MOSFET, and a fourth P-type MOSFET.

[0026] The non-inverting input of the third comparator is used to input the adjustable DC voltage. The inverting input of the third comparator is connected to one end of the second resistor, the other end of the second resistor is connected to signal ground, and the output of the third comparator is connected to the gate of the second N-type MOS transistor.

[0027] The source terminal of the second N-type MOSFET is connected to one end of the second resistor, and the drain terminal of the second N-type MOSFET is connected to the source terminal of the third P-type MOSFET.

[0028] The drain terminal of the third P-type MOS transistor is connected to the drain terminal of the fourth P-type MOS transistor, and the gate terminal of the third P-type MOS transistor is connected to the gate terminal of the fourth P-type MOS transistor.

[0029] The source terminal of the fourth P-type MOS transistor is the output terminal of the second voltage-to-current conversion circuit, used to output the steady-state second charging current, wherein the second charging current is the ratio of the adjustable DC voltage to the resistance value of the second resistor;

[0030] The second oscillation circuit includes a second capacitor, a fourth comparator, a fourth N-type MOSFET, a third inverter, and a fourth inverter.

[0031] One end of the second capacitor is connected to the output terminal of the second voltage-to-current conversion circuit, and the other end of the second capacitor is connected to the signal ground;

[0032] The non-inverting input of the fourth comparator is connected to the output of the second voltage-to-current conversion circuit. The inverting input of the fourth comparator is used to input a preset reference voltage. The output of the fourth comparator is connected to the input of the third inverter. The output of the third inverter is the output of the second oscillation circuit. The output of the second oscillation circuit is used to output the second oscillation signal.

[0033] The source terminal of the fourth N-type MOS transistor is connected to the signal ground, the drain terminal of the fourth N-type MOS transistor is connected to one end of the second capacitor, the gate terminal of the fourth N-type MOS transistor is connected to the output terminal of the fourth inverter, and the input terminal of the fourth inverter is connected to the output terminal of the third inverter.

[0034] Furthermore, the frequency comparison and counting module includes a frequency discriminator circuit and a counter circuit. The input terminal of the frequency discriminator circuit is connected to the first signal channel and the second signal channel, respectively. The output terminal of the frequency discriminator circuit is connected to the input terminal of the counter circuit. The output terminal of the counter circuit is the output terminal of the frequency comparison and counting module.

[0035] The frequency discriminator circuit is used to compare the frequency of the first oscillation signal and the second oscillation signal, and outputs an addition / subtraction control signal and a counting clock signal according to the frequency comparison result;

[0036] The counter circuit is used to perform increment or decrement counting according to the increment / decrement control signal and the counting clock signal, and output the counting result.

[0037] Furthermore, the frequency discriminator circuit includes a first frequency discriminator branch, a second frequency discriminator branch, an OR gate, and an SR latch. The output of the first frequency discriminator branch is connected to the first input of the OR gate, the output of the second frequency discriminator branch is connected to the second input of the OR gate, and the output of the OR gate is used to output a counting clock signal.

[0038] The output of the first frequency discriminator branch is connected to the S terminal of the SR latch, the output of the second frequency discriminator branch is connected to the R terminal of the SR latch, the main output of the SR latch is used to output a status flag signal, and the inverted output of the SR latch is used to output the inverted result of the status flag signal, wherein the status flag signal and the inverted result of the status flag signal are both used as the addition / subtraction control signal.

[0039] Both the first frequency discrimination branch and the second frequency discrimination branch are used to compare the period of the first oscillation signal with the period of the second oscillation signal. When the period of the second oscillation signal is greater than the period of the first oscillation signal, the status flag signal output by the SR latch is high; when the period of the second oscillation signal is less than the period of the first oscillation signal, the status flag signal output by the SR latch is low.

[0040] Furthermore, both the first frequency discrimination branch and the second frequency discrimination branch include a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first D flip-flop, and a second D flip-flop;

[0041] The input terminal of the fifth inverter is connected to signal ground, the output terminal of the fifth inverter is connected to the data input terminal of the first D flip-flop, the output terminal of the first D flip-flop is connected to the data input terminal of the second D flip-flop, the clock terminal of the first D flip-flop is connected to the clock terminal of the second D flip-flop, and the output terminal of the second D flip-flop is the output terminal of the first frequency discriminator branch or the second frequency discriminator branch.

[0042] The output of the sixth inverter is connected to the asynchronous set terminal of the second D flip-flop; the input of the sixth inverter is connected to the output of the seventh inverter; the input of the seventh inverter is connected to the output of the eighth inverter; and the input of the eighth inverter is connected to the output of the second D flip-flop.

[0043] In the first frequency discrimination branch, the asynchronous set terminal of the first D flip-flop is used to input the second oscillation signal, and the clock terminals of the first D flip-flop and the second D flip-flop in the first frequency discrimination branch are used to input the first oscillation signal.

[0044] In the second frequency discrimination branch, the asynchronous set terminal of the first D flip-flop is used to input the first oscillation signal, and the clock terminals of the first D flip-flop and the second D flip-flop are used to input the second oscillation signal.

[0045] Furthermore, the counter circuit includes a three-bit up-down counter, and when the status flag signal is high, it performs up counting on each rising edge of the counting clock signal; when the status flag signal is low, it performs down counting on each rising edge of the counting clock signal.

[0046] As another aspect of the present invention, a switching power supply is provided, wherein the circuit for measuring the average value of the periodic irregular voltage described above is included.

[0047] The circuit for measuring the average value of periodic irregular voltage provided by this invention converts the periodic irregular input voltage to be measured and the internal adjustable DC voltage into frequency signals via a first signal channel and a second signal channel, respectively. These two frequency signals are then sent to a frequency comparison and counting module for frequency comparison and counting. This effectively avoids the contradiction between response speed and ripple suppression, the complexity of timing control, and the poor long-term stability caused by leakage current in the integrating capacitor, which are problems inherent in analog low-pass filtering or synchronous integration schemes. The frequency comparison and counting module determines an adjustment signal based on the frequency comparison result and controls the digital-to-analog converter module to output an adjustable DC voltage, achieving automatic convergence and locking of the second oscillation signal frequency to the average frequency of the first oscillation signal. This eliminates the need for ADC sampling and microprocessor computation, effectively reducing system complexity, power consumption, and cost. It is suitable for high-frequency or strong common-mode interference scenarios. After loop locking, it directly outputs the DC voltage corresponding to the average value of the periodic irregular input voltage to be measured, achieving the beneficial effects of simple circuit structure, no need for complex timing, low cost, high stability, and high measurement accuracy. Attached Figure Description

[0048] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0049] Figure 1 The block diagram of the circuit for measuring the average value of periodic irregular voltages provided by the present invention.

[0050] Figure 2 The specific structural block diagram of the circuit for measuring the average value of periodic irregular voltage provided by the present invention is shown.

[0051] Figure 3 The circuit schematic diagram of the first signal channel provided by the present invention.

[0052] Figure 4The circuit schematic diagram of the second signal channel provided by the present invention.

[0053] Figure 5 The circuit diagram of the frequency discriminator provided by the present invention.

[0054] Figure 6 The circuit diagram of the up / down counter provided by this invention.

[0055] Figure 7 The circuit diagram of the digital-to-analog conversion module provided by the present invention.

[0056] Figure 8 A schematic diagram of capacitor voltage and oscillator waveform provided for this invention.

[0057] Figure 9 The waveform diagram of the first oscillation signal f1(t), the second oscillation signal f2, and the output pulse OUT provided by the present invention. Detailed Implementation

[0058] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0059] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0060] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] This embodiment provides a circuit for measuring the average value of periodic irregular voltages. Figure 1 This is a structural block diagram of the average value measurement circuit 10 for periodic irregular voltages provided in an embodiment of the present invention, as shown below. Figure 1As shown, it includes: a first signal channel 100, a second signal channel 200, a frequency comparison and counting module 300, and a digital-to-analog converter module 400. The first signal channel 100 and the second signal channel 200 are both connected to the frequency comparison and counting module 300, which is connected to the digital-to-analog converter module 400. The digital-to-analog converter module 400 is also connected to the second signal channel 200.

[0062] The first signal channel 100 is used to process the periodic irregular input voltage Vin(t) to be measured, and obtain a first oscillation signal f1(t) whose instantaneous frequency is proportional to the instantaneous value of the periodic irregular input voltage Vin(t). Specifically, the first signal channel 100 performs voltage-frequency conversion processing on the periodic irregular input voltage Vin(t) to be measured, and the instantaneous frequency of the first oscillation signal f1(t) changes synchronously with the instantaneous value of Vin(t), thereby converting the voltage magnitude information into frequency information.

[0063] The second signal channel 200 is used to process the adjustable DC voltage Vdc to obtain a second oscillation signal f2 whose frequency is proportional to the adjustable DC voltage Vdc. Specifically, the second signal channel 200 performs voltage-to-frequency conversion processing on the adjustable DC voltage Vdc, and the frequency of the second oscillation signal f2 corresponds one-to-one with the magnitude of Vdc, thereby converting the information of the DC voltage magnitude into information of the frequency.

[0064] The frequency comparison and counting module 300 is used to determine the adjustment signal of the adjustable DC voltage Vdc based on the frequency comparison result of the first oscillation signal f1(t) and the second oscillation signal f2. The adjustment signal is used to adjust the adjustable DC voltage Vdc so that the frequency of the second oscillation signal f2 approaches the average frequency of the first oscillation signal f1(t) until the loop locks. Specifically, when the frequency of f2 is lower than the average frequency of f1(t), the adjustment signal indicates an increase in Vdc; when the frequency of f2 is higher than the average frequency of f1(t), the adjustment signal indicates a decrease in Vdc. Through continuous adjustment of Vdc by the adjustment signal, the frequency of f2 gradually converges to the average frequency of f1(t).

[0065] The analog-to-digital converter module 400 outputs an adjustable DC voltage Vdc according to the adjustment signal. When the loop is locked, the adjustable DC voltage Vdc output by the analog-to-digital converter module 400 is used to characterize the average value of the periodic irregular input voltage Vin(t) to be measured. Specifically, the analog-to-digital converter module 400 outputs a corresponding DC voltage Vdc according to the adjustment signal. Vdc is converted into a second oscillation signal f2 through the second signal channel 200 and then fed back to the frequency comparison and counting module 300 to participate in frequency comparison, forming a closed loop. When the loop is locked and the frequency of f2 is equal to the average frequency of f1(t), Vdc no longer changes. At this time, Vdc characterizes the average value of Vin(t).

[0066] In this embodiment of the invention, the operation of the measurement circuit is as follows: At the start of the measurement, the digital-to-analog converter module 400 outputs an initial adjustable DC voltage Vdc. The first signal channel 100 converts Vin(t) into a first oscillation signal f1(t), and the second signal channel 200 converts Vdc into a second oscillation signal f2. The frequency comparison and counting module 300 compares the frequency of f1(t) with that of f2 and determines the adjustment signal. When the frequency of f2 is less than the average frequency of f1(t), the adjustment signal increases Vdc, and the frequency of the second oscillation signal f2 increases accordingly. When the frequency of f2 is greater than the average frequency of f1(t), the adjustment signal decreases Vdc, and the frequency of the second oscillation signal f2 decreases accordingly. After repeated adjustments, the frequency of f2 gradually approaches the average frequency of f1(t), and finally the loop is locked. The DC voltage Vdc output by the digital-to-analog converter module 400 represents the average value of the periodic irregular input voltage Vin(t) to be measured.

[0067] Therefore, the average value measurement circuit for periodic irregular voltage provided by this invention converts the periodic irregular input voltage to be measured and the internal adjustable DC voltage into frequency signals through the first signal channel and the second signal channel, respectively. The two frequency signals are then sent to the frequency comparison and counting module for frequency comparison and counting. This effectively avoids the contradiction between response speed and ripple suppression, the complexity of timing control, and the poor long-term stability caused by leakage current in the integrating capacitor, which are problems inherent in analog low-pass filtering or synchronous integration schemes. The frequency comparison and counting module determines the adjustment signal based on the frequency comparison result and controls the digital-to-analog converter module to output the adjustable DC voltage, achieving automatic convergence and locking of the second oscillation signal frequency to the average frequency of the first oscillation signal. This eliminates the need for ADC sampling and microprocessor computation, effectively reducing system complexity, power consumption, and cost, and is suitable for high-frequency or strong common-mode interference scenarios. Thus, after loop locking, it directly outputs the DC voltage corresponding to the average value of the periodic irregular input voltage to be measured, achieving the beneficial effects of simple circuit structure, no need for complex timing, low cost, high stability, and high measurement accuracy.

[0068] In this embodiment of the invention, the specific implementation of the first signal channel 100 is as follows: Figure 2 This is a specific structural block diagram of the average value measurement circuit for periodic irregular voltage provided in an embodiment of the present invention, as shown below. Figure 2As shown, the first signal channel 100 includes a first voltage-to-current conversion circuit 110 and a first oscillation circuit 120. The input terminal of the first voltage-to-current conversion circuit 110 is the input terminal of the first signal channel 100, and the output terminal of the first voltage-to-current conversion circuit 110 is connected to the input terminal of the first oscillation circuit 120. The output terminal of the first oscillation circuit 120 is the output terminal of the first signal channel 100. The first voltage-to-current conversion circuit 110 is used to convert the periodic irregular input voltage Vin(t) to be measured into a transient first charging current I1(t) proportionally. The first oscillation circuit 120 is used to charge and discharge under the drive of the first charging current I1(t) to generate a first oscillation signal f1(t).

[0069] Specifically, such as Figure 3 As shown, the first voltage-to-current conversion circuit 110 includes a first resistor R1, a first comparator A1, a first N-type MOSFET N1, a first P-type MOSFET P1, and a second P-type MOSFET P2. The non-inverting input terminal of the first comparator A1 is used to input the periodic irregular input voltage Vin(t) to be measured. The inverting input terminal of the first comparator A1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to signal ground. The output terminal of the first comparator A1 is connected to the gate terminal of the first N-type MOSFET N1. The source terminal of the first N-type MOSFET N1 is connected to one end of the first resistor R1, and the drain terminal of the first N-type MOSFET N1 is connected to the source terminal of the first P-type MOSFET P1. The drain terminal of the first P-type MOSFET P1 is connected to the drain terminal of the second P-type MOSFET P2, and the gate terminal of the first P-type MOSFET P1 is connected to the gate terminal of the second P-type MOSFET P2. The source terminal of the second P-type MOSFET P2 is the output terminal of the first voltage-to-current conversion circuit 110, used to output the first charging current I1(t).

[0070] The working principle of the first voltage-to-current conversion circuit 110 is as follows: the first comparator A1, the first N-type MOSFET N1, and the first resistor R1 form a voltage-to-current conversion negative feedback loop. The first comparator A1 compares the periodic irregular input voltage Vin(t) to be measured with the voltage at one end of the first resistor R1. Its output drives the gate of the first N-type MOSFET N1. Through negative feedback, the source voltage of the first N-type MOSFET N1 (i.e., the voltage at one end of the first resistor R1) follows the periodic irregular input voltage Vin(t), thereby generating a current proportional to Vin(t) across the first resistor R1. This current is the ratio of Vin(t) to the resistance of the first resistor R1, i.e., I1(t) = Vin(t) / R1. This current flows through the first N-type MOSFET N1 into the first P-type MOSFET. The first P-type MOSFET P1 and the second P-type MOSFET P2 form a current mirror circuit, mirroring this current to the source of the second P-type MOSFET P2 to obtain the first charging current I1(t). Since the periodic irregular input voltage Vin(t) to be measured is a periodic irregular voltage, the first charging current I1(t) is a transient current that follows the instantaneous change of Vin(t).

[0071] The first oscillation circuit 120 includes a first capacitor C1, a second comparator A2, a third N-type MOSFET N3, a first inverter M1, and a second inverter M2. One end of the first capacitor C1 is connected to the output of the first voltage-to-current conversion circuit 110, and the other end of the first capacitor C1 is connected to signal ground. The non-inverting input of the second comparator A2 is connected to the output of the first voltage-to-current conversion circuit 110, and the inverting input of the second comparator A2 is used to input a preset reference voltage VREF. The output of the second comparator A2 is connected to the input of the first inverter M1, and the output of the first inverter M1 is the output of the first oscillation circuit 120, used to output the first oscillation signal f1(t). The source terminal of the third N-type MOSFET N3 is connected to signal ground, the drain terminal of the third N-type MOSFET N3 is connected to one end of the first capacitor C1, the gate terminal of the third N-type MOSFET N3 is connected to the output of the second inverter M2, and the input terminal of the second inverter M2 is connected to the output of the first inverter M1.

[0072] The working principle of the first oscillation circuit 120 is as follows: The first charging current I1(t) charges the first capacitor C1, and the voltage of the first capacitor C1 gradually increases. When the voltage of the first capacitor C1 is less than the preset reference voltage VREF, the second comparator A2 outputs a low level. After being inverted by the first inverter M1, the first oscillation signal f1(t) is at a high level. At this time, the output of the second inverter M2 outputs a low level, the third N-type MOSFET N3 is turned off, and the first charging current I1(t) continues to charge the first capacitor C1, and the voltage of the first capacitor C1 continues to rise. When the voltage of the first capacitor C1 is greater than the preset reference voltage VREF, the second comparator A2 outputs a high level, and the first oscillation signal f1(t) flips to a low level. At this time, the output of the second inverter M2 outputs a high level, the third N-type MOSFET N3 is turned on, and the first capacitor C1 quickly discharges to ground through the third N-type MOSFET N3, and the voltage of the first capacitor C1 drops rapidly. When the voltage of the first capacitor C1 drops below the preset reference voltage VREF, the first oscillation signal f1(t) flips to a high level again, the third N-type MOSFET N3 is turned off again, and the first charging current I1(t) charges the first capacitor C1 again. This cycle repeats, and the first oscillation circuit 120 generates the first oscillation signal f1(t).

[0073] The high-level duration of the first oscillation signal f1(t) corresponds to the charging time of the first capacitor C1, which is determined by the charging current (i.e., the first charging current I1(t)). The low-level duration of the first oscillation signal f1(t) corresponds to the discharging time of the first capacitor C1, which is determined by the discharging current. In this embodiment of the invention, the discharging current when the third N-type MOS transistor N3 is turned on is set to be much greater than the first charging current I1(t) and remains constant. Therefore, the high-level duration of the first oscillation signal f1(t) is much greater than the low-level duration. Since the first charging current I1(t) = Vin(t) / R1, the instantaneous frequency of the first oscillation signal f1(t) is proportional to the instantaneous value of the periodic irregular input voltage Vin(t) to be measured, satisfying f1(t) = Vin(t) / (R1×C1×VREF).

[0074] In this embodiment of the invention, the specific implementation of the second signal channel 200 is as follows: Figure 2As shown, the second signal channel 200 includes a second voltage-to-current conversion circuit 210 and a second oscillation circuit 220. The input terminal of the second voltage-to-current conversion circuit 210 is the input terminal of the second signal channel 200, the output terminal of the second voltage-to-current conversion circuit 210 is connected to the input terminal of the second oscillation circuit 220, and the output terminal of the second oscillation circuit 220 is the output terminal of the second signal channel 200. The second voltage-to-current conversion circuit 210 is used to convert the adjustable DC voltage Vdc into a steady-state second charging current I2. The second oscillation circuit 220 is used to generate a second oscillation signal f2 under the drive of the second charging current I2.

[0075] Specifically, such as Figure 4 As shown, the second voltage-to-current conversion circuit 210 includes a second resistor R2, a third comparator A3, a second N-type MOSFET N2, a third P-type MOSFET P3, and a fourth P-type MOSFET P4. The non-inverting input of the third comparator A3 is used to input an adjustable DC voltage Vdc. The inverting input of the third comparator A3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to signal ground. The output of the third comparator A3 is connected to the gate of the second N-type MOSFET N2. The source of the second N-type MOSFET N2 is connected to one end of the second resistor R2, and the drain of the second N-type MOSFET N2 is connected to the source of the third P-type MOSFET P3. The drain of the third P-type MOSFET P3 is connected to the drain of the fourth P-type MOSFET P4, and the gate of the third P-type MOSFET P3 is connected to the gate of the fourth P-type MOSFET P4. The source of the fourth P-type MOSFET P4 is the output of the second voltage-to-current conversion circuit 210, used to output a steady-state second charging current I2.

[0076] The working principle of the second voltage-to-current conversion circuit 210 is as follows: the third comparator A3, the second N-type MOSFET N2, and the second resistor R2 form a voltage-to-current conversion negative feedback loop, causing the voltage at one end of the second resistor R2 to follow the adjustable DC voltage Vdc, generating a current Vdc / R2 across the second resistor R2. This current flows through the second N-type MOSFET into the third P-type MOSFET P3, and is mirrored by the current mirror circuit formed by the third P-type MOSFET P3 and the fourth P-type MOSFET P4, resulting in the second charging current I2 = Vdc / R2. Since the adjustable DC voltage Vdc is at a DC level, the second charging current I2 is a constant steady-state current.

[0077] The second oscillation circuit 220 includes a second capacitor C2, a fourth comparator A4, a fourth N-type MOSFET N4, a third inverter M3, and a fourth inverter M4. One end of the second capacitor C2 is connected to the output of the second voltage-to-current conversion circuit 210, and the other end of the second capacitor C2 is connected to signal ground. The non-inverting input of the fourth comparator A4 is connected to the output of the second voltage-to-current conversion circuit 210, and the inverting input of the fourth comparator A4 is used to input a preset reference voltage VREF. The output of the fourth comparator A4 is connected to the input of the third inverter M3, and the output of the third inverter M3 is the output of the second oscillation circuit 220, used to output the second oscillation signal f2. The source terminal of the fourth N-type MOSFET N4 is connected to signal ground, the drain terminal of the fourth N-type MOSFET N4 is connected to one end of the second capacitor C2, the gate terminal of the fourth N-type MOSFET N4 is connected to the output of the fourth inverter M4, and the input terminal of the fourth inverter M4 is connected to the output of the third inverter M3.

[0078] The second oscillation circuit 220 works as follows: The second charging current I2 charges the second capacitor C2. When the voltage of the second capacitor C2 is less than the preset reference voltage VREF, the second oscillation signal f2 is at a high level, the fourth N-type MOSFET N4 is turned off, and the second charging current I2 continues to charge the second capacitor C2. When the voltage of the second capacitor C2 is greater than the preset reference voltage VREF, the second oscillation signal f2 is at a low level, the fourth N-type MOSFET N4 is turned on, and the second capacitor C2 discharges rapidly to ground through the fourth N-type MOSFET N4. This cycle repeats to generate the second oscillation signal f2. The frequency of the second oscillation signal f2 is proportional to the adjustable DC voltage Vdc, satisfying f2 = Vdc / (R2 × C2 × VREF).

[0079] In this embodiment of the invention, the third N-type MOS transistor N3 and the fourth N-type MOS transistor N4 have the same area, and their discharge currents are equal and constant. Therefore, the low-level duration of the first oscillation signal f1(t) is equal to the low-level duration of the second oscillation signal f2. Since the low-level durations of the two oscillation circuits are equal and much shorter than the high-level durations, the period difference between the first oscillation signal f1(t) and the second oscillation signal f2 mainly lies in the difference in the high-level duration, providing conditions for frequency comparison by the frequency discriminator circuit 310.

[0080] In embodiments of the present invention, such as Figure 2As shown, the frequency comparison and counting module 300 includes a frequency discriminator circuit 310 and a counter circuit 320. The input terminals of the frequency discriminator circuit 310 are connected to the first signal channel 100 and the second signal channel 200, respectively. The output terminal of the frequency discriminator circuit 310 is connected to the input terminal of the counter circuit 320, and the output terminal of the counter circuit 320 is the output terminal of the frequency comparison and counting module 300. The frequency discriminator circuit 310 is used to compare the frequency difference between the first oscillation signal f1(t) and the second oscillation signal f2, and outputs an increment / decrement control signal and a counting clock signal according to the frequency comparison result. The counter circuit 320 is used to perform increment or decrement counting according to the increment / decrement control signal and the counting clock signal, and outputs the counting result.

[0081] Figure 5 This is a schematic diagram of the circuit structure of the frequency discriminator circuit provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the frequency discriminator circuit 310 includes a first frequency discriminator branch 311, a second frequency discriminator branch 312, an OR gate OR1, and an SR latch SR1. The output of the first frequency discriminator branch 311 is connected to the first input of the OR gate OR1, and the output of the second frequency discriminator branch 312 is connected to the second input of the OR gate OR1. The output of the OR gate OR1 is used to output the counting clock signal CLK. The output of the first frequency discriminator branch 311 is connected to the S terminal of the SR latch SR1, and the output of the second frequency discriminator branch 312 is connected to the R terminal of the SR latch SR1. The main output of the SR latch SR1 is used to output the status flag signal FLAG, and the inverted output of the SR latch SR1 is used to output the inverted result FLAG_N of the status flag signal FLAG. Both the status flag signal FLAG and the inverted result FLAG_N serve as addition and subtraction control signals.

[0082] Specifically, the frequency discriminator circuit 310 operates as follows: the first frequency discriminator branch 311 detects the rising edge of the first oscillation signal f1(t) during the high-level period of the second oscillation signal f2, and the second frequency discriminator branch 312 detects the rising edge of the second oscillation signal f2 during the high-level period of the first oscillation signal f1(t). Only when the high-level duration of the second oscillation signal f2 includes two rising edges of the first oscillation signal f1(t), the output of the first frequency discriminator branch 311 outputs a high-level pulse. This high-level pulse is output as a counting clock pulse CLK through an OR gate, and on the other hand, it acts on the S terminal of the SR latch SR1, setting the status flag signal FLAG to high level and FLAG_N to low level. Similarly, when the high-level duration of the first oscillation signal f1(t) includes two rising edges of the second oscillation signal f2, the output of the second frequency discriminator branch 312 outputs a high-level pulse, which is output as a counting clock pulse CLK through the OR gate OR1 and acts on the R terminal of the SR latch SR1, setting the status flag signal FLAG to low level and FLAG_N to high level. Since the two conditions T2>T1 and T1>T2 are mutually exclusive, the status flag signal FLAG will not be set high and low simultaneously.

[0083] In embodiments of the present invention, such as Figure 5 As shown, the first frequency discrimination branch 311 and the second frequency discrimination branch 312 both include a fifth inverter M5, a sixth inverter M6, a seventh inverter M7, an eighth inverter M8, a first D flip-flop D1, and a second D flip-flop D2. Taking the first frequency discriminator branch 311 as an example: the input of the fifth inverter M5 is connected to signal ground, and the output of the fifth inverter M5 is connected to the data input of the first D flip-flop D1, providing a high-level data input for the first D flip-flop D1; the output of the first D flip-flop D1 is connected to the data input of the second D flip-flop D2, the clock of the first D flip-flop D1 is connected to the clock of the second D flip-flop D2, and the output of the second D flip-flop D1 is the output of the first frequency discriminator branch 311; the output of the sixth inverter M6 is connected to the asynchronous set terminal of the second D flip-flop D2, the input of the sixth inverter M6 is connected to the output of the seventh inverter M7, the input of the seventh inverter M7 is connected to the output of the eighth inverter M8, and the input of the eighth inverter M8 is connected to the output of the second D flip-flop D2. That is, the sixth inverter M6, the seventh inverter M7, and the eighth inverter M8 are cascaded sequentially between the output of the second D flip-flop D2 and the asynchronous set terminal of the second D flip-flop D2, forming a feedback path for the delay of three inverters. In the first frequency discrimination branch 311, the asynchronous set terminal of the first D flip-flop D1 is used to input the second oscillation signal f2, and the clock terminal of the first D flip-flop D1 and the clock terminal of the second D flip-flop D2 are used to input the first oscillation signal f1(t).

[0084] In this embodiment of the invention, the working principle of the first frequency discrimination branch is as follows: the second oscillation signal f2 acts on the asynchronous set terminal of the first D flip-flop D1, and the first oscillation signal f1(t) serves as the clock signal for the first D flip-flop D1 and the second D flip-flop D2. When the second oscillation signal f2 is high, the first D flip-flop D1 is asynchronously set, and its output terminal outputs a high level. When the rising edge of the first oscillation signal f1(t) arrives, the second D flip-flop D2 samples the output of the first D flip-flop D1, and the output terminal of the second D flip-flop D2 outputs a high-level pulse. The duration of this high-level pulse is limited to the delay of three inverters by the feedback path composed of the sixth inverter M6, the seventh inverter M7, and the eighth inverter M8. That is, when the high-level duration of the second oscillation signal f2 includes two rising edges of the first oscillation signal f1(t), the output terminal of the first frequency discrimination branch 311 outputs a high-level pulse with a duration of three inverter delays.

[0085] It should be understood that the structure of the second frequency discriminator branch is the same as that of the first frequency discriminator branch, the difference being that: in the second frequency discriminator branch 312, the asynchronous set terminal of the first D flip-flop D1 is used to input the first oscillation signal f1(t), and the clock terminals of the first D flip-flop D1 and the second D flip-flop D2 are used to input the second oscillation signal f2. The working principle of the second frequency discriminator branch 312 is symmetrical to that of the first frequency discriminator branch 311. When the high-level duration of the first oscillation signal f1(t) includes two rising edges of the second oscillation signal f2, the output terminal of the second frequency discriminator branch 312 outputs a high-level pulse with a duration of three inverter delays.

[0086] In an embodiment of the present invention, Figure 6 This is a circuit schematic diagram of the counter circuit provided in an embodiment of the present invention, such as... Figure 6 As shown: Counter circuit 320 includes a three-bit up / down counter. The input of counter circuit 320 is connected to the output of frequency discriminator circuit 310, and is used to receive up / down control signals (status flag signal FLAG and its inverted result FLAG_N) and counting clock signal CLK. Counter circuit 320 is used to: increment the count on each rising edge of counting clock signal CLK when status flag signal FLAG is high; and decrement the count on each rising edge of counting clock signal CLK when status flag signal FLAG is low. Counter circuit 320 outputs a three-bit count value.

[0087] Figure 7 This is a circuit schematic diagram of the digital-to-analog conversion module provided in an embodiment of the present invention, such as... Figure 7 As shown: The input terminal of the digital-to-analog converter module 400 is connected to the output terminal of the counter circuit 320, and is used to output the corresponding adjustable DC voltage Vdc according to the three-digit count value output by the counter circuit 320.

[0088] In embodiments of the present invention, such as Figure 7 As shown, the digital-to-analog converter module 400 includes four weighted current branches, each controlled by a three-bit counter value. Assume the width-to-length ratio w / l of the transistors (P8, P7, P6, P5) in the four weighted current branches is P8:P7:P6:P5 = 4k:2k:k:1, where k is the proportionality coefficient. When the three-bit counter value is 000, the adjustable DC voltage Vdc output by the digital-to-analog converter module 400 is at its maximum; when the three-bit counter value is 111, the adjustable DC voltage Vdc output by the digital-to-analog converter module 400 is at its minimum. The adjustable DC voltage Vdc output by the digital-to-analog converter module 400 satisfies the following relationship with the counter value CNT, the proportionality coefficient k, the reference current I_REF, and the load resistance R3: Vdc = CNT<2:0> × k × I_REF × R3. The adjustable DC voltage Vdc is output to the second voltage-to-current conversion circuit 210 via the output terminal of the digital-to-analog converter module 400, and converted into the second charging current I2.

[0089] In an embodiment of the present invention, Figure 8 This is a schematic diagram of the capacitor voltage and oscillator waveform provided in an embodiment of the present invention. Figure 8 As shown, the rising slope of the capacitor voltage represents the magnitude of the charging current, which determines the high-level duration TH of the oscillation signal; the falling slope of the capacitor voltage represents the magnitude of the discharging current, which determines the low-level duration TL of the oscillation signal. In this embodiment of the invention, the discharging current is set to be much larger than the charging current and remains constant, therefore TH is much larger than TL, and the TL of the first oscillation circuit 120 and the second oscillation circuit 220 are equal.

[0090] Let the period of the first oscillation signal f1(t) be T1, the high-level duration be TH1, and the low-level duration be TL1. Let the period of the second oscillation signal f2 be T2, the high-level duration be TH2, and the low-level duration be TL2. Since TL1 = TL2, when TH2 ≥ TH1 + TL1, we have TH2 + TL2 ≥ TH1 + TL1 + TL2, i.e., T2 ≥ T1 + TL1. Also, since T1 is much larger than TL1, when T2 > T1, the frequency discriminator circuit 310 outputs a high-level pulse, sets the status flag signal FLAG to high, and FLAG_N to low, and the counting clock signal CLK shows a high-level pulse. Similarly, when T1 > T2, the frequency discriminator circuit 310 outputs a high-level pulse, sets the status flag signal FLAG to low, and FLAG_N to high, and the counting clock signal CLK shows a high-level pulse. Since the two conditions are mutually exclusive, they cannot occur simultaneously.

[0091] Figure 9is a schematic waveform diagram of the first oscillation signal f1(t), the second oscillation signal f2 and the output pulse OUT provided by the embodiment of the present invention. Let Tw be an integer multiple of the input period of the periodic irregular input voltage Vin(t) to be measured, then the average frequency f1_avg of the first oscillation signal f1(t) within the Tw time window satisfies: f1_avg=1 / Tw*∫0 Tw f1(t)dt=Vin(t)_avg / R1*C1*VREF, where Vin(t)_avg represents the average value of the periodic irregular input voltage Vin(t) to be measured within the Tw time window. The second oscillation signal f2 satisfies: f2=Vdc / (R2×C2×VREF).

[0092] When the loop is in operation, the up-down counter continuously adjusts Vdc according to the output of the frequency comparator. When f2<f1(t), the count value of the up-down counter increases, Vdc rises, and f2 increases; and vice versa. When the loop is locked, f2=f1_avg, that is, Vdc / (R2×C2×VREF)=Vin(t)_avg / (R1×C1×VREF). When R1=R2 and C1=C2, Vdc=Vin(t)_avg, that is, the DC voltage output by the digital-to-analog conversion module 400 is equal to the average value of the periodic irregular input voltage to be measured, and the DC voltage represents the average value of the measured signal.

[0093] In summary, the circuit for measuring the average value of periodic irregular voltage provided by the embodiment of the present invention adopts the dual-oscillator structure of the first signal channel and the second signal channel to convert the periodic irregular input voltage to be measured and the internal adjustable DC voltage into frequency signals respectively; the frequency discriminator circuit compares the speeds of the two frequencies and outputs an up-down control signal and a counting clock signal, the counter circuit performs up-down counting, and the digital-to-analog conversion module converts the count value into an adjustable DC voltage and feeds it back to the second signal channel, forming an automatically converging negative feedback loop, so that the adjustable DC voltage is automatically locked to the average value of the periodic irregular input voltage to be measured, thereby achieving the beneficial effects of a simple circuit structure, no need for complex timing, low cost, high stability, and capable of directly outputting a high-precision analog average voltage.

[0094] As another embodiment of the present invention, a switching power supply is further provided, which includes the above-mentioned circuit for measuring the average value of periodic irregular voltage.

[0095] In a switching power supply, the power conversion circuit generates a periodic irregular voltage signal (such as PWM waveform, rectified output ripple, etc.). The input terminal of the first signal channel 100 of the measurement circuit is connected to this periodic irregular voltage signal. After the measurement circuit automatically locks through the dual oscillator frequency feedback loop, the DC voltage output by the digital-to-analog converter module 400 represents the average value of the periodic irregular voltage signal. This DC voltage can be used for output voltage monitoring, feedback control, or protection of the switching power supply.

[0096] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A circuit for measuring the average value of a periodic irregular voltage, characterized in that, include: The system comprises a first signal channel, a second signal channel, a frequency comparison and counting module, and a digital-to-analog conversion module. The first signal channel and the second signal channel are both connected to the frequency comparison and counting module. The frequency comparison and counting module is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is also connected to the second signal channel. The first signal channel is used to process the periodic irregular input voltage to be measured to obtain a first oscillation signal whose instantaneous frequency is proportional to the instantaneous value of the periodic irregular input voltage to be measured. The second signal channel is used to process the adjustable DC voltage to obtain a second oscillation signal whose frequency is proportional to the adjustable DC voltage; The frequency comparison counting module is used to determine an adjustment signal for the adjustable DC voltage based on the frequency comparison result between the first oscillation signal and the second oscillation signal. The adjustment signal is used to adjust the adjustable DC voltage so that the frequency of the second oscillation signal approaches the average frequency of the first oscillation signal until the loop is locked. The digital-to-analog converter module is used to output the corresponding adjustable DC voltage according to the adjustment signal, and when the loop is locked, the adjustable DC voltage output by the digital-to-analog converter module is used to characterize the average value of the periodic irregular input voltage to be measured.

2. The average value measurement circuit for periodic irregular voltage according to claim 1, characterized in that, The first signal channel includes a first voltage-to-current conversion circuit and a first oscillation circuit. The input terminal of the first voltage-to-current conversion circuit is the input terminal of the first signal channel. The output terminal of the first voltage-to-current conversion circuit is connected to the input terminal of the first oscillation circuit. The output terminal of the first oscillation circuit is the output terminal of the first signal channel. The first voltage-to-current conversion circuit is used to convert the periodic irregular input voltage to be measured into a transient first charging current in a proportional manner; The first oscillation circuit is used to charge and discharge under the drive of the first charging current to generate the first oscillation signal.

3. The average value measurement circuit for periodic irregular voltage according to claim 2, characterized in that, The first voltage-to-current conversion circuit includes a first resistor, a first comparator, a first N-type MOSFET, a first P-type MOSFET, and a second P-type MOSFET. The non-inverting input terminal of the first comparator is used to input the periodic irregular input voltage to be measured. The inverting input terminal of the first comparator is connected to one end of the first resistor, the other end of the first resistor is connected to signal ground, and the output terminal of the first comparator is connected to the gate terminal of the first N-type MOS transistor. The source terminal of the first N-type MOSFET is connected to one end of the first resistor, and the drain terminal of the first N-type MOSFET is connected to the source terminal of the first P-type MOSFET. The drain terminal of the first P-type MOSFET is connected to the drain terminal of the second P-type MOSFET, and the gate terminal of the first P-type MOSFET is connected to the gate terminal of the second P-type MOSFET. The source terminal of the second P-type MOS transistor is the output terminal of the first voltage-to-current conversion circuit, used to output the first charging current, wherein the first charging current is the ratio of the periodic irregular input voltage to be measured to the resistance value of the first resistor; The first oscillation circuit includes a first capacitor, a second comparator, a third N-type MOSFET, a first inverter, and a second inverter. One end of the first capacitor is connected to the output terminal of the first voltage-to-current conversion circuit, and the other end of the first capacitor is connected to the signal ground. The non-inverting input of the second comparator is connected to the output of the first voltage-to-current conversion circuit. The inverting input of the second comparator is used to input a preset reference voltage. The output of the second comparator is connected to the input of the first inverter. The output of the first inverter is the output of the first oscillation circuit. The output of the first oscillation circuit is used to output the first oscillation signal. The source terminal of the third N-type MOS transistor is connected to the signal ground, the drain terminal of the third N-type MOS transistor is connected to one end of the first capacitor, the gate terminal of the third N-type MOS transistor is connected to the output terminal of the second inverter, and the input terminal of the second inverter is connected to the output terminal of the first inverter.

4. The average value measurement circuit for periodic irregular voltage according to claim 1, characterized in that, The second signal channel includes a second voltage-to-current conversion circuit and a second oscillation circuit. The input terminal of the second voltage-to-current conversion circuit is the input terminal of the second signal channel. The output terminal of the second voltage-to-current conversion circuit is connected to the input terminal of the second oscillation circuit. The output terminal of the second oscillation circuit is the output terminal of the second signal channel. The second voltage-to-current conversion circuit is used to convert the adjustable DC voltage into a steady-state second charging current; The second oscillation circuit is used to generate the second oscillation signal under the drive of the second charging current.

5. The average value measurement circuit for periodic irregular voltage according to claim 4, characterized in that, The second voltage-to-current conversion circuit includes a second resistor, a third comparator, a second N-type MOSFET, a third P-type MOSFET, and a fourth P-type MOSFET. The non-inverting input of the third comparator is used to input the adjustable DC voltage. The inverting input of the third comparator is connected to one end of the second resistor, the other end of the second resistor is connected to signal ground, and the output of the third comparator is connected to the gate of the second N-type MOS transistor. The source terminal of the second N-type MOSFET is connected to one end of the second resistor, and the drain terminal of the second N-type MOSFET is connected to the source terminal of the third P-type MOSFET. The drain terminal of the third P-type MOS transistor is connected to the drain terminal of the fourth P-type MOS transistor, and the gate terminal of the third P-type MOS transistor is connected to the gate terminal of the fourth P-type MOS transistor. The source terminal of the fourth P-type MOS transistor is the output terminal of the second voltage-to-current conversion circuit, used to output the steady-state second charging current, wherein the second charging current is the ratio of the adjustable DC voltage to the resistance value of the second resistor; The second oscillation circuit includes a second capacitor, a fourth comparator, a fourth N-type MOSFET, a third inverter, and a fourth inverter. One end of the second capacitor is connected to the output terminal of the second voltage-to-current conversion circuit, and the other end of the second capacitor is connected to the signal ground; The non-inverting input of the fourth comparator is connected to the output of the second voltage-to-current conversion circuit. The inverting input of the fourth comparator is used to input a preset reference voltage. The output of the fourth comparator is connected to the input of the third inverter. The output of the third inverter is the output of the second oscillation circuit. The output of the second oscillation circuit is used to output the second oscillation signal. The source terminal of the fourth N-type MOS transistor is connected to the signal ground, the drain terminal of the fourth N-type MOS transistor is connected to one end of the second capacitor, the gate terminal of the fourth N-type MOS transistor is connected to the output terminal of the fourth inverter, and the input terminal of the fourth inverter is connected to the output terminal of the third inverter.

6. The average value measurement circuit for periodic irregular voltage according to any one of claims 1 to 5, characterized in that, The frequency comparison and counting module includes a frequency discriminator circuit and a counter circuit. The input terminal of the frequency discriminator circuit is connected to the first signal channel and the second signal channel, respectively. The output terminal of the frequency discriminator circuit is connected to the input terminal of the counter circuit. The output terminal of the counter circuit is the output terminal of the frequency comparison and counting module. The frequency discriminator circuit is used to compare the frequency of the first oscillation signal and the second oscillation signal, and outputs an addition / subtraction control signal and a counting clock signal according to the frequency comparison result; The counter circuit is used to perform increment or decrement counting according to the increment / decrement control signal and the counting clock signal, and output the counting result.

7. The average value measurement circuit for periodic irregular voltage according to claim 6, characterized in that, The frequency discriminator circuit includes a first frequency discriminator branch, a second frequency discriminator branch, an OR gate, and an SR latch. The output of the first frequency discriminator branch is connected to the first input of the OR gate, the output of the second frequency discriminator branch is connected to the second input of the OR gate, and the output of the OR gate is used to output a counting clock signal. The output of the first frequency discriminator branch is connected to the S terminal of the SR latch, the output of the second frequency discriminator branch is connected to the R terminal of the SR latch, the main output of the SR latch is used to output a status flag signal, and the inverted output of the SR latch is used to output the inverted result of the status flag signal, wherein the status flag signal and the inverted result of the status flag signal are both used as the addition / subtraction control signal. Both the first frequency discrimination branch and the second frequency discrimination branch are used to compare the period of the first oscillation signal with the period of the second oscillation signal. When the period of the second oscillation signal is greater than the period of the first oscillation signal, the status flag signal output by the SR latch is high; when the period of the second oscillation signal is less than the period of the first oscillation signal, the status flag signal output by the SR latch is low.

8. The average value measurement circuit for periodic irregular voltage according to claim 7, characterized in that, Both the first frequency discrimination branch and the second frequency discrimination branch include a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first D flip-flop, and a second D flip-flop; The input terminal of the fifth inverter is connected to signal ground, the output terminal of the fifth inverter is connected to the data input terminal of the first D flip-flop, the output terminal of the first D flip-flop is connected to the data input terminal of the second D flip-flop, the clock terminal of the first D flip-flop is connected to the clock terminal of the second D flip-flop, and the output terminal of the second D flip-flop is the output terminal of the first frequency discriminator branch or the second frequency discriminator branch. The output of the sixth inverter is connected to the asynchronous set terminal of the second D flip-flop; the input of the sixth inverter is connected to the output of the seventh inverter; the input of the seventh inverter is connected to the output of the eighth inverter; and the input of the eighth inverter is connected to the output of the second D flip-flop. In the first frequency discrimination branch, the asynchronous set terminal of the first D flip-flop is used to input the second oscillation signal, and the clock terminals of the first D flip-flop and the second D flip-flop in the first frequency discrimination branch are used to input the first oscillation signal. In the second frequency discrimination branch, the asynchronous set terminal of the first D flip-flop is used to input the first oscillation signal, and the clock terminals of the first D flip-flop and the second D flip-flop are used to input the second oscillation signal.

9. The average value measurement circuit for periodic irregular voltage according to claim 7, characterized in that, The counter circuit includes a three-bit up-and-down counter, and when the status flag signal is high, it performs up counting on each rising edge of the counting clock signal; when the status flag signal is low, it performs down counting on each rising edge of the counting clock signal.

10. A switching power supply, characterized in that, It includes the average value measurement circuit for periodic irregular voltage as described in any one of claims 1 to 9.

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