A direct current component extraction circuit

Abstract

The application discloses a direct current component extraction circuit, which is characterized in that a peak-valley detection circuit, a peak-valley sampling and holding circuit and an analog adder circuit are sequentially connected in cascade, the peak-valley detection circuit is used for detecting extreme points of an input alternating current signal and outputting a peak detection signal and a valley detection signal to the peak-valley sampling and holding circuit, the peak-valley sampling and holding circuit samples and holds extreme values of the input alternating current signal in response to the peak detection signal and the valley detection signal, determines a peak value voltage and a valley value voltage, and the analog adder circuit connected with the peak-valley sampling and holding circuit extracts a direct current component voltage based on the peak value voltage and the valley value voltage, so that the extreme value point voltage can be directly captured, the reaction speed is fast, the demand of high dynamic response can be met, the real-time response speed is fast, the direct current component extraction precision can be ensured without the analog-digital conversion processing, and the real-time response speed and the high extraction precision can be simultaneously realized.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement and signal processing technology, and in particular to a DC component extraction circuit. Background Technology

[0002] In the fields of power electronic equipment, industrial control, motor drive and precision testing instruments, accurately and in real time extracting the DC component from AC signals is a core requirement for ensuring system closed-loop stability and improving measurement and control accuracy.

[0003] Currently, existing technologies primarily employ analog filtering or digital processing methods for DC component extraction. Analog filtering typically uses an RC low-pass filter composed of resistors and capacitors, leveraging the capacitor's "DC blocking and AC passing" characteristic. By selecting larger resistor or capacitor values ​​and setting a larger time constant, AC ripple is filtered out to obtain a smooth DC output. However, a large time constant leads to severe phase lag and dynamic response delay in the output signal. Digital processing methods typically involve analog-to-digital conversion of the input analog signal, followed by digital low-pass filtering, moving average algorithms, or leakage integral algorithms to perform digital calculations and obtain a DC estimate. While digital processing offers greater flexibility, it is limited by processor computing power. High-order filtering calculations introduce high latency and memory overhead, and quantization errors from analog-to-digital conversion and fixed-point arithmetic also affect extraction accuracy. Therefore, existing DC component extraction technologies struggle to simultaneously meet the requirements of real-time response speed and high-precision extraction. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a DC component extraction circuit to solve the problem that existing DC component extraction circuits cannot simultaneously meet the requirements of real-time response speed and high-precision extraction.

[0005] To solve the above-mentioned technical problems, the objective of this invention is achieved through the following technical solution: A DC component extraction circuit is provided, comprising a peak-valley detection circuit, a peak-valley sample-and-hold circuit, and an analog adder circuit cascaded in sequence; the peak-valley detection circuit is used to detect the extreme points of the input AC signal and output peak detection signals and valley detection signals; the peak-valley sample-and-hold circuit is connected to the peak-valley detection circuit and is used to sample and hold the extreme points of the input AC signal in response to the peak detection signals and the valley detection signals, thereby determining the peak voltage and valley voltage; the analog adder circuit is connected to the peak-valley sample-and-hold circuit and is used to extract the DC component voltage based on the peak voltage and the valley voltage.

[0006] The further technical solution is as follows: the peak and trough detection circuit includes a differentiator, a zero-crossing comparator, and an edge detection and extreme point discrimination circuit connected in sequence; the input terminal of the differentiator is connected to the input terminal of the DC component extraction circuit, and the differentiator is used to perform differentiation operation on the input AC signal to obtain a differential signal; the input terminal of the zero-crossing comparator is connected to the output terminal of the differentiator, and the zero-crossing comparator is used to convert the differential signal into a square wave signal, the edge of the square wave signal corresponding to the extreme point of the input AC signal; the input terminal of the edge detection and extreme point discrimination circuit is connected to the output terminal of the zero-crossing comparator, and the edge detection and extreme point discrimination circuit is used to extract the rising edge and falling edge from the square wave signal, and generate the trough detection signal and the peak detection signal respectively.

[0007] The further technical solution is as follows: the differentiator includes a first operational amplifier, a first capacitor and a first resistor. The input terminal of the differentiator is connected to the inverting input terminal of the first operational amplifier through the first capacitor. The non-inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the output terminal of the differentiator. The two ends of the first resistor are respectively connected to the inverting input terminal and the output terminal of the first operational amplifier.

[0008] The further technical solution is as follows: the zero-crossing comparator includes a second operational amplifier, the inverting input terminal of the second operational amplifier is grounded, the non-inverting input terminal of the second operational amplifier is connected to the input terminal of the zero-crossing comparator, so as to be connected to the output terminal of the differentiator, and the output terminal of the second operational amplifier is connected to the output terminal of the zero-crossing comparator, so as to be connected to the input terminal of the edge detection and extreme point discrimination circuit.

[0009] The further technical solution is as follows: the edge detection and extreme point discrimination circuit includes a delay module, a first AND gate, and a second AND gate; the input terminal of the delay module is connected to the input terminal of the edge detection and extreme point discrimination circuit, and is connected to the output terminal of the zero-crossing comparator; the first input terminal of the first AND gate is connected to the output terminal of the delay module; an inverter is provided at the second input terminal of the first AND gate as an inverting input terminal; the inverting input terminal of the first AND gate is connected to the output terminal of the zero-crossing comparator, so as to output the peak detection signal at the falling edge of the square wave signal; an inverter is provided at the first input terminal of the second AND gate as an inverting input terminal; the inverting input terminal of the second AND gate is connected to the output terminal of the delay module; the second input terminal of the second AND gate is connected to the output terminal of the zero-crossing comparator, so as to output the trough detection signal at the rising edge of the square wave signal.

[0010] The further technical solution is as follows: the delay module is a delay trigger, the data terminal of the delay trigger is connected to the output terminal of the zero-crossing comparator to latch the square wave signal, and the output terminal of the delay trigger is connected to the first input terminal of the first AND gate and the inverting input terminal of the second AND gate respectively.

[0011] A further technical solution is as follows: the peak-valley sampling and holding circuit includes a first voltage holder and a second voltage holder; the sampling control terminal of the first voltage holder is used to receive the peak detection signal output by the peak-valley detection circuit, the signal input terminal of the first voltage holder is used to receive the input AC signal, and the first voltage holder is used to sample and hold the extreme values ​​of the input AC signal at the peak points to obtain the peak voltage; the sampling control terminal of the second voltage holder is used to receive the valley detection signal output by the peak-valley detection circuit, the signal input terminal of the second voltage holder is used to receive the input AC signal, and the second voltage holder is used to sample and hold the extreme values ​​of the input AC signal at the valley points to obtain the valley voltage.

[0012] The further technical solution is as follows: both the first voltage holder and the second voltage holder employ an extreme value detection circuit. The extreme value detection circuit includes a third operational amplifier, a fourth operational amplifier, a first diode, a first grounding capacitor, and a first grounding resistor. The non-inverting input terminal of the third operational amplifier serves as the input terminal of the extreme value detection circuit. The inverting input terminals of both the third and fourth operational amplifiers are connected to the output terminal of the fourth operational amplifier. The output terminal of the third operational amplifier is connected to the non-inverting input terminal of the fourth operational amplifier via the first diode. The output terminal of the fourth operational amplifier serves as the output terminal of the extreme value detection circuit. The first grounding capacitor and the first grounding resistor are connected in parallel and are electrically connected at the connection node between the first diode and the non-inverting input terminal of the fourth operational amplifier.

[0013] The further technical solution is as follows: the first input terminal of the analog adder circuit is connected to the output terminal of the first voltage holder, and the second input terminal of the analog adder circuit is connected to the output terminal of the second voltage holder, which is used to perform an arithmetic average of the peak voltage and the trough voltage to obtain the DC component voltage.

[0014] The further technical solution is as follows: the analog adder circuit includes a fifth operational amplifier, a first input resistor, a second input resistor, and a feedback resistor; the first end of the first input resistor is connected to the first input terminal of the analog adder circuit, so as to be connected to the output terminal of the first voltage holder; the first end of the second input resistor is connected to the second input terminal of the analog adder circuit, so as to be connected to the output terminal of the second voltage holder; the second end of the first input resistor is connected to the second end of the second input resistor and then connected to the inverting input terminal of the fifth operational amplifier, the non-inverting input terminal of the fifth operational amplifier is grounded, and the two ends of the feedback resistor are respectively connected to the inverting input terminal and the output terminal of the fifth operational amplifier.

[0015] The beneficial technical effects of this invention are as follows: The DC component extraction circuit of this invention, by setting up a peak-valley detection circuit, a peak-valley sample-and-hold circuit, and an analog adder circuit in cascade, wherein the peak-valley detection circuit is used to detect the extreme points of the input AC signal and outputs peak detection signals and valley detection signals to the peak-valley sample-and-hold circuit, so that the peak-valley sample-and-hold circuit, in response to the peak detection signals and valley detection signals, samples and holds the extreme points of the input AC signal to determine the peak voltage and valley voltage, and then, through the analog adder circuit connected to the peak-valley sample-and-hold circuit, extracts the peak voltage and valley voltage. The quasi-adder circuit processes peak and trough voltages to extract the DC component voltage, directly capturing extreme point voltages with fast response speed, meeting the requirements of high dynamic response and real-time fast response. Moreover, it eliminates the need for analog-to-digital converters (ADCs) for analog-to-digital conversion, avoiding quantization noise and rounding errors caused by fixed-point digital arithmetic, thus ensuring the accuracy of DC component extraction and achieving a balance between real-time response speed and high extraction accuracy. At the same time, it does not rely on computing resources such as digital signal processors, effectively reducing the system processor's consumption of memory and computing resources. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the DC component extraction circuit provided by the present invention; Figure 2 The circuit diagram of the differentiator of the peak and trough detection circuit of the DC component extraction circuit provided by the present invention; Figure 3 The circuit diagram of the zero-crossing comparator of the peak and trough detection circuit of the DC component extraction circuit provided by the present invention; Figure 4 The circuit diagram of the edge detection and extreme point discrimination circuit of the peak and valley detection circuit of the DC component extraction circuit provided by the present invention; Figure 5 A circuit diagram of the first voltage holder and the second voltage holder of the peak and trough sampling and holding circuit of the DC component extraction circuit provided by the present invention; Figure 6 A circuit diagram of the analog adder circuit for the DC component extraction circuit provided by the present invention; Figure 7 This is a timing diagram showing the operation of the peak and trough detection circuit when performing DC component extraction using the DC component extraction circuit provided by this invention. Figure 8 This is the final timing diagram for DC component extraction using the DC component extraction circuit provided by the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 , Figure 1 The diagram below illustrates the framework of the DC component extraction circuit provided by the present invention. The DC component extraction circuit 10 includes a peak-valley detection circuit 11, a peak-valley sample-and-hold circuit 12, and an analog adder circuit 13 cascaded together. The peak-valley detection circuit 11 is used to detect the extreme points of the input AC signal and output peak detection signals and valley detection signals. The peak-valley sample-and-hold circuit 12 is connected to the peak-valley detection circuit 11 and is used to sample and hold the extreme points of the input AC signal in response to the peak detection signals and the valley detection signals to determine the peak voltage and valley voltage. The analog adder circuit 13 is connected to the peak-valley sample-and-hold circuit 12 and is used to extract the DC component voltage from the peak voltage and the valley voltage.

[0020] The DC component extraction circuit 10 comprises a cascaded peak and trough detection circuit 11, a peak and trough sample-and-hold circuit 12, and an analog adder circuit 13. The peak and trough detection circuit 11 detects the extreme points of the input AC signal and outputs peak and trough detection signals to the peak and trough sample-and-hold circuit 12. The peak and trough sample-and-hold circuit 12 then samples and holds the extreme points of the input AC signal in response to the peak and trough detection signals, determining the peak and trough voltages. The voltage is then transferred to the circuit connected to the peak and trough sample-and-hold circuit 13. The analog adder circuit 13 processes the peak and trough voltages to extract the DC component voltage, enabling direct capture of extreme point voltages. This results in a fast response speed, meeting the requirements for high dynamic response and providing real-time fast response. Furthermore, it eliminates the need for an analog-to-digital converter (ADC) for analog-to-digital conversion, avoiding quantization noise and rounding errors caused by fixed-point digital arithmetic. This ensures the accuracy of DC component extraction, achieving a balance between real-time response speed and high extraction accuracy. Simultaneously, it does not rely on computing resources such as a digital signal processor, effectively reducing the system processor's consumption of memory and computing resources.

[0021] Preferably, the peak-valley sample-and-hold circuit 12 responds to the peak detection signal and the valley detection signal, samples and holds the extreme values ​​of the input AC signal, and determines the peak voltage and the valley voltage; the analog adder circuit 13 is connected to the peak-valley sample-and-hold circuit 12 to perform an arithmetic average of the peak voltage and the valley voltage to obtain the DC component voltage, thereby directly capturing the extreme point voltage and outputting the average value.

[0022] Specifically, the peak and trough detection circuit 11 includes a differentiator 111, a zero-crossing comparator 112, and an edge detection and extreme point discrimination circuit 113 connected in sequence. The input terminal of the differentiator 111 is connected to the input terminal of the DC component extraction circuit 10, and the differentiator 111 is used to perform differentiation on the input AC signal to obtain a differential signal. The input terminal of the zero-crossing comparator 112 is connected to the output terminal of the differentiator 111, and the zero-crossing comparator 112 is used to convert the differential signal into a differential signal. The signal is replaced with a square wave signal, the edges of which correspond to the extreme points of the input AC signal. The rising edge of the square wave corresponds to the trough of the input AC signal, and the falling edge of the square wave corresponds to the peak of the input AC signal. The input terminal of the edge detection and extreme point discrimination circuit 113 is connected to the output terminal of the zero-crossing comparator 112. The edge detection and extreme point discrimination circuit 113 is used to extract the rising edge and falling edge from the square wave signal and generate the trough detection signal and the peak detection signal, respectively.

[0023] Combination Figure 1 and Figure 2Specifically, the differentiator 111 includes a first operational amplifier A1, a first capacitor C1, and a first resistor R1. The input terminal of the differentiator 111 is connected to the inverting input terminal of the first operational amplifier A1 through the first capacitor C1. The non-inverting input terminal of the first operational amplifier A1 is grounded. The output terminal of the first operational amplifier A1 is connected to the output terminal of the differentiator 111. The two ends of the first resistor R1 are connected to the inverting input terminal and the output terminal of the first operational amplifier A1, respectively, so that the inverting input terminal of the first operational amplifier A1 is connected to the output terminal through the first resistor R1. The input terminal of the differentiator 111 is used to receive the input AC signal. The first end of the first resistor R1 is electrically connected to the connection node between the first capacitor C1 and the inverting input terminal of the first operational amplifier A1, and the second end of the first resistor R1 is electrically connected to the connection node between the output terminal of the first operational amplifier A1 and the output terminal of the differentiator 111.

[0024] Combination Figure 1 and Figure 3 Specifically, the zero-crossing comparator 112 includes a second operational amplifier A2, the inverting input of the second operational amplifier A2 is grounded, the non-inverting input of the second operational amplifier A2 is connected to the input of the zero-crossing comparator 112, and is connected to the output of the differentiator 111. The output of the second operational amplifier A2 is connected to the output of the zero-crossing comparator 112, and is connected to the input of the edge detection and extreme point discrimination circuit 113. The second operational amplifier A2 determines the positive or negative value of the output of the differentiator 111. The second operational amplifier A2 is in open-loop comparator mode. Based on the high gain of the open loop, the second operational amplifier A2 can convert the continuous analog waveform output by the differentiator 111 into a binary square wave signal, which has only two states: high level and low level. When the differential signal output by the differentiator 111 is positive, that is, the differential signal rises, the output of the zero-crossing comparator 112 outputs a high level. When the differential signal output by the differentiator 111 is negative, that is, the differential signal falls, the output of the zero-crossing comparator 112 outputs a low level.

[0025] Combination Figure 1 and Figure 4Specifically, the edge detection and extreme point discrimination circuit 113 includes a delay module U1, a first AND gate U2, and a second AND gate U3. The input terminal of the delay module U1 is connected to the input terminal of the edge detection and extreme point discrimination circuit 113, and is connected to the output terminal of the zero-crossing comparator 112. The first input terminal of the first AND gate U2 is connected to the output terminal of the delay module U1. An inverter is provided at the second input terminal of the first AND gate U2 as an inverting input terminal. The inverting input terminal of the first AND gate U2 is connected to the output terminal of the zero-crossing comparator 112, so as to output the peak detection signal at the falling edge of the square wave signal. An inverter is provided at the first input terminal of the second AND gate U3 as an inverting input terminal. The inverting input terminal of the second AND gate U3 is connected to the output terminal of the delay module U1. The second input terminal of the second AND gate U3 is connected to the output terminal of the zero-crossing comparator 112, so as to output the trough detection signal at the rising edge of the square wave signal. The output terminals of the first AND gate U2 and the second AND gate U3 serve as the first output terminal OUT1 and the second output terminal OUT2 of the peak and trough detection circuit 11, respectively, to output the peak detection signal and the trough detection signal.

[0026] Preferably, the delay module U1 is a delay trigger, the data terminal D of the delay trigger is connected to the output terminal of the zero-crossing comparator 112 to latch the square wave signal, and the output terminal Q of the delay trigger is connected to the first input terminal of the first AND gate U2 and the inverting input terminal of the second AND gate U3 respectively.

[0027] The delay trigger is a D flip-flop. The delay trigger latches the square wave signal output by the zero-crossing comparator 112 in real time. The first AND gate U2 performs a logical AND operation on the output of the delay trigger and the inverted square wave signal to extract the falling edge of the square wave signal and generate a peak detection signal. The second AND gate U3 performs a logical AND operation on the output of the inverted delay trigger and the square wave signal to extract the rising edge of the square wave signal and generate a trough detection signal.

[0028] Combination Figure 1 and Figure 5Specifically, the peak-valley sampling and holding circuit 12 includes a first voltage holder 121 and a second voltage holder 122. The sampling control terminal of the first voltage holder 121 is used to receive the peak detection signal output by the peak-valley detection circuit 11, and the signal input terminal of the first voltage holder 121 is used to receive the input AC signal. The first voltage holder 121 is used to sample and hold the input AC signal at the peak point to obtain the peak voltage. The sampling control terminal of the second voltage holder 122 is used to receive the valley detection signal output by the peak-valley detection circuit 11, and the signal input terminal of the second voltage holder 122 is used to receive the input AC signal. The second voltage holder 122 is used to sample and hold the input AC signal at the valley point to obtain the valley voltage.

[0029] Combination Figure 1 and Figure 5 Specifically, both the first voltage holder 121 and the second voltage holder 122 employ an extreme value detection circuit. This extreme value detection circuit includes a third operational amplifier A3, a fourth operational amplifier A4, a first diode D11, a first grounding capacitor C11, and a first grounding resistor R11. The non-inverting input of the third operational amplifier A3 serves as the input of the extreme value detection circuit. The inverting inputs of both the third operational amplifier A3 and the fourth operational amplifier A4 are connected to the output of the fourth operational amplifier A4. The output of the third operational amplifier A3 is connected to the non-inverting input of the fourth operational amplifier A4 via the first diode D11. The output of the fourth operational amplifier A4 serves as the output of the extreme value detection circuit. The first grounding capacitor C11 and the first grounding resistor R11 are connected in parallel and are electrically connected at the connection node between the first diode D11 and the non-inverting input of the fourth operational amplifier A4.

[0030] Preferably, the anode of the first diode D11 is connected to the output terminal of the third operational amplifier A3, the cathode of the first diode D11 is connected to the non-inverting input terminal of the fourth operational amplifier A4, and the first grounding capacitor C11 and the first grounding resistor R11 are electrically connected at the connection node between the cathode of the first diode D11 and the non-inverting input terminal of the fourth operational amplifier A4.

[0031] Combination Figure 1 and Figure 6Specifically, the first output terminal OUT1 and the second output terminal OUT2 of the peak and trough detection circuit 11 are connected to the first input terminal IN1 and the second input terminal IN2 of the analog adder circuit 13, respectively. Then, the first input terminal IN1 of the analog adder circuit 13 is connected to the output terminal of the first voltage holder 121, and the second input terminal IN2 of the analog adder circuit 13 is connected to the output terminal of the second voltage holder 122. This is used to perform an arithmetic average of the peak voltage and the trough voltage to obtain the DC component voltage.

[0032] Combination Figure 1 and Figure 6 Specifically, the analog adder circuit 13 includes a fifth operational amplifier A5, a first input resistor R21, a second input resistor R22, and a feedback resistor R23. The first terminal of the first input resistor R21 is connected to the first input terminal IN1 of the analog adder circuit 13, which is connected to the output terminal of the first voltage holder 121. The first terminal of the second input resistor R22 is connected to the second input terminal IN2 of the analog adder circuit 13, which is connected to the output terminal of the second voltage holder 122. The second terminal of the first input resistor R21, after being connected to the second terminal of the second input resistor R22, is connected to the inverting input terminal of the fifth operational amplifier A5. The non-inverting input terminal of the fifth operational amplifier A5 is grounded. The two terminals of the feedback resistor R23 are connected to the inverting input terminal and the output terminal of the fifth operational amplifier A5, respectively, so that the inverting input terminal of the fifth operational amplifier A5 is connected to the output terminal through the feedback resistor R23. The non-inverting input terminal of the fifth operational amplifier A5 is grounded. The first end of the feedback resistor R23 is electrically connected between the connection node of the second end of the first input resistor R21 and the second end of the second input resistor R22 and the inverting input terminal of the fifth operational amplifier A5. The second end of the feedback resistor R23 is electrically connected at the connection node of the output terminal of the fifth operational amplifier A5 and the output terminal of the analog adder circuit 13.

[0033] Combination Figure 7 and Figure 8 , Figure 7 The diagram illustrates the timing process of the peak and trough detection circuit during DC component extraction using the aforementioned DC component extraction circuit. Figure 8 The final timing diagram for DC component extraction using the aforementioned DC component extraction circuit is shown, as follows: Figure 7As shown, the horizontal axis of the timing diagram in each sub-diagram represents time. The first sub-diagram is the timing diagram of the input AC signal, and its vertical axis represents the voltage amplitude. In the first sub-diagram, the blue solid line represents the input AC signal, and the red dashed line represents the changing DC component. The second sub-diagram is the timing diagram of the differential signal, and its vertical axis represents the voltage amplitude per second. The third sub-diagram is the timing diagram of the square wave signal, and its vertical axis represents the logic level. The fourth sub-diagram is the timing diagram of the trough detection signal and the peak detection signal, and its vertical axis represents the pulse. In the fourth sub-diagram, the red line represents the peak detection signal, and the blue line represents the trough detection signal. Figure 8 As shown in the figure, the horizontal axis represents time, and the vertical axis represents voltage amplitude. Figure 8 In the diagram, the dark blue line represents the input AC signal (VIN), the red line represents the peak voltage (Vpeak), the light blue line represents the trough voltage (Vvalley), and the thick black line represents the DC component voltage (Vdc).

[0034] Combination Figure 7 and Figure 8 For one cycle of the input AC signal, the circuit's operating timing is illustrated in the rising phase, peak phase, falling phase, and trough phase as follows: In the rising phase: the input AC signal accelerates upwards according to a sinusoidal law, with the slope increasing first and then gradually decreasing, reaching its maximum at the midpoint; the differential signal gradually decreases from its positive maximum value to zero; if the differential signal is greater than zero, it indicates that the signal is in an upward trend; since the differential signal is always positive, the square wave signal remains at a high level; the peak detection signal remains at a low level because it has not reached the peak, and the trough detection signal remains at a low level; the peak voltage remains the peak sampling value of the previous cycle, the trough voltage remains the trough sampling value of the previous cycle, and the DC component voltage remains near the DC component of the previous cycle.

[0035] During the peak phase: the input AC signal reaches its maximum value (at the peak), with an instantaneous slope of zero; the differential signal crosses zero, changing from a positive value to a negative value, with the zero-crossing point at the peak; at the instant the differential signal crosses zero, the square wave signal jumps from a high level to a low level, forming a falling edge; the peak detection signal is triggered at the falling edge of the zero-crossing signal of the input AC signal (i.e., the peak position), outputting a high-level signal, while the trough detection signal remains at a low level; the peak voltage is updated by continuously acquiring the current value of the input AC signal while the peak detection signal is at a high level, updating the peak voltage to the peak sampling value of this cycle and holding it after the signal ends, while the trough voltage holds the trough sampling value of the previous cycle, and the DC component voltage is updated along with the peak voltage.

[0036] During the descent phase: the input AC signal decelerates and decreases to approximately a trough, with the descent slope being the largest initially and then gradually approaching zero; the differential signal changes from zero to a negative value, and its absolute value first increases and then decreases; since the differential signal is always negative, the square wave signal remains at a low level; the peak detection signal remains at a low level, and the trough detection signal remains at a low level because it has not reached a trough; the peak voltage remains the peak sampling value of the peak phase, the trough voltage remains the trough sampling value of the previous cycle, and the DC component voltage remains the DC component updated after the peak phase.

[0037] During the trough phase: the input AC signal reaches its minimum value (at the trough), with an instantaneous slope of zero; the differential signal crosses zero, changing from a negative value to a positive value, with the zero-crossing point at the trough moment; at the instant the differential signal crosses zero, the square wave signal jumps from a low level to a high level, forming a rising edge; the peak detection signal remains at a low level, and the trough detection signal is triggered at the rising edge of the zero-crossing signal of the input AC signal (i.e., the trough position), outputting a high-level signal; the peak voltage maintains the peak sampling value of the peak phase, and the trough voltage continuously acquires the current value of the input AC signal while the trough detection signal is at a high level, updating the trough voltage to the trough sampling value of this cycle and maintaining it after the signal ends; the DC component voltage is updated along with the update of the trough voltage.

[0038] In summary, the DC component extraction circuit of this invention comprises a cascaded peak-valley detection circuit, a peak-valley sample-and-hold circuit, and an analog adder circuit. The peak-valley detection circuit detects the extreme points of the input AC signal and outputs peak and valley detection signals to the peak-valley sample-and-hold circuit. The peak-valley sample-and-hold circuit then samples and holds the extreme points of the input AC signal in response to the peak and valley detection signals, determining the peak and valley voltages. Finally, the analog adder circuit connected to the peak-valley sample-and-hold circuit... By processing peak and trough voltages, the DC component voltage is extracted, enabling direct capture of extreme point voltages and output of average values. This results in a fast response speed, meeting the requirements for high dynamic response and providing real-time fast response. Furthermore, it eliminates the need for analog-to-digital converters (ADCs) for analog-to-digital conversion, avoiding quantization noise and rounding errors caused by fixed-point digital arithmetic. This ensures the accuracy of DC component extraction, achieving a balance between real-time response speed and high extraction accuracy. Simultaneously, it does not rely on computing resources such as digital signal processors, effectively reducing the system processor's consumption of memory and computing resources.

[0039] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A DC component extraction circuit, characterized in that, It includes a cascaded peak and trough detection circuit, a peak and trough sample-and-hold circuit, and an analog adder circuit; The peak and trough detection circuit is used to detect the extreme points of the input AC signal and output peak detection signal and trough detection signal; The peak-valley sampling and holding circuit is connected to the peak-valley detection circuit, and is used to sample and hold the extreme values ​​of the input AC signal in response to the peak detection signal and the valley detection signal, and to determine the peak voltage and valley voltage. The analog adder circuit is connected to the peak-valley sample-and-hold circuit and is used to extract the DC component voltage based on the peak voltage and the valley voltage.

2. The DC component extraction circuit according to claim 1, characterized in that, The peak and trough detection circuit includes a differentiator, a zero-crossing comparator, and an edge detection and extreme point discrimination circuit that are connected in sequence. The input terminal of the differentiator is connected to the input terminal of the DC component extraction circuit. The differentiator is used to perform differentiation operations on the input AC signal to obtain a differential signal. The input terminal of the zero-crossing comparator is connected to the output terminal of the differentiator. The zero-crossing comparator is used to convert the differential signal into a square wave signal. The edge of the square wave signal corresponds to the extreme point of the input AC signal. The input terminal of the edge detection and extreme point discrimination circuit is connected to the output terminal of the zero-crossing comparator. The edge detection and extreme point discrimination circuit is used to extract the rising edge and falling edge from the square wave signal and generate the trough detection signal and the peak detection signal respectively.

3. The DC component extraction circuit according to claim 2, characterized in that, The differentiator includes a first operational amplifier, a first capacitor, and a first resistor. The input terminal of the differentiator is connected to the inverting input terminal of the first operational amplifier through the first capacitor. The non-inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the output terminal of the differentiator. The two ends of the first resistor are connected to the inverting input terminal and the output terminal of the first operational amplifier, respectively.

4. The DC component extraction circuit according to claim 2, characterized in that, The zero-crossing comparator includes a second operational amplifier. The inverting input of the second operational amplifier is grounded, and the non-inverting input of the second operational amplifier is connected to the input of the zero-crossing comparator to be connected to the output of the differentiator. The output of the second operational amplifier is connected to the output of the zero-crossing comparator to be connected to the input of the edge detection and extreme point discrimination circuit.

5. The DC component extraction circuit according to claim 2, characterized in that, The edge detection and extreme point discrimination circuit includes a delay module, a first AND gate, and a second AND gate; The input terminal of the delay module is connected to the input terminal of the edge detection and extreme point discrimination circuit, and is connected to the output terminal of the zero-crossing comparator. The first input terminal of the first AND gate is connected to the output terminal of the delay module. An inverter is provided at the second input terminal of the first AND gate as an inverting input terminal. The inverting input terminal of the first AND gate is connected to the output terminal of the zero-crossing comparator, so as to output the peak detection signal at the falling edge of the square wave signal. An inverter is provided at the first input terminal of the second AND gate as an inverting input terminal. The inverting input terminal of the second AND gate is connected to the output terminal of the delay module. The second input terminal of the second AND gate is connected to the output terminal of the zero-crossing comparator, so as to output the trough detection signal at the rising edge of the square wave signal.

6. The DC component extraction circuit according to claim 5, characterized in that, The delay module is a delay trigger. The data terminal of the delay trigger is connected to the output terminal of the zero-crossing comparator to latch the square wave signal. The output terminal of the delay trigger is connected to the first input terminal of the first AND gate and the inverting input terminal of the second AND gate, respectively.

7. The DC component extraction circuit according to claim 1, characterized in that, The peak-valley sampling and holding circuit includes a first voltage holder and a second voltage holder. The sampling control terminal of the first voltage holder is used to receive the peak detection signal output by the peak and trough detection circuit, the signal input terminal of the first voltage holder is used to receive the input AC signal, and the first voltage holder is used to sample and hold the extreme value of the input AC signal at the peak point of the input AC signal to obtain the peak voltage. The sampling control terminal of the second voltage holder is used to receive the trough detection signal output by the peak and trough detection circuit. The signal input terminal of the second voltage holder is used to receive the input AC signal. The second voltage holder is used to sample and hold the extreme value of the input AC signal at the trough point of the input AC signal to obtain the trough voltage.

8. The DC component extraction circuit according to claim 7, characterized in that, Both the first voltage holder and the second voltage holder employ an extreme value detection circuit, which includes a third operational amplifier, a fourth operational amplifier, a first diode, a first grounding capacitor, and a first grounding resistor. The non-inverting input of the third operational amplifier serves as the input of the extreme value detection circuit. The inverting inputs of the third operational amplifier and the fourth operational amplifier are both connected to the output of the fourth operational amplifier. The output of the third operational amplifier is connected to the non-inverting input of the fourth operational amplifier via the first diode. The output of the fourth operational amplifier serves as the output of the extreme value detection circuit. The first grounding capacitor and the first grounding resistor are connected in parallel, and the first grounding capacitor and the first grounding resistor are electrically connected at the connection node between the first diode and the non-inverting input terminal of the fourth operational amplifier.

9. The DC component extraction circuit according to claim 7, characterized in that, The first input terminal of the analog adder circuit is connected to the output terminal of the first voltage holder, and the second input terminal of the analog adder circuit is connected to the output terminal of the second voltage holder, for performing an arithmetic average of the peak voltage and the trough voltage to obtain the DC component voltage.

10. The DC component extraction circuit according to claim 9, characterized in that, The analog adder circuit includes a fifth operational amplifier, a first input resistor, a second input resistor, and a feedback resistor; The first end of the first input resistor is connected to the first input end of the analog adder circuit, so as to be connected to the output end of the first voltage holder; The first end of the second input resistor is connected to the second input terminal of the analog adder circuit, so as to be connected to the output terminal of the second voltage holder; The second end of the first input resistor is connected to the second end of the second input resistor and then connected to the inverting input of the fifth operational amplifier. The non-inverting input of the fifth operational amplifier is grounded. The two ends of the feedback resistor are connected to the inverting input and the output of the fifth operational amplifier, respectively.

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