Mainboard and electronic equipment

Abstract

The utility model discloses a mainboard and electronic equipment. The mainboard comprises a first processor, a second processor, a third processor, a fourth processor, a first bridge piece, a second bridge piece and a mainboard management control chip, every two of the first processor, the second processor, the third processor and the fourth processor are connected with each other, the first processor is connected with the first bridge piece, the second processor is connected with the second bridge piece, and the mainboard management control chip is connected with the mainboard management control chip. The first bridge chip is connected with the mainboard management control chip, so that the mainboard adopts four processors and two bridge chips, the design is simple, the cost is lower, the integration level is high, the interfaces are rich, and the real-time performance and reliability of information processing are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, in particular to a mainboard and an electronic device. Background Art

[0002] With the development of science and technology, the demand for high-performance computers is increasing day by day, and the performance of core components such as processors and bridge chips has been greatly improved. The motherboard design of server platforms based on high-performance processor bridge chips has become particularly important. The current motherboard design can no longer meet the requirements of real-time and reliability of information processing. Utility Model Content

[0003] In view of the above problems, the present utility model is proposed to provide a mainboard and an electronic device that overcome the above problems or at least partially solve the above problems.

[0004] According to one aspect of the utility model, a mainboard is provided, characterized in that the mainboard includes a first processor, a second processor, a third processor, a fourth processor, a first bridge chip, a second bridge chip, and a mainboard management control chip;

[0005] The first processor, the second processor, the third processor, and the fourth processor are connected to each other in pairs;

[0006] The first processor is connected to the first bridge chip;

[0007] The second processor is connected to the second bridge chip;

[0008] The first bridge chip is connected to the mainboard management control chip.

[0009] Optionally, the first processor, the second processor, the third processor, and the fourth processor are connected to each other in pairs through a 16-bit wide end-to-end bus, the first processor is connected to the first bridge chip through a 16-bit wide end-to-end bus, and the second processor is connected to the second bridge chip through a 16-bit wide end-to-end bus.

[0010] Optionally, the mainboard further includes an Ethernet chip and a first network connector, and the mainboard management control chip is connected to the first network connector via the Ethernet chip.

[0011] Optionally, the mainboard further includes a second network connector, and the first bridge chip is connected to the second network connector.

[0012] Optionally, the mainboard further includes a rear display interface and a switch, and the mainboard management control chip and the first bridge chip are both connected to the rear display interface via the switch.

[0013] Optionally, the mainboard further includes a front display interface and a video driver chip, and the switch is further connected to the front display interface via the video driver chip.

[0014] Optionally, the mainboard management control chip is connected to the first bridge chip and the second bridge chip through a universal serial bus, and the mainboard management control chip is also connected to the first bridge chip through a high-speed serial bus and a reduced pin bus.

[0015] Optionally, the first processor, the second processor, the third processor and the fourth processor are Loongson 3C5000 processors or Loongson 3C5000L processors, and the first bridge chip and the second bridge chip are Loongson 7A2000 bridge chips.

[0016] Optionally, the mainboard management control chip is Loongson 2K0500 BMC.

[0017] According to another aspect of the utility model, an electronic device is provided, comprising the mainboard as claimed in the above claims.

[0018] According to a mainboard of the utility model, a first processor, a second processor, a third processor, a fourth processor, a first bridge chip, a second bridge chip, and a mainboard management control chip are included. The first processor, the second processor, the third processor, and the fourth processor are connected to each other in pairs, the first processor is connected to the first bridge chip, the second processor is connected to the second bridge chip, and the first bridge chip is connected to the mainboard management control chip, so that the mainboard adopts four processors and two bridge chips, and also has a simple design, low cost, high integration, rich interfaces, and improved real-time and reliability of information processing.

[0019] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not considered to be limiting of the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0021] Figure 1 A schematic diagram of the structure of a mainboard according to an embodiment of the utility model is shown;

[0022] Figure 2 A schematic diagram of a mainboard is shown;

[0023] Figure 3 A structural schematic diagram of a mainboard described in an embodiment of the utility model is shown. DETAILED DESCRIPTION

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0025] In the description of the present invention, unless otherwise specified, "plurality" means two or more than two; the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "inside", "outside", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the machine or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] The specific implementation of the utility model is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the utility model, but are not used to limit the scope of the utility model.

[0028] See also Figure 1 The utility model provides a motherboard 100, including a first processor 101, a second processor 102, a third processor 103, a fourth processor 104, a first bridge chip 105, a second bridge chip 106, and a motherboard management control chip 107;

[0029] The first processor 101, the second processor 102, the third processor 103, and the fourth processor 104 are connected to each other. The first processor 101 is connected to the first bridge chip 105. The second processor 102 is connected to the second bridge chip 106. The first bridge chip 105 is connected to the motherboard management control chip 107.

[0030] For example, Figure 2In the schematic diagram of the motherboard shown, the first processor CPU0, the second processor CPU1, the third processor CPU2, and the fourth processor CPU3 can use the Loongson 3C5000 processor. CPU0 and CPU2 are interconnected through HT (HyperTransport, end-to-end bus). The first bridge chip (main bridge) and the second bridge chip (auxiliary bridge) can use the Loongson 7A2000 bridge chip. The main bridge and CPU0 are interconnected through an end-to-end bus. The auxiliary bridge and CPU1 are interconnected through an end-to-end bus. The motherboard management control chip (i.e., BMC module) can use the Loongson 2K0500 BMC (Baseboard Management Controller, baseboard management controller) chip. The BMC module and the main bridge are interconnected through LPC (LowPinCountBus, reduced pin bus), PCIe (Peripheral Component Interconnect express, peripheral component interconnect high-speed bus), and USB (Universal Serial Bus, universal serial bus). Among them, the BMC module is an independent module, which may not be limited to the Loongson 2K0500 BMC, but may also be any other applicable BMC. The processor is not limited to the Loongson 3C5000 processor. For example, if the processor adopts the Loongson 3C5000L processor, the 16-bit HT bus interconnected between CPU0, CPU1, CPU2 and CPU3 needs to be configured in 8-bit mode, and the corresponding HT bus interconnected with the 7A2000 bridge chip is also configured in 8-bit mode. The bridge chip is also not limited to the Loongson 7A2000 bridge chip, and any other suitable bridge chip can be used.

[0031] It should be noted that, in addition to the above-mentioned processor, bridge chip and motherboard management control chip, the motherboard proposed in the embodiment of the utility model also requires basic components such as power module, clock module, various slots, etc., and the embodiment of the utility model does not limit this.

[0032] According to a mainboard of the utility model, a first processor, a second processor, a third processor, a fourth processor, a first bridge chip, a second bridge chip, and a mainboard management control chip are included. The first processor, the second processor, the third processor, and the fourth processor are connected to each other in pairs, the first processor is connected to the first bridge chip, the second processor is connected to the second bridge chip, and the first bridge chip is connected to the mainboard management control chip, so that the mainboard adopts four processors and two bridge chips, and also has a simple design, low cost, high integration, rich interfaces, and improved real-time and reliability of information processing.

[0033] In the embodiment of the present utility model, optionally, referring to Figure 1The first processor, the second processor, the third processor, and the fourth processor are connected to each other through a 16-bit wide end-to-end bus, the first processor is connected to the first bridge chip through a 16-bit wide end-to-end bus, and the second processor is connected to the second bridge chip through a 16-bit wide end-to-end bus.

[0034] The first processor, the second processor, the third processor, the fourth processor, the first bridge chip, and the second bridge chip are all chips that support 16-bit wide end-to-end buses. The 16-bit wide end-to-end buses are used between processors and between processors and bridge chips, which can speed up the data transmission speed between chips and improve the information processing speed.

[0035] For example, Figure 2 As shown in the figure, the HT1 X16 of CPU0 and the HT0 X16 of CPU1 are connected to each other through a 16-bit HT bus. The connections between other CPUs and bridge chips are as follows Figure 2 CPU0 is also connected to CPU0, CPU1, CPU2 and CPU3 through GPIO (General Purpose Input Output) interfaces, such as GPIO12 interface of CPU0 is connected to GPIO13 interface of CPU0, CPU1, CPU2 and CPU3, so as to control circuit components.

[0036] In the embodiment of the present utility model, optionally, referring to Figure 3 The mainboard 100 further includes an Ethernet chip 108 and a first network connector 109 , and the mainboard management control chip 107 is connected to the first network connector 109 via the Ethernet chip 108 .

[0037] Ethernet chip refers to the chip that implements the physical interface transceiver of Ethernet, which can be used as an external network card chip for the motherboard management control chip, for example Figure 2 As shown, the GMAC (Gigabit Media Access Control) interface of the BMC module is connected to the YT8531C chip (a domestic Ethernet chip).

[0038] The first network connector is a module used to connect to a network cable, for example Figure 2As shown, the GMAC interface of the BMC module is connected to the RJ45+Transformer module through the YT8531C chip. The RJ45+Transformer module is a network connector with a built-in transformer. The GMAC interface of the BMC module is a Gigabit Ethernet interface. The GMAC interface is connected to the YT8531C chip through the RGMII (Reduced Gigabit Media Independent Interface). The YT8531C chip is connected to the RJ45+Transformer module through the MDI (Medium Dependent Interface).

[0039] In the embodiment of the present utility model, optionally, referring to Figure 3 The mainboard 100 further includes a second network connector 110 , and the first bridge chip 105 is connected to the second network connector 110 .

[0040] The first bridge chip is a bridge chip with a built-in network card function. The second network connector is a module used to connect to a network cable. The first bridge chip can be directly connected to the second network connector to achieve network connection. For example, the Loongson 7A2000 bridge chip is a bridge chip with a built-in network card function, which simplifies the motherboard design. The motherboard obviously has all the benefits of the first bridge chip.

[0041] For example, Figure 2 As shown, the GNET (Ethernet direct output port on the bridge chip, implemented on the Loongson 7A2000 bridge chip) interface of the main bridge is connected to the RJ45+Transformer module, which is a network connector with a built-in transformer.

[0042] In the embodiment of the present utility model, optionally, referring to Figure 3 The mainboard 100 further includes a rear display interface 111 and a switch 112 , and the mainboard management control chip 107 and the first bridge chip 105 are both connected to the rear display interface 111 through the switch 112 .

[0043] The first bridge chip is a bridge chip with built-in graphics card function. The motherboard management control chip is a chip with built-in basic performance graphics card. The rear display interface is an interface used to connect to a display device for data signal transmission, for example, a DSUB-15F interface, where DSUB is an interface standard commonly used for data transmission, which can connect data generation devices and data output devices, such as central processing units and printers. A switcher is a module used to switch lines, for example, a SWITCH chip.

[0044] For example, Figure 2 As shown, the VGA interface of the main bridge is connected to the SWITCH chip, the VGA (Video Graphics Array) interface of the BMC module is also connected to the SWITCH chip, and the SWITCH chip is further connected to the DSUB-15F interface.

[0045] In the embodiment of the present utility model, optionally, referring to Figure 3 The mainboard 100 further includes a front display interface 113 and a video driver chip 114 , and the switch 112 is also connected to the front display interface 113 via the video driver chip 114 .

[0046] The rear display interface is an interface used to connect to a display device for data signal transmission, such as the front VGA pin header. The video driver chip is an integrated circuit chip used for video filtering, control and driving other electronic devices, such as the SGM9117 chip (a domestic video driver chip).

[0047] For example, Figure 2 As shown, the SWITCH chip is also connected to the SGM9117 chip, and the SGM9117 chip is connected to the front VGA pin header.

[0048] In an embodiment of the utility model, optionally, the mainboard management control chip is connected to the first bridge chip and the second bridge chip through a universal serial bus, and the mainboard management control chip is also connected to the first bridge chip through a high-speed serial bus and a reduced pin bus.

[0049] Universal Serial Bus is a serial bus standard, for example, USB2.0, USB3.0, etc. The motherboard management control chip and the bridge chip need to be connected through multiple interfaces to meet different information interaction requirements. The motherboard management control chip is connected to the first bridge chip through a universal serial bus, and the motherboard management control chip can also be connected to the second bridge chip through another universal serial bus. The connection between the motherboard management control chip and the second bridge chip is optional. The motherboard management control chip is connected to the first bridge chip and the second bridge chip through the universal serial bus respectively, realizing the information data interaction between the motherboard management control chip and the two bridge chips.

[0050] For example, the USB (OTG) on the BMC module is connected to the USB2.0 interface of the main bridge, where OTG (On The Go) refers to a USB mode that allows two devices to negotiate identities. The USB (OTG) on the BMC module is also connected to the USB3.0 interface of the auxiliary bridge.

[0051] A high-speed serial bus is a communication link with higher data throughput, for example, the PCIe bus. A reduced pin bus is a bus with fewer pins, for example, the LPC bus.

[0052] For example, the BMC module is connected to the PCIe-F0 interface of the main bridge, and the number of channels is 1. The LPC (Slave) interface of the BMC module is connected to the LPC interface of the main bridge.

[0053] In an embodiment of the utility model, optionally, the first processor, the second processor, the third processor and the fourth processor are Loongson 3C5000 processors or Loongson 3C5000L processors, and the first bridge chip and the second bridge chip are Loongson 7A2000 bridge chips.

[0054] As described above, in addition to being compatible with the Loongson 3C5000 processor, the embodiments of the present invention are also compatible with the Loongson 3C5000L processor and any other applicable processors. In addition to being compatible with the Loongson 7A2000 bridge chip, the embodiments of the present invention are also compatible with any other applicable bridge chips.

[0055] When using the Loongson 3C5000L processor, the 16-bit HT bus interconnecting the first processor, the second processor, the third processor and the fourth processor needs to be configured in 8-bit mode, and the corresponding HT bus of the Loongson 7A2000 bridge chip also needs to be configured in 8-bit mode.

[0056] In an embodiment of the utility model, optionally, the mainboard management control chip is Loongson 2K0500BMC.

[0057] In addition to being compatible with the Loongson 2K0500 BMC, the embodiment of the utility model can also be compatible with any other applicable BMC.

[0058] In the embodiment of the utility model, optionally, the mainboard further includes a plurality of USB interfaces. The plurality of USB interfaces can be arbitrarily allocated between the first bridge chip and the second bridge chip. For example, there are 6 USB interfaces, including 2 rear USB 2.0 interfaces, 2 rear USB 3.0 interfaces, and 2 front USB 3.0 interfaces.

[0059] For example, Figure 2 As shown, the 2 USB2.0 ports on the main bridge are connected to 2 USB2.0 TypeA interfaces, the 2 USB3.0 ports on the main bridge are connected to 2 USB3.0 TypeA interfaces, the 1 USB2.0 port on the main bridge is connected to 1 front USB2.0 pin header, and the 1 USB3.0 port on the main bridge is connected to 1 front USB3.0 pin header.

[0060] In the embodiment of the utility model, optionally, the mainboard further includes a plurality of standard PCIe3.0 slots. The plurality of standard PCIe3.0 slots can be arbitrarily allocated between the first bridge chip and the second bridge chip. For example, the six standard PCIe3.0 slots are one X16-bit wide slot, four X8-bit wide slots, and one X4-bit wide slot.

[0061] For example, Figure 2 As shown, PCIe-G0 on the main bridge is connected to PCIe Slot (slot) X16, PCIe-H on the main bridge is connected to PCIe Slot (slot) X8, PCIe-F1 on the auxiliary bridge is connected to PCIe Slot (slot) X4, PCIe-G0 on the auxiliary bridge is connected to 2 PCIe Slot (slot) X8, and PCIe-H on the auxiliary bridge is connected to PCIe Slot (slot) X8.

[0062] In the embodiment of the utility model, the motherboard may also include an M.2 interface of M-key PCIe X4. M-key is a type of interface for solid-state hard disks, with 5 gold fingers on the right. M.2 interface is also called NGFF, which stands for Next Generation Form Factor in English. It is a new interface specification that replaces MSATA.

[0063] For example, Figure 2 As shown, the PCIe-F1 on the main bridge is connected to PCIe-M.2X4.

[0064] In the embodiment of the utility model, optionally, the mainboard also includes a plurality of memory slots. For example, 16 memory slots. Support RDIMM (Registered Dual Inline Memory Module) and UDIMM (Unbuffered Dual Inline Memory Module). Each processor outputs 4 memory slots, and the SPD (Serial Presence Detect) address is: MC0 is 100, MC1 is 000, MC2 is 010, and MC3 is 110.

[0065] For example, Figure 2 As shown, CPU0 outputs 4 DDR4 SLOTs (a type of memory slot), CPU1 outputs 4 DDR4 SLOTs, CPU2 outputs 4 DDR4 SLOTs, and CPU3 outputs 4 DDR4 SLOTs.

[0066] In the embodiment of the utility model, optionally, the mainboard further includes two MINI SAS HD interfaces. MINI SAS HD is a hard disk interface.

[0067] For example, Figure 2 As shown in the figure, the SATA3.0 of the main bridge is connected to a MINI SAS HD interface, and the SATA3.0 of the auxiliary bridge is connected to a MINI SAS HD interface. Two Loongson 7A2000 bridge chips can provide up to 8 SATA3.0 interfaces.

[0068] also, Figure 2 In the example, the power module is a collection of all power supplies on the motherboard. The clock module is a collection of all clocks on the motherboard. The power module and the clock module need to be connected to all electronic devices on the motherboard that require power and clock signals. The GMEM (Graphics Memory) interface of the main bridge is connected to the display memory DDR4. The BMC module can be connected to the power module to monitor the voltage of the voltage module. The BMC module can also be connected to 4 SYSTEM FANs (chassis cooling fans) and 4 CPU FANs (processor cooling fans) for fan speed control and monitoring. The I2C (Inter-Integrated Circuit) Host bus of the BMC module is also connected to the I2C bus of CPU0, CPU1, CPU2, and CPU3 through SGM4551 (a level converter). The I2C Host bus of the BMC module is also connected to the I2C0 bus of the first bridge chip and the second bridge chip. The I2CHost bus of the BMC module can also be connected to the onboard temperature sensor. The SPI (Serial Peripheral interface) of CPU0 is connected to the boot firmware. The SE (Secure Element) SPI of CPU0 is connected to the SE firmware. The LA-JTAG (Joint Test Action Group) interface of CPU0 is connected to the connector. The UART0 (Universal Asynchronous Receiver / Transmitter0) serial port of CPU0 is connected to the level converter, the level converter is connected to the 3232 chip, and the 3232 chip is connected to the DSUB-9M interface.

[0069] An embodiment of the utility model provides an electronic device, comprising the mainboard in the above embodiment.

[0070] The motherboard composed of the above-mentioned multiple processors can be used as a server motherboard for industrial-level applications or as a desktop motherboard for serving families, business offices, etc., thereby ensuring the reliability of data computing and processing and improving work efficiency.

[0071] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0072] A motherboard and an electronic device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A motherboard, characterized in that: The mainboard includes a first processor, a second processor, a third processor, a fourth processor, a first bridge chip, a second bridge chip, and a mainboard management control chip; The first processor, the second processor, the third processor, and the fourth processor are connected to each other in pairs; The first processor is connected to the first bridge chip; The second processor is connected to the second bridge chip; The first bridge chip is connected to the mainboard management control chip.

2. The mainboard according to claim 1, characterized in that: The first processor, the second processor, the third processor, and the fourth processor are connected to each other through a 16-bit wide end-to-end bus, the first processor is connected to the first bridge chip through a 16-bit wide end-to-end bus, and the second processor is connected to the second bridge chip through a 16-bit wide end-to-end bus.

3. The mainboard according to claim 1, characterized in that: The mainboard further includes an Ethernet chip and a first network connector, and the mainboard management control chip is connected to the first network connector via the Ethernet chip.

4. The mainboard according to claim 1, characterized in that: The mainboard further includes a second network connector, and the first bridge chip is connected to the second network connector.

5. The mainboard according to claim 1, characterized in that: The mainboard further includes a rear display interface and a switch, and the mainboard management control chip and the first bridge chip are both connected to the rear display interface via the switch.

6. The mainboard according to claim 5, characterized in that: The mainboard also includes a front display interface and a video driver chip, and the switch is also connected to the front display interface through the video driver chip.

7. The mainboard according to claim 1, characterized in that: The mainboard management control chip is connected to the first bridge chip and the second bridge chip through a universal serial bus, and the mainboard management control chip is also connected to the first bridge chip through a high-speed serial bus and a reduced pin bus.

8. The mainboard according to any one of claims 1 to 7, characterized in that: The first processor, the second processor, the third processor and the fourth processor are Loongson 3C5000 processors or Loongson 3C5000L processors, and the first bridge chip and the second bridge chip are Loongson 7A2000 bridge chips.

9. The mainboard according to claim 8, characterized in that: The motherboard management control chip is Loongson 2K0500BMC.

10. An electronic device, characterized in that: A mainboard comprising any one of claims 1 to 9.

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