High-speed communication interface circuit and high-speed SWD communication device

Abstract

The utility model discloses a high-speed communication interface circuit and a high-speed SWD communication device. The high-speed communication interface circuit comprises a host processor, a GPIO interface, a first SPI interface and a second SPI interface, wherein the host processor is arranged on a host; the GPIO interface, the first SPI interface and the second SPI interface are respectively in signal connection with the host processor; the GPIO interface, the first SPI interface and the second SPI interface are respectively connected with an SWD interface of a slave through an isolation module and carry out data transmission; the GPIO interface and the first SPI interface are configured to be controlled by the host processor and send data to the SWD interface of the slave; and the GPIO interface and the second SPI interface are configured to be controlled by the host processor and receive data from the SWD interface of the slave. By utilizing the scheme of the utility model, the communication speed of the host and the slave can be improved, so that the debugging and burning efficiency of the host to the slave is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, and in particular to a high-speed communication interface circuit and a high-speed SWD communication device. Background Art

[0002] SWD (Serial Wire Debug) is a low pin count debugging method that uses a two-wire debugging method, so it is particularly suitable for chips with high pin packaging requirements.

[0003] The SWD interface consists of two lines: the serial clock line SWCLK and the serial data line SWDIO. SWCLK is used by the host (debugger) to send clock beats to the target chip unidirectionally and provide a clock signal; SWDIO is a bidirectional data line used for reading and writing data.

[0004] When the host controls SWDIO, the host outputs data on the falling edge of SWCLK, and the slave reads data on the rising edge of SWCLK. When the slave controls SWDIO, the slave outputs data on the rising edge of SWCLK, and the host reads data on the falling edge of SWCLK.

[0005] Each frame on the SWD data line consists of the following 2 or 3 phases:

[0006] 1. Request: Master to Slave

[0007] 2. Response: Slave to Master

[0008] 3. Data transfer phase: When reading data, data is transferred from the slave to the host; when writing data, data is transferred from the host to the slave. This phase is not present for every operation request.

[0009] In the prior art, the host usually only uses the GPIO interface to connect to the SWD interface of the slave, and the driver also uses an ordinary GPIO driver. The host processor calls the GPIO driver to control the GPIO interface level to realize the SWD communication function. Because the GPIO interface driver itself does not support automatic control of the level flip of batch data, accordingly, during SWD communication, the host processor needs to keep looping and executing the GPIO interface driver, and the speed of this processor-led GPIO interface level flip depends on the performance and busyness of the processor. Generally speaking, the efficiency of this processor-led GPIO interface high and low level flip is low, which leads to low SWD communication efficiency between the host and the slave, and it takes a long time (such as 300 seconds) to download a large-capacity program (such as 1MB), affecting the development experience. Utility Model Content

[0010] The embodiments of the utility model provide a high-speed communication interface circuit and a high-speed SWD communication device, which can improve the speed of SWD communication between a host and a slave, thereby improving chip debugging and burning efficiency.

[0011] On the one hand, an embodiment of the utility model provides a high-speed communication interface circuit, comprising: a host processor arranged on a host, and a GPIO interface, a first SPI interface, and a second SPI interface respectively connected to the host processor signal;

[0012] The GPIO interface, the first SPI interface and the second SPI interface are respectively connected to the SWD interface of the slave through an isolation module and perform data transmission;

[0013] The GPIO interface and the first SPI interface are configured to be controlled by the host processor and send data to the SWD interface of the slave;

[0014] The GPIO interface and the second SPI interface are configured to be controlled by the host processor and receive data from the SWD interface of the slave.

[0015] Optionally, the connection line between the host and the slave includes a SWD clock line and a SWD data line;

[0016] The SWD clock line is respectively connected to the clock line of the GPIO interface, the clock line of the first SPI interface and the clock line of the second SPI interface after passing through the first node;

[0017] The SWD data line is respectively connected to the data line of the GPIO interface, the data line of the first SPI interface and the data line of the second SPI interface after passing through the second node.

[0018] Optionally, the SWD clock line is connected to the clock line of the GPIO interface, the clock line of the first SPI interface, and the clock line of the second SPI interface in an isolated manner, respectively, including:

[0019] The clock line of the GPIO interface, the clock line of the first SPI interface, and the clock line of the second SPI interface are each connected to the first node through an isolation module, and are used to output a clock signal to the first node in a time-division multiplexing manner.

[0020] Optionally, the GPIO interface clock line is used to output a control clock signal to the first node after the isolation module connected thereto is enabled;

[0021] The clock line of the first SPI interface is used to output a write clock signal to the first node after the isolation module connected thereto is enabled;

[0022] The clock line of the second SPI interface is used to output a read clock signal to the first node after the isolation module connected thereto is enabled;

[0023] The frequencies of the write clock signal, the read clock signal, and the control clock signal are the same or different.

[0024] Optionally, the SWD data line is connected to the data line of the GPIO interface, the data line of the first SPI interface, and the data line of the second SPI interface in an isolated manner, including:

[0025] The data line of the GPIO interface, the data line of the first SPI interface, and the data line of the second SPI interface are each connected to a second node through an isolation module.

[0026] Optionally, the data line of the GPIO interface is in input-output mode, the data line of the first SPI interface is in single-line output mode, and the data line of the second SPI interface is in single-line input mode;

[0027] The data line of the GPIO interface is used to send and receive data to the second node after the isolation module connected thereto is enabled;

[0028] The data line of the first SPI interface is a data output terminal of the first SPI interface, and is used to send data to the second node after the isolation module connected thereto is enabled;

[0029] The data line of the second SPI interface is a data input terminal of the second SPI interface, and is used to receive data from the second node after the isolation module connected thereto is enabled.

[0030] Optionally, the GPIO interface and the first SPI interface are also configured to be controlled by the host processor to send a request packet to the SWD interface of the slave.

[0031] Optionally, the isolation module is arranged in the GPIO interface, the first SPI interface and the second SPI interface.

[0032] Optionally, the isolation module is arranged outside the GPIO interface, the first SPI interface and the second SPI interface; the circuit further comprises: an enable signal output interface;

[0033] The host processor is further used to generate an enable signal corresponding to each isolation module, and output the enable signal to the corresponding isolation module through the enable signal output interface.

[0034] Optionally, the enable signal output interface is a common IO interface.

[0035] On the other hand, an embodiment of the utility model further provides a high-speed SWD communication device, the device comprising: a host and a slave, the host comprising the high-speed communication interface circuit.

[0036] Optionally, the host further comprises: a memory storing a driver program, a debugging program and / or a program to be burned of the high-speed SWD communication device;

[0037] The host processor of the host implements debugging and / or burning of the slave by loading and running the driver, debugging program and / or program to be burned of the high-speed SWD communication device.

[0038] The high-speed communication interface circuit and high-speed SWD communication device provided by the embodiment of the utility model adopt a GPIO (General-purpose input / output) interface to connect with the slave SWD interface to send and receive information that cannot be processed in batches, and use SPI (Serial Peripheral Interface) to connect with the slave SWD interface to send and receive information that can be processed in batches. The GPIO interface, the first SPI interface and the second SPI interface are connected to the SWD interface of the target chip through an isolation module to solve the crosstalk between the interfaces, and then the communication speed of the SWD interface is effectively improved by running the driver of the dedicated high-speed SWD communication device. In the scheme of the utility model, not only is the structure simple and the probability of failure is reduced, but even if a failure occurs, it is easy to troubleshoot. In addition, the communication operation between the debugger and the target chip is simple and easy to implement; the amount of code is small and the power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a structural schematic diagram of a high-speed communication interface circuit provided by the utility model;

[0040] Figure 2 This is another structural schematic diagram of the high-speed communication interface circuit provided by the utility model;

[0041] Figure 3 This is a schematic diagram of the interface connection structure between the high-speed communication interface circuit provided by the utility model and the debugger and the target chip;

[0042] Figure 4 This is another schematic diagram of an interface connection structure between a debugger and a target chip in which the high-speed communication interface circuit provided by the utility model is applied;

[0043] Figure 5 This is a schematic diagram of the write timing in the SWD protocol;

[0044] Figure 6 This is a schematic diagram of the read timing in the SWD protocol;

[0045] Figure 7 This is a structural schematic diagram of a high-speed SWD communication device provided by the utility model;

[0046] Figure 8 yes Figure 7 The figure shows a flow chart of data transmission during program debugging or burning of a target chip in a high-speed SWD communication device. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] SPI (Serial Peripheral Interface) is a synchronous serial communication interface specification for chip communication, mainly used in single-chip microcomputer systems. The SPI interface is called a four-wire interface. The SPI interface includes a chip select signal CS, a clock signal SCK, a master output slave input signal MOSI, and a master input slave output signal MISO. Among them:

[0049] 1. Chip select signal CS: It is the selected signal of the slave. When the CS signal is at a low level, the slave is in a selected state and can receive instructions from the host. When the CS signal is at a high level, the slave is in a non-selected state and does not receive instructions from the host or send data.

[0050] 2. Clock signal: SCK signal is the clock signal of SPI bus. The frequency of SCK signal determines the speed of data transmission.

[0051] 3. Data signal: MOSI signal is the data output signal of the SPI bus, sent by the master; MISO signal is the data input signal of the SPI bus, sent by the slave.

[0052] The SPI interface can be configured with various parameters according to actual needs, such as data rate, data format, clock polarity, clock phase, etc.

[0053] SPI devices communicate in full-duplex mode. In point-to-point communication, the SPI interface does not require addressing operations, making communication simple and efficient.

[0054] In the prior art, the host usually only uses the GPIO interface to connect to the SWD interface of the slave, and the host processor runs the GPIO driver to control the GPIO interface level to realize the SWD communication function. Due to the fact that the GPIO driver itself does not support automatic batch data level flipping, during SWD communication, the host processor needs to execute the GPIO interface driver program in a loop, and the speed of this processor-led GPIO interface level flipping depends on the performance and busyness of the processor. Generally speaking, the efficiency of this processor-led GPIO interface high and low level flipping is low, which leads to the problem of low data transmission efficiency. To this end, the embodiment of the utility model provides a high-speed communication interface circuit and a high-speed SWD communication device. When the host and the slave perform batch data interaction, the SPI interface has a high receiving and sending clock frequency and can automatically batch data receiving and sending. The characteristics of the SPI interface with the assistance of the GPIO interface realize SWD communication, effectively improving the transmission speed of the SWD interface.

[0055] like Figure 1 The figure is a structural diagram of a high-speed communication interface circuit provided by the utility model.

[0056] The high-speed communication interface circuit includes: a host processor 101 disposed on a host 100, and a GPIO interface 102, a first SPI interface 103, and a second SPI interface 104 respectively connected to the host processor 101. The host processor 101 and the interfaces can serve as the main control chip of the host 100. Among them:

[0057] The GPIO interface 102 , the first SPI interface 103 and the second SPI interface 104 are respectively connected to the SWD interface 201 of the slave 200 through the isolation module EN.

[0058] It should be noted that the isolation module EN can be arranged outside the GPIO interface 102, the first SPI interface 103, and the second SPI interface 104, such as Figure 1 It can also be set in the GPIO interface 102, the first SPI interface 103, and the second SPI interface 104, as shown; Figure 2 shown.

[0059] The isolation module EN provides enabling and disabling of the interface IO state. After disabling, the voltage change of the interface on one side cannot be transmitted to the other side. At the same time, the module can also provide a level conversion function.

[0060] Continue to refer to Figure 1In this embodiment, the GPIO interface 102 and the first SPI interface 103 are configured to be controlled by the host processor 101 and send data to the SWD interface 201 of the slave 200; the GPIO interface 102 and the second SPI interface 104 are configured to be controlled by the host processor 101 and receive data from the SWD interface 201 of the slave 200.

[0061] The GPIO interface 102 is a bidirectional transmission interface, which can cooperate with the first SPI interface 103 to transmit data, and can also cooperate with the second SPI interface 104 to receive data.

[0062] In the embodiment of the utility model, the GPIO interface 102 has a clock line (referred to as GPIO_CLK) and a data line (referred to as GPIO_DATA). The clock line GPIO_CLK and the data line GPIO_DATA are respectively connected to the clock line SWCLK and the data line SWDIO of the SWD interface 201 at the first node A and the second node B, so as to realize the transmission of the non-batch-processable data part between the host 100 and the slave 200, wherein the clock line GPIO_CLK is used to unidirectionally output the serial clock signal to the slave 200, and the data line GPIO_DATA is a bidirectional data line, which is used to write data to the slave 200 or read data from the slave 200.

[0063] In this embodiment, the clock line GPIO_CLK is connected to the clock line of the first SPI interface 103 (denoted as SPI1_CLK) and the clock line of the second SPI interface 104 (denoted as SPI2_CLK) through an isolation module; the data line GPIO_DATA is connected to the data line of the first SPI interface 103 and the data line of the second SPI interface 104 through an isolation module. Among them, the data signal port of the first SPI interface 103 is the host output slave input signal port (MOSI). For the convenience of description, the signal line connected to the data signal port is referred to as the first SPI data line and is denoted as SPI1_DATA_OUT; the data signal port of the second SPI interface 104 is the host input slave output signal port (MISO). For the convenience of description, the signal line connected to the data signal port is referred to as the second SPI data line and is denoted as SPI2_DATA_IN.

[0064] In the present invention, the first SPI interface 103 is in single-line output mode, and the second SPI interface 104 is in single-line input mode. Accordingly, the data line of the first SPI interface 103 is the data output end of the first SPI interface 103, which is used to send batch data to the slave 200; the data line of the second SPI interface 104 is the data input end of the second SPI interface 104, which is used to receive batch data from the slave 200.

[0065] That is to say, the present application scheme uses the single-line simplex communication mode of SPI, so the SPI interface only has a clock signal line (SCK) and a unidirectional data line, namely MOSI or MISO.

[0066] For ease of description, the first SPI interface 103 is sometimes referred to as SPI1 and the second SPI interface 104 is referred to as SPI2 in the following description. Accordingly, the clock signal lines and unidirectional data lines of SPI1 and SPI2 are respectively labeled as follows:

[0067] SPI1 is dedicated to sending: SCK (SPI1_CLK), MOSI (SPI1_DATA_OUT);

[0068] SPI2 is dedicated to receiving: SCK (SPI2_CLK), MISO (SPI2_DATA_IN).

[0069] In order to more clearly show the connection methods of the above three interfaces, Figure 3 As shown, it is shown that Figure 1 The high-speed communication interface circuit shown is a schematic diagram of the interface connection structure between the debugger and the target chip.

[0070] Reference Figure 3 In this example, the clock line GPIO_CLK of the GPIO interface, the clock line SPI1_CLK of the first SPI interface, and the clock line SPI2_CLK of the second SPI interface are each connected to the first node A through an isolation module, for outputting a clock signal to the first node A. The first node A is connected to the clock line SWCLK of the SWD interface of the target chip. Wherein:

[0071] The clock line GPIO_CLK of the GPIO interface outputs a control clock signal to the first node A after the isolation module 30 connected thereto is enabled;

[0072] The clock line SPI1_CLK of the first SPI interface is used to output a write clock signal to the first node A after the isolation module 31 connected thereto is enabled;

[0073] The clock line SPI2_CLK of the second SPI interface is used to output a read clock signal to the first node A after the isolation module 32 connected thereto is enabled;

[0074] The frequencies of the control clock signal, the write clock signal and the read clock signal can be configured according to actual application requirements, which is not limited in this solution. The frequencies of the write clock signal, the read clock signal and the control clock signal can be the same or different.

[0075] In this embodiment, when the isolation modules of different clock lines are enabled, the clock frequencies input to the target chip may be different. That is, the reading and writing of data may be performed according to the data transmission rate defined by the SPI interface, which will be described in detail later.

[0076] Similarly, in Figure 3 In the example shown, the data lines GPIO_DATA, SPI1_DATA_OUT, and SPI2_DATA_IN of the GPIO interface are each connected to the second node B through the isolation module, and the second node B is connected to the data line SWDIO of the SWD interface of the slave. GPIO_DATA and SPI1_DATA_OUT send data to the slave through the second node B; GPIO_DATA and SPI2_DATA_IN receive data from the slave through the second node B.

[0077] When sending data to the slave, it is necessary to enable the isolation module 31 connected to the clock line SPI1_CLK of the first SPI interface and the isolation module 41 connected to SPI1_DATA_OUT; when receiving data from the slave, it is necessary to enable the isolation module 32 connected to the clock line SPI2_CLK of the second SPI interface and the isolation module 42 connected to SPI2_DATA_IN.

[0078] The enabling (or gating) of each of the above isolation modules can be controlled by a corresponding enabling signal. Accordingly, in the utility model high-speed communication interface circuit, it can further include: an enabling signal output interface, such as Figure 3 The connection line marked with "enable" is the connection line connecting the enable signal output interface and the isolation module. Figure 1 The host processor 101 can generate an enable signal corresponding to each isolation module and output it to the corresponding isolation module through the enable signal output interface.

[0079] In a non-limiting embodiment, the enable signal output interface may be implemented using an IO interface, such as a GPIO interface.

[0080] like Figure 4 As shown, it is shown that Figure 2 The high-speed communication interface circuit shown is applied to another interface connection structure diagram between a debugger and a target chip.

[0081] Figure 4 In the embodiment shown, because Figure 2 The isolation module in the high-speed communication interface circuit is set in the GPIO interface 102, the first SPI interface 103, and the second SPI interface 104, so there is no need to enable the signal output interface, and the host processor can directly control the isolation module in the chip.

[0082] It should be noted that the data transmission between the high-speed communication interface circuit provided in the embodiment of the utility model and the SWD interface of the slave adopts the standard SWD protocol. The GPIO interface 102 sends and receives information that cannot be batch processed, while the part of the SWD protocol that can be batch processed, such as WDATA is fixed to 32 bits, and the host processor 101 can transmit 32 bits to the first SPI interface 103 at one time. For example, RDATA is fixed to 32 bits, and the host processor 101 can inform the second SPI interface 104 to read 32 bits of data. The rest of the work is automatically sent / received by the hardware circuit inside the SPI, and the host processor 101 does not need to intervene during the period. Since the hardware circuit of SPI is fast, it can also output a higher frequency clock than the host processor 101, so it can greatly improve the data sending and receiving speed and simplify the software processing process.

[0083] like Figure 5 and Figure 6 As shown in the figure, they are respectively the schematic diagrams of write timing and read timing in the SWD protocol, where the meaning of each bit is as follows:

[0084] Bit0: Start, fixed to 1.

[0085] Bit1: APnDP, 0 means accessing the DP (Debug Port) register, 1 means accessing the MEM-AP (Memory Access Port) register.

[0086] Bit2: RnW, 0 indicates a write request, 1 indicates a read request.

[0087] Bit[4:3]: Address value A[3:2], storing the address of the DP / MEM-AP register.

[0088] Bit5: Parity, used to indicate the parity bit of the four-digit number consisting of {APnDP, RnW, A[2:3]}.

[0089] Bit6: Stop, fixed to 0.

[0090] Bit7: Park, fixed to 1.

[0091] Trn: Turnaround cycle, during which the data line is not driven. In actual application, the input and output states of the SWDIO pins must be flipped during Trn. The time of this cycle is controlled by the TURNROUND parameter, which is stored in the WCR (Word Control Register) register.

[0092] The ACK value returned by the target chip consists of 3 bits, as follows:

[0093] ACK[0:2]==001, indicating FAULT;

[0094] ACK[0:2]==010, indicating WAIT;

[0095] ACK[0:2]==100, indicating OK.

[0096] The data consists of 32 bits of valid data + 1 bit of parity bit, where:

[0097] WDATA: Data sent by the host, that is, data written to the slave.

[0098] RDATA: Data received by the host, that is, data read from the slave.

[0099] Parity: 32-bit odd parity for write data, from host to target; 32-bit odd parity for read data, from target to host.

[0100] Combine the following Figure 1 and Figure 3 , further details the communication process between the high-speed communication interface circuit and the target chip, the communication process is as follows:

[0101] By default, all isolation modules are closed.

[0102] First, the host turns on the switches of the isolation module 30 connected to GPIO_CLK and the isolation module 40 connected to GPIO_DATA through an enable signal, connects the SWCLK and SWDIO of the slave, and sends bit0 to bit7 (i.e., the request part) of the SWD protocol to the slave;

[0103] Next, a blank bit, bit 8 (reverse cycle), is sent, and the transmission direction of GPIO_DATA is reversed. The slave SWCLK and SWDIO are connected continuously, and the response (ACK[0:2]) from the slave is prepared.

[0104] After the slave responds ACK[0:2]==100 (indicating OK), the isolation module 30 connected to GPIO_CLK and the isolation module 40 connected to GPIO_DATA are immediately turned off, and the connection between SWCLK and SWDIO is disconnected.

[0105] It should be noted that each port of the host has a default level set, and the SWD port of the slave also has a default pull-up resistor. After disconnecting the connection between SWCLK and SWDIO, the corresponding ports of the host and slave will not be in a floating state.

[0106] If the above request (Bit2 in bit0 to bit7: RnW, 0 indicates a write request, 1 indicates a read request) is a write request, then after the switching cycle, the switches of the isolation module 31 connected to SPI1_CLK and the isolation module 41 connected to SPI1_DATA_OUT are turned on through the enable signal, SPI1_CLK and SPI1_DATA_OUT are connected to the slave SWCLK and SWDIO, and 32-bit batch data is sent to the slave. After the sending is completed, the switches of the isolation module 31 connected to SPI1_CLK and the isolation module 41 connected to SPI1_DATA_OUT are immediately turned off, and the connection between SWCLK and SWDIO is disconnected.

[0107] If the above request is a read request, there is no turnaround cycle, and the switches of the isolation module 32 connected to SPI2_CLK and the isolation module 42 connected to SPI2_DATA_IN are directly opened through the enable signal, SPI2_CLK and SP2_DATA_IN are connected to the slave SWCLK and SWDIO, and 32-bit batch data from the slave is received. After the reception is completed, the switches of the isolation module 32 connected to SPI2_CLK and the isolation module 42 connected to SPI2_DATA_IN are immediately closed, and the connection between SWCLK and SWDIO is disconnected.

[0108] Then, the checksum of the 32-bit batch data is calculated, and the switches of the isolation module 30 connected to GPIO_CLK and the isolation module 40 connected to GPIO_DATA are turned on at the same time, and the SWCLK and SWDIO of the slave are connected. If the above request is a read request, the check bit (Parity) returned by the slave is received, and the two checksums are compared to see if they are consistent. If they are consistent, a standard SWD communication process is terminated and the next frame of data processing is waited for. If the above request is a send request, the check bit result is sent to the slave, and the slave determines whether the result is consistent, and then the host ends a standard SWD communication process and waits for the next frame of data processing.

[0109] It should be noted that the above-mentioned read request and write request can also be packaged (for the convenience of description, it is referred to as a request packet) and sent in the same manner as the above-mentioned data transmission, that is, the GPIO interface and the first SPI interface are configured to be controlled by the host processor and send a request packet to the SWD interface of the slave.

[0110] The high-speed communication interface circuit provided by the embodiment of the utility model adopts a GPIO interface to connect with the slave SWD interface to send and receive information that cannot be processed in batches, and uses SPI to connect with the slave SWD interface to send and receive information that can be processed in batches. The GPIO interface, the first SPI interface and the second SPI interface are connected to the SWD interface of the target chip through an isolation module to solve the crosstalk between the interfaces, and then the communication speed of the SWD interface is effectively improved by running the driver of a dedicated high-speed SWD communication device.

[0111] Correspondingly, an embodiment of the utility model further provides a high-speed SWD communication device, which implements the above-mentioned high-speed communication interface circuit in a debugger to achieve rapid debugging and / or burning of a target chip.

[0112] like Figure 7 , which is a schematic diagram of the structure of a high-speed SWD communication device provided in an embodiment of the utility model.

[0113] The high-speed SWD communication device comprises a host 100 and a slave 200 . The host 100 comprises the high-speed communication interface circuit 10 , and data transmission with the SWD interface of the slave 200 is realized through the high-speed communication interface circuit 10 .

[0114] In actual applications, the host 100 can be a debugger, and the slave 200 can be a target chip installed on a development board. The GPIO interface of the host 100 is connected to the SWD interface of the target chip, one of the GPIO ports is a unidirectional transmission port, which is used for the host 100 to output a clock signal to the target chip, and the other GPIO port is a bidirectional transmission port, which is used for the host 100 to write data to the target chip or read data from the target chip.

[0115] The host 100 may also include a memory (not shown), which stores a driver, a debugging program and / or a program to be burned of the high-speed SWD communication device. Therefore, the host 100 can communicate with the target chip alone, or it can be connected to a PC 600 via a USB port, and the PC 600 provides real-time updated data to the host 100 via USB, and then the host 100 synchronously loads the real-time updated data to the target chip via the SWD interface.

[0116] Figure 8 Shows Figure 7 The figure shows a flow chart of data transmission during program debugging or burning of a target chip in a high-speed SWD communication device.

[0117] Also refer to Figure 7 , Figure 8 ,as well as Figure 3 , Figure 8 The process shown includes the following steps:

[0118] In step 601, the host 100 is started, each interface driver is initialized, and the GPIO interface is connected by default;

[0119] In step 602, the USB interface of the host 100 receives data from the PC;

[0120] In step 603, the host 100 determines whether the data of the PC is to be written to the target chip or read from the target chip; if it is to be written, step 620 is executed; otherwise, step 604 is executed;

[0121] In steps 620-625, the host 100 sends a write request to the target chip through the SPI1 interface (bit0-bit7 of the SWD protocol); specifically, first disconnect the GPIO channel and open the SPI1 channel, the host 100 sends a write request to the target chip through the SPI1 channel, then disconnect the SPI1 channel and open the GPIO channel;

[0122] In step 626, the host 100 sends a turnaround period Tm to the slave 200;

[0123] In step 627, the host 100 determines the response of the target chip; if it is OK, execute step 628; otherwise, execute step 640;

[0124] In step 628, the host 100 sends a turnaround period Tm to the slave 200;

[0125] In step 629, the isolation modules of GPIO_CLK and GPIO_DATA are turned off, thereby disconnecting the GPIO interface from the target chip, that is, disconnecting the GPIO channel;

[0126] In step 630, the isolation modules of SPI1_CLK and SPI1_DATA_OUT are turned on, thereby connecting the first SPI interface with the target chip, that is, turning on the SPI1 channel;

[0127] In step 631, the host 100 sends 32-bit batch data to the target chip via the first SPI interface;

[0128] After the data is sent, in step 632, the connection between the first SPI interface and the target chip is disconnected, that is, the SPI1 channel is disconnected.

[0129] In step 633, the host 100 calculates the checksum of the sent 32-bit batch data;

[0130] In step 634, the isolation modules of GPIO_CLK and GPIO_DATA are reopened to restore the connection between the GPIO interface and the target chip, that is, the GPIO channel is opened;

[0131] In step 635, the host 100 sends a check bit to the target chip via the GPIO channel;

[0132] In step 636, the target chip determines whether the check bit is correct and updates the result to the write status bit (WDATAERR). If the check bit is wrong, the next time the host 100 attempts to send a request to the target chip, it will respond with Fault (failure). After receiving the Fault, the host 100 will immediately read the status bit of the target chip, find the exception, clear the exception, and resend the write request.

[0133] In steps 604 to 609, the host 100 sends a read request (bit 0 to bit 7 of the SWD protocol) to the target chip through the SPI1 interface; specifically, first disconnect the GPIO channel and open the SPI1 channel, the host 100 sends a read request to the target chip through the SPI1 channel, then disconnect the SPI1 channel and open the GPIO channel;

[0134] In step 610, the host 100 sends a turnaround period Tm to the slave 200;

[0135] In step 611, the host 100 determines the response of the target chip; if it is OK, execute step 612; otherwise, execute step 640;

[0136] In step 612, the isolation modules of GPIO_CLK and GPIO_DATA are turned off, thereby disconnecting the GPIO interface from the target chip, that is, disconnecting the GPIO channel;

[0137] In step 613, the isolation modules of SPI2_CLK and SPI2_DATA_IN are turned on, thereby connecting the second SPI interface with the target chip, that is, turning on the SPI2 channel;

[0138] In step 614, the host 100 receives 32-bit batch data from the target chip through the second SPI interface;

[0139] After the data is received, in step 615, the connection between the second SPI interface and the target chip is disconnected, that is, the SPI2 channel is disconnected;

[0140] In step 616, the host 100 calculates the checksum of the received 32-bit batch data;

[0141] In step 617, the isolation modules of GPIO_CLK and GPIO_DATA are reopened to restore the connection between the GPIO interface and the target chip, that is, the GPIO channel is opened;

[0142] In step 618, the host 100 receives the check bit of the target chip through the GPIO channel;

[0143] In step 619, the host 100 compares the calculated check digit with the received check digit to see if they are consistent; if yes, the process ends; otherwise, the process proceeds to step 640;

[0144] In step 640 , the host 100 reports an error to the PC 600 .

[0145] It should be noted that in the above process, the default connection state is maintained at the GPIO interface connection. When speed needs to be increased, the GPIO interface that needs to be accelerated is switched to the SPI interface. The SPI interface can be a single group or multiple groups, without limitation. The above process describes the workflow in the case of two groups of SPI.

[0146] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0147] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0148] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0149] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A high-speed communication interface circuit, characterized in that: include: A host processor disposed on the host, and a GPIO interface, a first SPI interface, and a second SPI interface respectively connected to the host processor signal; The GPIO interface, the first SPI interface and the second SPI interface are respectively connected to the SWD interface of the slave through an isolation module and perform data transmission; The GPIO interface and the first SPI interface are configured to be controlled by the host processor and send data to the SWD interface of the slave; The GPIO interface and the second SPI interface are configured to be controlled by the host processor and receive data from the SWD interface of the slave.

2. The high-speed communication interface circuit according to claim 1, characterized in that: The connection line between the host and the slave includes a SWD clock line and a SWD data line; The SWD clock line is respectively connected to the clock line of the GPIO interface, the clock line of the first SPI interface and the clock line of the second SPI interface after passing through the first node; The SWD data line is respectively connected to the data line of the GPIO interface, the data line of the first SPI interface and the data line of the second SPI interface after passing through the second node.

3. The high-speed communication interface circuit according to claim 2, characterized in that: The SWD clock line is connected to the clock line of the GPIO interface, the clock line of the first SPI interface and the clock line of the second SPI interface in an isolated manner, including: The clock line of the GPIO interface, the clock line of the first SPI interface, and the clock line of the second SPI interface are each connected to the first node through an isolation module, and are used to output a clock signal to the first node in a time-division multiplexing manner.

4. The high-speed communication interface circuit according to claim 3, characterized in that: The GPIO interface clock line is used to output a control clock signal to the first node after the isolation module connected thereto is enabled; The clock line of the first SPI interface is used to output a write clock signal to the first node after the isolation module connected thereto is enabled; The clock line of the second SPI interface is used to output a read clock signal to the first node after the isolation module connected thereto is enabled; The frequencies of the write clock signal, the read clock signal, and the control clock signal are the same or different.

5. The high-speed communication interface circuit according to claim 4, characterized in that: The SWD data line is connected to the data line of the GPIO interface, the data line of the first SPI interface and the data line of the second SPI interface in an isolated manner, including: The data line of the GPIO interface, the data line of the first SPI interface, and the data line of the second SPI interface are each connected to a second node through an isolation module.

6. The high-speed communication interface circuit according to claim 5, characterized in that: The data line of the GPIO interface is in input-output mode, the data line of the first SPI interface is in single-line output mode, and the data line of the second SPI interface is in single-line input mode; The data line of the GPIO interface is used to send and receive data to the second node after the isolation module connected thereto is enabled; The data line of the first SPI interface is a data output terminal of the first SPI interface, and is used to send data to the second node after the isolation module connected thereto is enabled; The data line of the second SPI interface is a data input terminal of the second SPI interface, and is used to receive data from the second node after the isolation module connected thereto is enabled.

7. The high-speed communication interface circuit according to claim 1, characterized in that: The GPIO interface and the first SPI interface are also configured to be controlled by the host processor and send a request packet to the SWD interface of the slave.

8. The high-speed communication interface circuit according to any one of claims 1 to 7, characterized in that: The isolation module is arranged in the GPIO interface, the first SPI interface and the second SPI interface.

9. The high-speed communication interface circuit according to any one of claims 1 to 7, characterized in that: The isolation module is arranged outside the GPIO interface, the first SPI interface and the second SPI interface; the circuit further comprises: an enable signal output interface; The host processor is further used to generate an enable signal corresponding to each isolation module, and output the enable signal to the corresponding isolation module through the enable signal output interface.

10. The high-speed communication interface circuit according to claim 9, characterized in that: The enable signal output interface is a common IO interface.

11. A high-speed SWD communication device, characterized in that: The device comprises: a host and a slave, wherein the host comprises the high-speed communication interface circuit according to any one of claims 1 to 10.

12. The high-speed SWD communication device according to claim 11, characterized in that: The host further comprises: a memory storing a driver program, a debugging program and / or a program to be burned of the high-speed SWD communication device; The host processor of the host implements debugging and / or burning of the slave by loading and running the driver, debugging program and / or program to be burned of the high-speed SWD communication device.

Images