Data clock recovery circuit, phase selection interpolation circuit thereof and electronic equipment
By designing a phase selection interpolation circuit including N-channel tail current tube and phase selection unit in the data clock recovery circuit, the clock jitter problem in traditional circuits is solved, and high-precision clock recovery and low bit error rate are achieved.
Patent Information
- Application Number
- CN202420476997.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-12
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-03-12
AI Technical Summary
The phase selection interpolation circuit in the traditional data clock recovery circuit has clock jitter problems, resulting in nonlinearity and error of the clock recovery signal, affecting the transmission rate and bit error rate.
Design a phase selection interpolation circuit, including two phase selection circuits and one phase interpolation circuit, each phase selection circuit includes N-channel tail current tube, phase selection unit, current source circuit and comparison circuit, and adjust tail current bias through negative feedback Set the voltage to ensure the stability of the common mode voltage of the output signal, and realize linear interpolation and high-precision phase recovery.
Effectively reduce phase jitter of the clock signal, ensure the linear triangular wave characteristics of the output signal, improve clock recovery accuracy, and reduce bit error rate.
Smart Images
Figure CN222366265U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of data clock recovery, and in particular relates to a data clock recovery circuit and a phase selection interpolation circuit and electronic equipment thereof. Background Art
[0002] The clock data recovery circuit (CDR) is an important component of the transmitter in the serializer system. The quality of the recovered clock directly affects the data collection of the transmitter, and further affects the core indicators such as transmission rate and bit error rate. The phase selector / phase interpolator (PS-PI) is a key module in the data clock recovery circuit. Its interpolation accuracy has a great influence on the output clock quality of the data clock recovery circuit.
[0003] The phase selection interpolation circuit includes two phase selection circuits and a phase interpolation circuit. The phase selection circuit receives multiple clock signals, selects and outputs two of the clock signals through a coding signal, and outputs the clock signals to the phase interpolation circuit. The phase interpolation circuit linearly interpolates the two received clock signals, thereby outputting a clock signal whose phase is between the two clock signals.
[0004] Among them, the conventional phase selection circuit is as follows Figure 1 As shown, when SA=0001, the two leftmost transistors are turned on. At this time, the clock signal output by the phase selection circuit is a clock signal with the same phase as CLK90, where CLKX is a phase difference of X degrees from the reference clock. Figure 2 is the waveform of each signal end when the phase selection circuit and the phase interpolation circuit are working, where CKa and CKb are the clock signals output by the two phase selection circuits, and CKO is the clock signal output by the phase interpolation circuit. Since the load in the phase selection circuit is a resistor, the output node waveform satisfies the RC charging characteristic, that is, first fast and then slow, thus introducing the nonlinearity of the output signal. This nonlinearity will cause errors in phase interpolation, such as Figure 3 As shown, this ultimately results in an increase in the jitter of the clock signal output by the clock recovery circuit. Utility Model Content
[0005] The utility model aims to provide a phase selection interpolation circuit, aiming to solve the problem of clock jitter in a traditional data clock recovery circuit.
[0006] A first aspect of an embodiment of the utility model provides a phase selection interpolation circuit of a data clock recovery circuit, comprising:
[0007] Two phase selection circuits are respectively connected to the controller of the data clock recovery circuit, each of the phase selection circuits is used to select and output one first clock signal among N received first clock signals with different phases according to the first coded signal output by the controller, wherein N≥2;
[0008] Wherein, the phase selection circuit comprises:
[0009] N first tail current tubes, used to output tail currents of corresponding magnitude according to a first bias voltage, wherein the tail currents vary in a positive correlation with the first bias voltage;
[0010] N phase selection units, each of which is connected to one of the first tail current tubes and two output ends of the phase selection circuit, and every two of the phase selection units receive the same two first clock signals. The N phase selection units receive the first coding signal, and each of the phase selection units is used to convert the two first clock signals into two output clock signals according to the first coding signal and output them to the two output ends of the phase selection circuit, and the output clock signals have the same frequency and the same phase as the first clock signal;
[0011] a current source circuit, the current source circuit being connected in series to two output terminals of the phase selection circuit, the current source circuit being used as a load of the phase selection circuit;
[0012] A comparison circuit, connected to the two output ends of the phase selection circuit and the N-way first tail current tube, for comparing the common mode voltage value of the two-way output clock signal with the reference voltage, and negatively feedback adjusting the magnitude of the first bias voltage;
[0013] The phase interpolation circuit is connected to the controller and the two phase selection circuits respectively, and is used to receive the two first clock signals output by the two phase selection circuits, and output the second clock signal after performing a weighted operation on the two received first clock signals according to the second coding signal output by the controller.
[0014] Optionally, the phase selection circuit receives N first clock signals, and the phase difference between the N first clock signals and the reference clock is k1*(360° / 2N), where k1 is 1, 3...2N-1;
[0015] Another phase selection circuit receives N first clock signals, and the phase difference between the N first clock signals and the reference clock is k2*(360° / 2N), where k2 is 2, 4...2N.
[0016] Optionally, N=4.
[0017] Optionally, the two phase selection units in each phase selection circuit receive two first clock signals, and the phase difference between the two first clock signals is 180°;
[0018] The other two phase selection units in each phase selection circuit receive another first clock signal, and the phase difference between the two first clock signals is 180°.
[0019] Optionally, the phase selection unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
[0020] The first end of the first transistor, the first end of the second transistor and the first end of the first tail current tube are connected, the second end of the first transistor is connected to the first end of the third transistor, the second end of the second transistor is connected to the first end of the third transistor, the control end of the first transistor and the control end of the second transistor respectively receive a first clock signal, and the first clock signals received by the first transistor and the second transistor differ in phase by 180°;
[0021] The second end of the third transistor and the second end of the fourth transistor are respectively connected to the current source circuit, and the second end of the third transistor is connected to the second end of the fourth transistor of another phase selection unit that receives the same two first clock signals, and the second end of the fourth transistor is connected to the second end of the third transistor of another phase selection unit that receives the same two first clock signals.
[0022] Optionally, the current source circuit includes a fifth transistor, a sixth transistor, a seventh transistor and a current source;
[0023] The first end of the fifth transistor, the first end of the sixth transistor and the first end of the seventh transistor are connected to the positive power supply end, the control end of the fifth transistor, the second end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are connected to a current source, and the second end of the sixth transistor and the second end of the seventh transistor are respectively connected to the two output ends of the phase selection circuit.
[0024] Optionally, the comparison circuit includes a first resistor, a second resistor and a comparator;
[0025] The first end of the first resistor and the first end of the second resistor are connected to the first end of the sixth transistor and the first end of the seventh transistor respectively, the second end of the first resistor, the second end of the second resistor and the non-inverting input end of the comparator are connected, the inverting input end of the comparator is used to input a reference voltage, and the output end of the comparator is connected to the control end of each first tail current tube respectively.
[0026] Optionally, the phase interpolation circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a second tail current tube, a third tail current tube, a third resistor and a fourth resistor;
[0027] The first end of the eighth transistor and the first end of the ninth transistor are connected to the first end of the second tail current tube, the control end of the second tail current tube is used to receive the second bias voltage, the second end of the second tail current tube is grounded, the control end of the eighth transistor and the control end of the ninth transistor are respectively connected to the two output ends of one of the phase selection circuits, the second end of the eighth transistor is connected to the first end of the tenth transistor, the second end of the ninth transistor is connected to the second end of the eleventh transistor, the control end of the tenth transistor and the control end of the eleventh transistor are used to receive the second coding signal, the second end of the tenth transistor and the second end of the fourteenth transistor are connected to the first end of the third resistor, the second end of the eleventh transistor and the second end of the fifteenth transistor are connected to the first end of the fourth resistor, and the second end of the third resistor and the second end of the fourth resistor are connected to the positive power supply end;
[0028] The first end of the twelfth transistor, the first end of the thirteenth transistor and the first end of the third tail current tube are connected, the control end of the third tail current tube is used to receive a second bias voltage, the second end of the third tail current tube is grounded, the control end of the twelfth transistor and the control end of the thirteenth transistor are respectively connected to the two output ends of another phase selection circuit, the second end of the twelfth transistor is connected to the first end of the fourteenth transistor, and the second end of the thirteenth transistor is connected to the second end of the fifteenth transistor.
[0029] A second aspect of the embodiments of the present utility model provides a data clock recovery circuit, comprising the phase selection interpolation circuit as described above.
[0030] A third aspect of the embodiments of the present utility model provides an electronic device, comprising the data clock recovery circuit as described above.
[0031] Compared with the prior art, the beneficial effects of the embodiments of the utility model are as follows: the above-mentioned phase selection interpolation circuit includes two phase selection circuits and one phase interpolation circuit, each phase selection circuit includes N first tail current tubes, N phase selection units, a current source circuit and a comparison circuit, the load selection current source circuit of the phase selection circuit, the comparison circuit compares the common-mode voltage value of the two output clock signals output by the phase selection unit with the reference voltage, and negatively feedback adjusts the first bias voltage of the tail current tube so that the common-mode voltage value is equal to the reference voltage, ensuring the stability of the common-mode point of the output signal, thereby making the tail current of the tail current tube equal to the current of the current source circuit, and the output waveform becomes a linear triangular wave, realizing linear interpolation, ensuring the output phase accuracy, and reducing the phase jitter of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0033] Figure 1 is a circuit diagram of a conventional phase selection circuit;
[0034] Figure 2 A schematic diagram of waveforms of various signals of a conventional phase selection interpolation circuit;
[0035] Figure 3 It is a waveform diagram of a conventional phase interpolation circuit during phase interpolation;
[0036] Figure 4 A schematic diagram of the structure of a phase selection interpolation circuit provided in an embodiment of the utility model;
[0037] Figure 5 A schematic diagram of the structure of a first phase selection circuit provided in an embodiment of the utility model;
[0038] Figure 6 A schematic diagram of the structure of a second phase selection circuit provided in an embodiment of the utility model;
[0039] Figure 7 A circuit diagram of a first phase selection circuit provided by an embodiment of the utility model;
[0040] Figure 8 A circuit diagram of a second phase selection circuit provided in an embodiment of the utility model;
[0041] Fig. 9A circuit diagram of a phase interpolation circuit provided in an embodiment of the utility model;
[0042] Fig.10 A schematic diagram of waveforms during phase interpolation of a phase interpolation circuit provided in an embodiment of the utility model;
[0043] Fig.11 A schematic diagram of the structure of a data clock recovery circuit provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0046] The first aspect of an embodiment of the utility model proposes a phase selection interpolation circuit 100 of a data clock recovery circuit. The data clock recovery circuit also includes a controller, which is used to output a coded signal to a corresponding module in the phase selection interpolation circuit 100 to selectively interpolate and output a clock signal input by the phase selection interpolation circuit 100.
[0047] like Figure 4 As shown, the phase selection interpolation circuit 100 includes two phase selection circuits 10 and one phase interpolation circuit 20, the two phase selection circuits 10 are respectively connected to the controller of the data clock recovery circuit, and each phase selection circuit 10 is used to select and output one of the received N first clock signals with different phases according to the first coding signal SA or SB output by the controller, wherein N≥2;
[0048] The phase interpolation circuit 20 is respectively connected to the controller and the two phase selection circuits 10, and is used to receive the two first clock signals output by the two phase selection circuits 10, and output the second clock signal CKO after performing weighted operation on the two received first clock signals according to the second coding signal PI output by the controller.
[0049] Among them, the phases of the first clock signals received by each phase selection circuit 10 are different, and each phase selection circuit 10 receives N first clock signals with different phase differences corresponding to the reference clock. For example, one of the phase selection circuits 10 receives four first clock signals with phase differences of 90°, 180°, 270°, and 360° from the reference clock, and the other phase selection circuit 10 receives four first clock signals with phase differences of 45°, 135°, 225°, and 315° from the reference clock. The phase of each first clock signal can be set according to the needs, and the phase difference with the reference clock can be set in an arithmetic progression or in other settings, and the specific size and change rule are not limited.
[0050] In an optional embodiment, a phase selection circuit 10 receives N first clock signals, each of which has a phase difference of k1*(360° / 2N) with the reference clock, where k1 is 1, 3...2N-1;
[0051] Another phase selection circuit 10 receives N first clock signals, each of which has a phase difference of k2*(360° / 2N) with the reference clock, where k2 is 2, 4 . . . 2N.
[0052] In this embodiment, the phase difference between the phase of each first clock signal and the reference clock is arranged in an arithmetic progression. When N is equal to 4, one phase selection circuit 10 receives four first clock signals whose phase differences with the reference clock are 90°, 180°, 270°, and 360°, respectively, and the other phase selection circuit 10 receives four first clock signals whose phase differences with the reference clock are 45°, 135°, 225°, and 315°, respectively.
[0053] When N is equal to 6, one phase selection circuit 10 receives six first clock signals whose phase differences with the reference clock are 30°, 90°, 150°, 210°, 270°, and 330°, respectively, and the other phase selection circuit 10 receives six first clock signals whose phase differences with the reference clock are 60°, 120°, 180°, 240°, 300°, and 360°, respectively.
[0054] The value of N can be set according to the requirements. In an optional embodiment, in order to simplify the circuit structure and logic operation, N=4.
[0055] The first coding signal SA or SB received by each phase selection circuit 10 may be the same or different. The phase selection circuit 10 selects one of the input first clock signals for output according to the received first coding signal SA or SB. For example, when the first coding signal SA received by the first phase selection circuit 10 is 0001, the first first clock signal CLK1 is selected for output; when the first coding signal SA is 0010, the second first clock signal CLK2 is selected for output, thereby selecting and outputting the corresponding first clock signals from the first first clock signal CLK1 to the fourth first clock signal CLK4.
[0056] When the first coding signal SA received by the second phase selection circuit 10 is 0001, the fifth first clock signal CLK5 is selected to be output. When the first coding signal SA is 0010, the sixth first clock signal CLK6 is selected to be output, thereby selecting and outputting the corresponding first clock signals from the fifth to the eighth first clock signals.
[0057] Each phase selection circuit 10 selects and outputs a first clock signal with a different phase. For example, two phase selection circuits 10 respectively select and output two first clock signals with a phase difference of 90° and 45° with the reference clock.
[0058] The phase interpolation circuit 20 performs linear interpolation on the two first clock signals according to the received second coding signal PI, thereby outputting a second clock signal CKO whose phase is between the two inputs. For example, after weighted operation, the phase difference between the output second clock signal CKO and the reference clock is 60°.
[0059] Among them, Figure 5 and Figure 6 As shown, in this embodiment, the phase selection circuit 10 includes:
[0060] N first tail current tubes M01, used for outputting tail currents of corresponding magnitude according to the first bias voltage Vbias1, and the tail currents change in a positive correlation with the first bias voltage Vbias1;
[0061] N phase selection units 12, each phase selection unit 12 is connected to a first tail current tube M01 and two output ends of the phase selection circuit 10, every two phase selection units 12 receive the same two first clock signals, the N phase selection units 12 receive the first coding signal SA, each phase selection unit 12 is used to convert the two first clock signals into two output clock signals according to the first coding signal SA and output them to the two output ends of the phase selection circuit 10, and the output clock signals have the same frequency and the same phase as the first clock signal;
[0062] A current source circuit 13, the current source circuit 13 is connected in series to two output terminals of the phase selection circuit 10, and the current source circuit 13 is used as a load of the phase selection circuit 10;
[0063] The comparison circuit 14 is connected to the two output terminals of the phase selection circuit 10 and the N first tail current tubes M01, and is used to compare the common mode voltage value of the two output clock signals with the reference voltage Vcm, and negatively feedback adjust the magnitude of the first bias voltage Vbias1.
[0064] In this embodiment, when N=4, the phase selection circuit 10 includes four tail current tubes 11 and four phase selection units 12, each two phase selection units 12 form a unit group, and receive two first clock signals with different phases, for example Figure 5 As shown, the first phase selection unit 12 and the second phase selection unit 12 receive the first first clock signal CLK1 and the third first clock signal CLK3, the third phase selection unit 12 and the fourth phase selection unit 12 receive the second first clock signal CLK2 and the fourth first clock signal CLK4, and the two phase selection units 12 in the unit group are respectively turned on according to the received first coding signal SA, and one of the first clock signals is selected to be output. For example, when the first phase selection unit 12 and the second phase selection unit 12 receive the first coding signal SA as 0001, the first phase selection unit 12 is correspondingly turned on and time-sharingly selects to output the first first clock signal CLK1 and the second first clock signal CLK2; when the first phase selection unit 12 and the second phase selection unit 12 receive the first coding signal SA as 0010, the second phase selection unit 12 is correspondingly turned on and time-sharingly selects to output the first first clock signal CLK1 and the second first clock signal CLK2 to form an output clock signal.
[0065] The tail current tube 11 outputs a tail current that changes positively according to the size of the received first bias voltage Vbias1. When the phase selection unit 12 is turned on accordingly, the tail current is output to the current source circuit 13 through the phase selection unit 12. The current source circuit 13 serves as the load of the phase selection circuit 10. The tail current tube 11 charges the load. Under the triggering of different first clock signals and first coding signals SA, the on-time and off-time of the phase selection unit 12 change accordingly, thereby outputting two output clock signals with the same frequency and phase as the two first clock signals. The output clock signals have current characteristics and are converted into common-mode voltages through the current source circuit 13.
[0066] The two-way common-mode voltage changes in a positive correlation with the size of the output clock signal. The comparison circuit 14 compares the common-mode voltage value of the two-way output clock signal output by the phase selection unit 12 with the reference voltage Vcm, and negatively feedback adjusts the first bias voltage Vbias1 of the tail current tube 11. For example, when the current value of the two-way output clock signal is greater than the tail current, the terminal voltage of the current source circuit 13, that is, the common-mode voltage value, becomes larger, and the first bias voltage Vbias1 output by the comparison circuit 14 becomes larger, and the tail current increases; or when the current value of the two-way output clock signal is less than the tail current, the terminal voltage of the current source circuit 13, that is, the common-mode voltage value, becomes smaller, and the first bias voltage Vbias1 output by the comparison circuit 14 becomes smaller, and the tail current decreases, and finally the current value of the two-way output clock signal is equal to the tail current, and the common-mode voltage value is equal to the reference voltage Vcm, so as to ensure the stability of the common-mode point of the output signal. Fig.10 As shown, the output waveform of the phase selection unit 12 becomes a linear triangular wave, and the phase interpolation circuit 20 implements linear interpolation under the triggering of different second coding signals PI, thereby ensuring the output phase accuracy and reducing the phase jitter of the clock signal.
[0067] The phases of the two first clock signals received by the two phase selection units 12 of the unit group can be selected according to the requirements. In an optional embodiment, the output clock signal of the phase selection unit 12 is a clock signal of opposite levels. Correspondingly, the two phase selection units 12 in each phase selection circuit 10 receive the two first clock signals, and the phase difference between the two first clock signals is 180°.
[0068] The other two phase selection units 12 in each phase selection circuit 10 receive another first clock signal, and the phase difference between the two first clock signals is 180°.
[0069] For example, the first clock signal and the third clock signal received by the two phase selection units 12 in the unit group have a phase difference of 90° and 270° with the reference clock respectively, and the second clock signal and the fourth clock signal received by the two phase selection units 12 in the other unit group have a phase difference of 180° and 360° with the reference clock respectively, and the phase selection unit 12 outputs two output clock signals with opposite phases.
[0070] Among them, the phase selection unit 12 and the phase interpolation circuit 20 can select corresponding transistor structures, the current source circuit 13 can use corresponding transistors and current sources, the comparison circuit 14 can use the corresponding comparator U1 structure, and the tail current tube 11 can select an N-channel transistor according to the relationship between voltage and current.
[0071] In an alternative embodiment, if Figures 7 to 9 As shown, the phase selection unit 12 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4;
[0072] A first end of the first transistor M1, a first end of the second transistor M2 and a first end of a first tail current tube M01 are connected, a second end of the first transistor M1 is connected to a first end of the third transistor M3, a second end of the second transistor M2 is connected to a first end of the third transistor M3, a control end of the first transistor M1 and a control end of the second transistor M2 respectively receive a first clock signal, and a phase difference of the first clock signals received by the first transistor M1 and the second transistor M2 is 180°;
[0073] The second end of the third transistor M3 and the second end of the fourth transistor M4 are respectively connected to the current source circuit 13, and the second end of the third transistor M3 is connected to the second end of the fourth transistor M4 of another phase selection unit 12 that receives the same two first clock signals, and the second end of the fourth transistor M4 is connected to the second end of the third transistor M3 of another phase selection unit 12 that receives the same two first clock signals.
[0074] The current source circuit 13 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a current source I;
[0075] A first end of the fifth transistor M5, a first end of the sixth transistor M6, and a first end of the seventh transistor M7 are connected to the positive power supply end, a control end of the fifth transistor M5, a second end of the fifth transistor M5, a control end of the sixth transistor M6, and a control end of the seventh transistor M7 are connected to the current source I, and a second end of the sixth transistor M6 and a second end of the seventh transistor M7 are respectively connected to two output ends of the phase selection circuit 10.
[0076] The comparison circuit 14 includes a first resistor R1, a second resistor R2 and a comparator U1;
[0077] The first end of the first resistor R1 and the first end of the second resistor R2 are connected to the first end of the sixth transistor M6 and the first end of the seventh transistor M7 respectively, the second end of the first resistor R1, the second end of the second resistor R2 and the non-inverting input end of the comparator U1 are connected, the inverting input end of the comparator U1 is used to input the reference voltage Vcm, and the output end of the comparator U1 is connected to the control end of each first tail current tube M01 respectively.
[0078] The phase interpolation circuit 20 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a second tail current tube M02, a third tail current tube M03, a third resistor R3 and a fourth resistor R4;
[0079] The first end of the eighth transistor M8 and the first end of the ninth transistor M9 are connected to the first end of the second tail current tube M02, the control end of the second tail current tube M02 is used to receive the second bias voltage Vbias2, the second end of the second tail current tube M02 is grounded, the control end of the eighth transistor M8 and the control end of the ninth transistor M9 are respectively connected to the two output ends of one of the phase selection circuits 10, the second end of the eighth transistor M8 is connected to the first end of the tenth transistor M10, the second end of the ninth transistor M9 is connected to the second end of the eleventh transistor M11, the control end of the tenth transistor M10 and the control end of the eleventh transistor M11 are used to receive the second coding signal PI, the second end of the tenth transistor M10 and the second end of the fourteenth transistor M14 are connected to the first end of the third resistor R3, the second end of the eleventh transistor M11 and the second end of the fifteenth transistor M15 are connected to the first end of the fourth resistor R4, and the second end of the third resistor R3 and the second end of the fourth resistor R4 are connected to the positive power supply end;
[0080] A first end of the twelfth transistor M12, a first end of the thirteenth transistor M13 and a first end of the third tail current tube M03 are connected, a control end of the third tail current tube M03 is used to receive a second bias voltage Vbias2, a second end of the third tail current tube M03 is grounded, a control end of the twelfth transistor M12 and a control end of the thirteenth transistor M13 are respectively connected to two output ends of another phase selection circuit 10, a second end of the twelfth transistor M12 is connected to a first end of the fourteenth transistor M14, and a second end of the thirteenth transistor M13 is connected to a second end of the fifteenth transistor M15.
[0081] Taking the first phase selection circuit 10 as an example, the first phase selection circuit 10 receives the first first clock signal CLK1 to the fourth first clock signal CLK4. It is assumed that the first clock signal and the third clock signal have a phase difference of 90° and 270° with the reference clock, respectively, and the second clock signal and the fourth clock signal have a phase difference of 180° and 360° with the reference clock, respectively.
[0082] The third transistor M3 and the fourth transistor M4 of each phase selection unit 12 form a switch pair and are turned on respectively under the control of the first coding signal SA. For example, when the first coding signal SA is 0001, Figure 7 The leftmost switch pair is turned on, when the first coding signal SA is 0010, the second switch pair on the left is turned on, and when the first coding signal SA is 1000, the rightmost switch pair is turned on.
[0083] The fifth transistor M5 and the sixth transistor M6 form a current source bias circuit, the fifth transistor M5 and the seventh transistor M7 form a current source bias circuit, and the sixth transistor M6 and the seventh transistor M7 form a current source.
[0084] After the third transistor M3 and the fourth transistor M4 of one of the phase selection units 12 are turned on, the first transistor M1 and the second transistor M2 are turned on alternately according to the two received first clock signals, and the tail current tube 11 outputs a current signal through the first transistor M1 and the second transistor M2, that is, two output clock signals with opposite phases are formed, and the output clock signal is output to the sixth transistor M6 and the seventh transistor M7 of the current source circuit 13. Since the load becomes a current source, the output waveform of the phase selection circuit 10 becomes a linear triangular wave, and the output clock signal forms a common-mode voltage on the load side. The common-mode voltage is output to the comparator U1 through the first resistor R1 and the second resistor R2. The comparator U1 compares the common-mode voltage value with the reference voltage Vcm, and negatively feedback adjusts the tail current of the tail current tube 11, so that the sum of the current of the fifth transistor M5 and the current of the sixth transistor M6 is equal to the tail current.
[0085] For example, when the current value of the two-way output clock signal is greater than the tail current, the terminal voltage of the current source circuit 13, i.e., the common-mode voltage value, becomes larger, the first bias voltage Vbias1 output by the comparison circuit 14 becomes larger, and the tail current increases; or when the current value of the two-way output clock signal is less than the tail current, the terminal voltage of the current source circuit 13, i.e., the common-mode voltage value, becomes smaller, the first bias voltage Vbias1 output by the comparison circuit 14 becomes smaller, and the tail current decreases, and finally the current value of the two-way output clock signal is equal to the tail current, and the common-mode voltage value is equal to the reference voltage Vcm, so as to ensure the stability of the common-mode point of the output signal, such as Fig.10 As shown, the output waveform of the phase selection unit 12 becomes a linear triangular wave.
[0086] The tenth transistor M10 and the eleventh transistor M11 of the phase interpolation circuit 20 form a switch pair, and the fourteenth transistor M14 and the fifteenth transistor M15 form a switch pair. The tenth transistor M10 and the eleventh transistor M11 are correspondingly turned on or the fourteenth transistor M14 and the fifteenth transistor M15 are turned on when triggered by different second coding signals PI. The eighth transistor M8 and the ninth transistor M9 are correspondingly turned on when triggered by the two first clock signals output by one of the phase selection circuits 10, and the twelfth transistor M12 and the thirteenth transistor M13 are correspondingly turned on when triggered by the two first clock signals output by the other phase selection circuit 10, thereby realizing linear interpolation of two second clock signals CKO with opposite phases, ensuring output phase accuracy, and reducing phase jitter of the clock signal.
[0087] Compared with the prior art, the beneficial effects of the embodiment of the utility model are as follows: the above-mentioned phase selection interpolation circuit 100 includes two phase selection circuits 10 and one phase interpolation circuit 20, each phase selection circuit 10 includes N first tail current tubes M01, N phase selection units 12, current source circuits 13 and comparison circuits 14, the load of the phase selection circuit 10 selects the current source circuit 13, and the comparison circuit 14 compares the common-mode voltage value of the two output clock signals output by the phase selection unit 12 with the reference voltage Vcm, and negatively feedback adjusts the first bias voltage Vbias1 of the tail current tube 11 so that the common-mode voltage value is equal to the reference voltage Vcm, thereby ensuring the stability of the common-mode point of the output signal, thereby making the tail current of the tail current tube 11 equal to the current of the current source circuit 13, and the output waveform becomes a linear triangular wave, realizing linear interpolation, ensuring the output phase accuracy, and reducing the phase jitter of the clock signal.
[0088] The third aspect of the embodiments of the utility model proposes a data clock recovery circuit, which includes a phase selection interpolation circuit 100. The specific structure of the phase selection interpolation circuit 100 refers to the above embodiments. Since the data clock recovery circuit adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.
[0089] like Fig.11 As shown, the data clock recovery circuit also includes a Bang-Bang Phase Detector (BBPD), a UP / DN filter, a phase selection interpolation circuit 100, a controller and a reference clock. The reference clock provides four clock signals divided into two phase selection circuits 10. The two phase selection circuits 10 generate two output clock signals respectively according to the first coding signal SA of the controller. The phase interpolation circuit 20 performs phase interpolation operation on the two output clock signals according to the second coding signal PI to generate the second clock signal CKO. The Bang-Bang type phase detector compares the phase relationship between the data signal data and the second clock signal CKO to generate the corresponding leading up signal and lagging dn signal. The UP / DN filter generates UPF and DNF after filtering the up signal and the dn signal. The controller receives the UPF and DNF signals and generates coding signals for controlling the two PS and PI according to the second clock signal CKO. The data clock recovery circuit forms a phase-locked loop until the phase alignment of the second clock signal CKO and the data signal data reaches loop lock. At this time, the second clock signal CKO is the clock signal recovered from the data. The data signal data is further judged and re-timed to obtain the recovered data signal, i.e., Re_data.
[0090] The utility model also proposes an electronic device, which includes a data clock recovery circuit. The specific structure of the data clock recovery circuit refers to the above embodiment. Since the electronic device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.
[0091] In this embodiment, the electronic device may be an electronic device having a corresponding data clock recovery circuit, such as a serializer, an image sensor, and the like.
[0092] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.
Claims
1. A phase selection interpolation circuit for a data clock recovery circuit, characterized in that: include: Two phase selection circuits are respectively connected to the controller of the data clock recovery circuit, each of the phase selection circuits is used to select and output one first clock signal among N received first clock signals with different phases according to the first coded signal output by the controller, wherein N≥2; Wherein, the phase selection circuit comprises: N first tail current tubes, used to output tail currents of corresponding magnitude according to a first bias voltage, wherein the tail currents vary in a positive correlation with the first bias voltage; N phase selection units, each of which is connected to one of the first tail current tubes and two output ends of the phase selection circuit, and every two of the phase selection units receive the same two first clock signals. The N phase selection units receive the first coding signal, and each of the phase selection units is used to convert the two first clock signals into two output clock signals according to the first coding signal and output them to the two output ends of the phase selection circuit, and the output clock signals have the same frequency and the same phase as the first clock signal; a current source circuit, the current source circuit being connected in series to two output terminals of the phase selection circuit, the current source circuit being used as a load of the phase selection circuit; A comparison circuit, connected to the two output ends of the phase selection circuit and the N-way first tail current tube, for comparing the common mode voltage value of the two-way output clock signal with the reference voltage, and negatively feedback adjusting the magnitude of the first bias voltage; The phase interpolation circuit is connected to the controller and the two phase selection circuits respectively, and is used to receive the two first clock signals output by the two phase selection circuits, and output the second clock signal after performing a weighted operation on the two received first clock signals according to the second coding signal output by the controller.
2. The phase selection interpolation circuit of the data clock recovery circuit according to claim 1, characterized in that: The phase selection circuit receives N first clock signals, each of the N first clock signals has a phase difference of k1*(360° / 2N) with a reference clock, where k1 is 1, 3...2N-1; Another phase selection circuit receives N first clock signals, and the phase difference between the N first clock signals and the reference clock is k2*(360° / 2N), where k2 is 2, 4...2N.
3. The phase selection interpolation circuit of the data clock recovery circuit as claimed in claim 2, characterized in that: N＝4。 4. The phase selection interpolation circuit of the data clock recovery circuit according to claim 1, characterized in that: The two phase selection units in each phase selection circuit receive two first clock signals, and the phase difference between the two first clock signals is 180°; The other two phase selection units in each phase selection circuit receive another first clock signal, and the phase difference between the two first clock signals is 180°.
5. The phase selection interpolation circuit of the data clock recovery circuit as claimed in claim 4, characterized in that: The phase selection unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The first end of the first transistor, the first end of the second transistor and the first end of the first tail current tube are connected, the second end of the first transistor is connected to the first end of the third transistor, the second end of the second transistor is connected to the first end of the third transistor, the control end of the first transistor and the control end of the second transistor respectively receive a first clock signal, and the first clock signals received by the first transistor and the second transistor differ in phase by 180°; The second end of the third transistor and the second end of the fourth transistor are respectively connected to the current source circuit, and the second end of the third transistor is connected to the second end of the fourth transistor of another phase selection unit that receives the same two first clock signals, and the second end of the fourth transistor is connected to the second end of the third transistor of another phase selection unit that receives the same two first clock signals.
6. The phase selection interpolation circuit of the data clock recovery circuit as claimed in claim 4, characterized in that: The current source circuit includes a fifth transistor, a sixth transistor, a seventh transistor and a current source; The first end of the fifth transistor, the first end of the sixth transistor and the first end of the seventh transistor are connected to the positive power supply end, the control end of the fifth transistor, the second end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are connected to a current source, and the second end of the sixth transistor and the second end of the seventh transistor are respectively connected to the two output ends of the phase selection circuit.
7. The phase selection interpolation circuit of the data clock recovery circuit according to claim 6, characterized in that: The comparison circuit includes a first resistor, a second resistor and a comparator; The first end of the first resistor and the first end of the second resistor are connected to the first end of the sixth transistor and the first end of the seventh transistor respectively, the second end of the first resistor, the second end of the second resistor and the non-inverting input end of the comparator are connected, the inverting input end of the comparator is used to input a reference voltage, and the output end of the comparator is connected to the control end of each first tail current tube respectively.
8. The phase selection interpolation circuit of the data clock recovery circuit according to claim 1, characterized in that: The phase interpolation circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a second tail current tube, a third tail current tube, a third resistor and a fourth resistor; The first end of the eighth transistor and the first end of the ninth transistor are connected to the first end of the second tail current tube, the control end of the second tail current tube is used to receive the second bias voltage, the second end of the second tail current tube is grounded, the control end of the eighth transistor and the control end of the ninth transistor are respectively connected to the two output ends of one of the phase selection circuits, the second end of the eighth transistor is connected to the first end of the tenth transistor, the second end of the ninth transistor is connected to the second end of the eleventh transistor, the control end of the tenth transistor and the control end of the eleventh transistor are used to receive the second coding signal, the second end of the tenth transistor and the second end of the fourteenth transistor are connected to the first end of the third resistor, the second end of the eleventh transistor and the second end of the fifteenth transistor are connected to the first end of the fourth resistor, and the second end of the third resistor and the second end of the fourth resistor are connected to the positive power supply end; The first end of the twelfth transistor, the first end of the thirteenth transistor and the first end of the third tail current tube are connected, the control end of the third tail current tube is used to receive a second bias voltage, the second end of the third tail current tube is grounded, the control end of the twelfth transistor and the control end of the thirteenth transistor are respectively connected to the two output ends of another phase selection circuit, the second end of the twelfth transistor is connected to the first end of the fourteenth transistor, and the second end of the thirteenth transistor is connected to the second end of the fifteenth transistor.
9. A data clock recovery circuit, characterized in that: It comprises the phase selection interpolation circuit as described in any one of claims 1 to 8.
10. An electronic device, characterized in that: Comprising the data clock recovery circuit as claimed in claim 9.