Light emitting diode

Abstract

The utility model discloses a light emitting diode. The light emitting diode comprises a substrate; the epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked on the substrate from bottom to top; the first through hole penetrates through the second semiconductor layer and the light-emitting layer and exposes the first semiconductor layer; a dielectric film current barrier layer and an ohmic contact layer are sequentially formed above the second semiconductor layer; the ohmic contact layer and the peripheral part of the dielectric film current blocking layer have an overlapped part and are provided with a first opening for exposing the middle area of the dielectric film current blocking layer; the first insulating dielectric layer covers the dielectric film current barrier layer, the ohmic contact layer and the side wall of the first through hole; the second through hole penetrates through the first insulating dielectric layer; the second through holes and the first openings are arranged in a one-to-one correspondence manner; the electrode layer is positioned above the first insulating dielectric layer and is provided with a first electrode and a second electrode; the first electrode is electrically connected with the first semiconductor layer based on the first through hole; the second electrode is electrically connected with the ohmic contact layer based on the second through hole.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a light emitting diode (LED). Background Art

[0002] The traditional upright structure light-emitting diode adopts a step and extended electrode design. The performance of the light-emitting diode based on this design is affected by the current transmission and expansion in the P-type semiconductor layer and the N-type semiconductor layer. The current density away from the extended electrode decreases significantly, resulting in the performance of the light-emitting diode being limited.

[0003] The industry often uses inverted DBR (Distributed Bragg Reflector) structure light emitting diodes to replace upright structure light emitting diodes, thereby greatly improving the performance of light emitting diodes.

[0004] In a flip-chip DBR structured light-emitting diode, since the electrode needs to be electrically connected to the corresponding semiconductor layer based on a through hole, the limitation of process factors will lead to the sacrifice of a certain area of ​​the electrode high-reflection region, thereby affecting the light extraction efficiency of the light-emitting diode. Utility Model Content

[0005] In view of this, the present application provides a light emitting diode, the scheme is as follows:

[0006] In a first aspect, the present application provides a light emitting diode, comprising:

[0007] substrate;

[0008] The epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer which are sequentially stacked from bottom to top on the substrate;

[0009] A first through hole penetrates the second semiconductor layer and the light emitting layer to expose the first semiconductor layer;

[0010] A dielectric film current blocking layer and an ohmic contact layer are sequentially formed above the second semiconductor layer; the ohmic contact layer has an overlapping portion with the peripheral portion of the dielectric film current blocking layer, and has a first opening exposing the middle region of the dielectric film current blocking layer;

[0011] A first insulating dielectric layer covers the ohmic contact layer and the sidewall of the first through hole, and has a second opening exposing the bottom of the first through hole; a second through hole penetrating the first insulating dielectric layer; the second through hole and the first opening are arranged one by one opposite to each other;

[0012] The electrode layer located above the first insulating medium layer comprises a first electrode and a second electrode; the first electrode is electrically connected to the first semiconductor layer based on the first through hole; and the second electrode is electrically connected to the ohmic contact layer based on the second through hole.

[0013] Preferably, in the above light emitting diode, in a direction parallel to the plane where the substrate is located, the width of the overlapping portion ranges from 5 μm to 15 μm.

[0014] Preferably, in the above-mentioned light-emitting diode, the dielectric film current blocking layer is a single-layer insulating film;

[0015] Alternatively, the dielectric film current blocking layer is a first DBR layer having multiple layers of insulating films.

[0016] Preferably, in the above-mentioned light-emitting diode, the first insulating dielectric layer is a single-layer insulating film;

[0017] Alternatively, the first insulating dielectric layer is a second DBR layer having multiple insulating films.

[0018] Preferably, in the above-mentioned light-emitting diode, there is a patterned metal interconnection layer between the electrode layer and the first insulating dielectric layer, the first electrode is electrically connected to the first semiconductor layer based on a portion of the metal interconnection layer, and the second electrode is electrically connected to the ohmic contact layer based on another portion of the metal interconnection layer.

[0019] Preferably, in the above-mentioned light-emitting diode, there is a second insulating dielectric layer between the metal interconnect layer and the electrode layer;

[0020] The metal interconnection layer includes: a first interconnection line, part of which is located in the first through hole and electrically connected to the first semiconductor layer; a second interconnection line, which is located above the ohmic contact layer and electrically connected to the ohmic contact layer based on the second through hole;

[0021] The first electrode is electrically in contact with the first interconnection line based on a first electrode hole penetrating the second insulating medium layer; the second electrode is electrically in contact with the second interconnection line based on a second electrode hole penetrating the second insulating medium layer.

[0022] Preferably, in the above-mentioned light-emitting diode, there are a plurality of first through holes and a plurality of second through holes;

[0023] The first interconnection lines in different first through holes are connected as a whole; and the second interconnection lines in different second through holes are connected as a whole.

[0024] Preferably, in the above light-emitting diode, the second interconnection line is in electrical contact with the ohmic contact layer at the first opening;

[0025] Alternatively, there is a first metal reflective layer between the first insulating dielectric layer and the ohmic contact layer; the first metal reflective layer at least covers the first opening and is electrically connected to the ohmic contact layer; wherein the second interconnection line is electrically connected to the ohmic contact layer through the first metal reflective layer.

[0026] Preferably, in the above light emitting diode, the first metal reflective layer also covers a portion of the ohmic contact layer outside the first opening.

[0027] Preferably, in the above-mentioned light-emitting diode, the bottom of the first through hole has a second metal reflective layer electrically in contact with the first semiconductor layer;

[0028] At the bottom of the first through hole, the first electrode is electrically connected to the first semiconductor layer based on the second metal reflective layer.

[0029] The second aspect of the present application also provides another light emitting diode, comprising:

[0030] substrate;

[0031] The epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially stacked from bottom to top on the surface of the substrate;

[0032] The epitaxial layer has a plurality of light-emitting units arranged in sequence; the light-emitting units have a step structure, the step structure sequentially penetrates the second semiconductor layer and the light-emitting layer to expose the first semiconductor layer; and a groove penetrating the epitaxial layer is provided between adjacent light-emitting units;

[0033] A dielectric film current blocking layer and an ohmic contact layer are sequentially formed on the second semiconductor layer of each light-emitting unit; for the same light-emitting unit, the ohmic contact layer and the peripheral portion of the dielectric film current blocking layer have an overlapping portion, and have a first opening exposing the middle region of the dielectric film current blocking layer;

[0034] A first insulating dielectric layer covers the ohmic contact layer of each light-emitting unit and the side wall of the step structure; the first insulating dielectric layer has a plurality of through holes penetrating the first insulating dielectric layer and arranged one by one opposite to the first opening;

[0035] A patterned metal interconnection layer, the metal interconnection layer is located on the surface of the first insulating dielectric layer, and at least two light-emitting units are connected in series in sequence based on a step structure; the metal interconnection layer is electrically connected to the ohmic contact layer based on a through hole arranged in the first insulating dielectric layer opposite to the first opening;

[0036] The electrode layer located on the side of the metal interconnect layer away from the epitaxial layer has a first electrode and a second electrode; for the light-emitting units connected in series, the first electrode is electrically connected to the first semiconductor layer of one light-emitting unit based on a step structure, and the second electrode is electrically connected to the ohmic contact layer of another light-emitting unit based on the metal interconnect layer.

[0037] Preferably, in the above light emitting diode, in a direction parallel to the plane where the substrate is located, the width of the overlapping portion ranges from 5 μm to 15 μm.

[0038] Preferably, in the above-mentioned light-emitting diode, the dielectric film current blocking layer is a single-layer insulating film;

[0039] Alternatively, the dielectric film current blocking layer is a first DBR layer having multiple layers of insulating films.

[0040] Preferably, in the above-mentioned light emitting diode, the at least two light emitting units include: a first-order light emitting unit to an M-th-order light emitting unit, where M is a positive integer greater than 1;

[0041] The metal interconnection layer includes: a 1st-level interconnection line to an Mth-level interconnection line; a jth-level interconnection line is located above the jth-level light-emitting unit and is electrically connected to the ohmic contact layer of the jth-level light-emitting unit, where j is a positive integer not greater than M; an i+1th-level interconnection line is electrically connected to the first semiconductor layer of the ith-level light-emitting unit based on the step structure of the ith-level light-emitting unit, where i is a positive integer less than M;

[0042] The first electrode is electrically connected to the first semiconductor layer of the Mth-level light-emitting unit based on the step structure of the Mth-level light-emitting unit; and the second electrode is electrically connected to the first-level interconnection line.

[0043] Preferably, in the above-mentioned light-emitting diode, each light-emitting unit has a first through hole penetrating the second semiconductor layer and the light-emitting layer, and the first through hole exposes the first semiconductor layer;

[0044] The (i+1)th level interconnection line is also electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the first through hole.

[0045] Preferably, in the above-mentioned light-emitting diode, the first insulating dielectric layer also covers the sidewall of the first through hole and the bottom of the step structure;

[0046] A second opening penetrating the first insulating dielectric layer is provided at the bottom of the first through hole, and the (i+1)th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the second opening;

[0047] A third opening penetrating through the first insulating dielectric layer is provided at the bottom of the step structure, and the i+1th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the third opening;

[0048] The through holes in the first insulating medium layer arranged one-to-one opposite to the first openings are second through holes; the j-th level interconnection line is electrically connected to the ohmic contact layer of the j-th level light-emitting unit based on the second through holes.

[0049] Preferably, in the above-mentioned light-emitting diode, the first insulating dielectric layer is a single-layer insulating film;

[0050] Alternatively, the first insulating dielectric layer is a second DBR layer having multiple insulating films.

[0051] Preferably, in the above-mentioned light-emitting diode, the j-th level interconnection line is in electrical contact with the ohmic contact layer of the j-th level light-emitting unit;

[0052] Or, it also includes: a first metal reflective layer located between the first insulating medium layer and the ohmic contact layer; the first metal reflective layer at least covers the first opening and is electrically connected to the ohmic contact layer; wherein the j-th level interconnection line is electrically connected to the ohmic contact layer through the first metal reflective layer.

[0053] Preferably, in the above light emitting diode, the first metal reflective layer also covers a portion of the ohmic contact layer outside the first opening.

[0054] Preferably, in the above-mentioned light-emitting diode, the bottom of the first through hole has a second metal reflective layer electrically in contact with the first semiconductor layer; the i+1th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light-emitting unit based on the second metal reflective layer;

[0055] And / or, the bottom of the step structure has a third metal reflective layer electrically in contact with the first semiconductor layer; the i+1th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light-emitting unit based on the third metal reflective layer; the first electrode is electrically connected to the first semiconductor layer of the M-th level light-emitting unit based on the third metal reflective layer.

[0056] Preferably, in the above-mentioned light-emitting diode, there is a second insulating dielectric layer between the metal interconnect layer and the electrode layer;

[0057] A first electrode hole penetrating the second insulating medium layer is provided at the bottom of the step structure of the M-th light-emitting unit, and the first electrode is electrically connected to the first semiconductor layer of the M-th light-emitting unit based on the first electrode hole;

[0058] A second electrode hole penetrating through the second insulating medium layer is provided above the first-level interconnection line, and the second electrode is electrically contacted with the first-level interconnection line based on the second electrode hole.

[0059] Preferably, in the above light emitting diode, the first insulating dielectric layer also covers the surface of the step structure and fills the groove.

[0060] It can be seen from the above description that in the light-emitting diode provided by the technical solution of the present application, a dielectric film current blocking layer is arranged below the second through hole to block the current accumulation below the second through hole, so that the current can extend to the epitaxial layer in the area outside the second through hole through the ohmic contact layer, and can block the current from diffusing toward the bottom of the second through hole, that is, block the current flowing to the light-emitting layer below the second through hole, improve the current uniformity inside the device, avoid the problem of quantum efficiency reduction caused by excessive local current density, thereby improving the luminous efficiency of the light-emitting diode; and, since the dielectric film current blocking layer can guide the current to the area away from the second through hole, it can not only reduce the current crowding and electric field strength below the second through hole, but also reduce heat accumulation and improve device reliability; in addition, since the ohmic contact layer does not cover the entire surface of the second semiconductor layer, but a first opening is arranged above the dielectric film current blocking layer, the absorption of light by the ohmic contact layer can be reduced.

[0061] Furthermore, the dielectric film current blocking layer can also form an omni-directional reflector (ODR) with the first metal reflective layer, or when the metal interconnection layer is in electrical contact with the ohmic contact layer at the second through hole, there is no need to set the first metal reflective layer. The dielectric film current blocking layer can form an omni-directional reflector with the metal interconnection layer, thereby improving the reflectivity at the second through hole position and further improving the light extraction efficiency of the light-emitting diode.

[0062] Furthermore, the first insulating medium layer can form an omnidirectional reflector with the metal interconnection layer to further improve the reflectivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0064] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0065] Figure 1 A schematic diagram of the structure of a light emitting diode provided in an embodiment of the present application;

[0066] Figure 2 for Figure 1 A partial enlarged view of the light emitting diode shown;

[0067] Figure 3 A top view of a metal interconnection layer provided in an embodiment of the present application;

[0068] Figure 4 A schematic diagram of the structure of another light emitting diode provided in an embodiment of the present application;

[0069] Figure 5 A schematic diagram of the structure of another light emitting diode provided in an embodiment of the present application;

[0070] Figure 6 for Figure 5 A top view of the epitaxial layers in the light emitting diode shown;

[0071] Figure 7 for Figure 5 A top view of a metal interconnect layer in the light emitting diode shown;

[0072] Figure 8-Figure 15 A schematic diagram of the product structure of a light emitting diode manufacturing method in different process steps provided in an embodiment of the present application;

[0073] Figure 16-Figure 23 A schematic diagram of the product structure at different process steps of another light emitting diode manufacturing method provided in an embodiment of the present application.

[0074] Reference numerals:

[0075] 100-substrate; 101-epitaxial layer; 102-dielectric film current blocking layer; 103-ohmic contact layer; 104-first metal reflective layer; 105-second metal reflective layer; 106-first insulating dielectric layer; 108-metal interconnection layer; 109-second insulating dielectric layer; 110-first electrode; 111-second electrode; 112-overlapping portion; 113-third metal reflective layer; 11-first semiconductor layer; 12-light emitting layer; 13-second semiconductor layer; 14-first through hole; 15-second through hole; 16-first opening; 17-first interconnection line; 18-second interconnection line; 19-light emitting unit; 20-groove; 21-second opening; 22-first electrode hole; 23-second electrode hole; 24-step structure; 25-third opening; L1-first level interconnection line; L2-second level interconnection line; L3-third level interconnection line; L M -M-th level interconnection line; L i+1 -i+1th level interconnection line; L j -j-th level interconnection line. DETAILED DESCRIPTION

[0076] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0077] As described in the background art, in a light-emitting diode with an inverted DBR structure, since the electrode needs to be electrically connected to the corresponding semiconductor layer based on a through hole, a certain area of ​​the electrode high reflection region is sacrificed, thereby affecting the light extraction efficiency of the light-emitting diode.

[0078] In order to solve the above problem, one way is to set a current blocking layer (CBL) at the position of the through hole connected to the P-type semiconductor layer to enhance the current expansion effect and improve the light extraction efficiency. Since the actual reflectivity of the through hole above the P-type semiconductor layer is lower than that of the area covered with the DBR film layer, this method cannot achieve the ideal light extraction efficiency.

[0079] Another method is to set a reflective layer including metal Al at the position of the through hole connected to the N-type semiconductor layer to increase the reflectivity. On the one hand, the reflectivity of this method is still lower than 90%. On the other hand, metal Al easily reacts with the oxygen element in the ITO film in the light-emitting diode to form an Al2O3 film, thereby causing the chip voltage to increase.

[0080] In view of this, the technical solution of the embodiment of the present application provides a light-emitting diode with low cost, high brightness and high reliability. By providing a dielectric film current blocking layer under the second through hole, the current gathering under the second through hole is blocked, so that the current can be extended to the epitaxial layer outside the second through hole through the ohmic contact layer, and the current can be blocked from diffusing toward the bottom of the second through hole, that is, the current flowing to the light-emitting layer under the second through hole is blocked, the current uniformity inside the device is improved, and the problem of quantum efficiency reduction caused by excessive local current density is avoided, thereby improving the luminous efficiency of the light-emitting diode; moreover, since the dielectric film current blocking layer can guide the current to the area far away from the second through hole, it can not only reduce the current crowding and electric field strength under the second through hole, but also reduce heat accumulation and improve device reliability; in addition, since the ohmic contact layer does not cover the entire surface of the second semiconductor layer, but a first opening is provided above the dielectric film current blocking layer, the absorption of light by the ohmic contact layer can be reduced.

[0081] Furthermore, the dielectric film current blocking layer can also form an omnidirectional reflector with the first metal reflective layer, or when the metal interconnection layer is in electrical contact with the ohmic contact layer at the second through hole, there is no need to set the first metal reflective layer. The dielectric film current blocking layer can form an omnidirectional reflector with the metal interconnection layer (whose underlying metal has a higher reflectivity), thereby improving the reflectivity at the second through hole position and further improving the light extraction efficiency of the light-emitting diode.

[0082] Furthermore, the first insulating medium layer can form an omnidirectional reflector with the metal interconnection layer to further improve the reflectivity.

[0083] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0084] refer to Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the structure of a light emitting diode provided in an embodiment of the present application is shown in FIG. Figure 2 for Figure 1 A partial enlarged view of the light emitting diode shown, wherein the light emitting diode shown comprises:

[0085] Substrate 100;

[0086] The epitaxial layer 101 includes a first semiconductor layer 11, a light emitting layer 12, and a second semiconductor layer 13 which are sequentially stacked from bottom to top on the substrate 100;

[0087] A first through hole 14, the first through hole 14 penetrates the second semiconductor layer 13 and the light emitting layer 12 to expose the first semiconductor layer 11;

[0088] A dielectric film current blocking layer 102 and an ohmic contact layer 103 are sequentially formed above the second semiconductor layer 13; the ohmic contact layer 103 has an overlapping portion 112 with the peripheral portion of the dielectric film current blocking layer 102, and has a first opening 16 exposing the middle region of the dielectric film current blocking layer 102;

[0089] A first insulating dielectric layer 106, the first insulating dielectric layer 106 covers the ohmic contact layer 103 and the sidewall of the first through hole 14, and has a second opening 21 exposing the bottom of the first through hole 14; a second through hole 15 penetrating the first insulating dielectric layer 106; the second through hole 15 and the first opening 16 are arranged one by one opposite to each other;

[0090] The electrode layer is located above the first insulating dielectric layer 106 , and has a first electrode 110 and a second electrode 111 . The first electrode 110 is electrically connected to the first semiconductor layer 11 based on the first through hole 14 ; the second electrode 111 is electrically connected to the ohmic contact layer 103 based on the second through hole 15 .

[0091] One of the first semiconductor layer 11 and the second semiconductor layer 13 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. For example, the first semiconductor layer 11 is an N-type semiconductor layer, and the second semiconductor layer 13 is a P-type semiconductor layer.

[0092] In the light-emitting diode provided in the embodiment of the present application, a dielectric film current blocking layer 102 is provided below the second through hole 15 to block the current gathering below the second through hole 15, so that the current can spread to the epitaxial layer 101 in the area outside the second through hole 15 through the ohmic contact layer 103, and can block the current from diffusing toward the bottom of the second through hole 15, that is, block the current flowing to the light-emitting layer 12 below the second through hole 15, improve the current uniformity inside the device, avoid the problem of quantum efficiency reduction caused by excessive local current density, and thus improve the luminous efficiency of the light-emitting diode; and, since the dielectric film current blocking layer 102 can guide the current to the area away from the second through hole 15, not only can the current crowding and electric field strength below the second through hole 15 be reduced, but also heat accumulation can be reduced and device reliability can be improved; in addition, since the ohmic contact layer 103 does not cover the entire surface of the second semiconductor layer 13, but a first opening 16 is provided above the dielectric film current blocking layer 102, the absorption of light by the ohmic contact layer 103 can be reduced.

[0093] Combination Figure 1 and Figure 2 As shown, the dielectric film current blocking layer 102 covers a portion of the second semiconductor layer 13, the ohmic contact layer 103 covers a portion of the second semiconductor layer 13 and the peripheral portion of the dielectric film current blocking layer 102, and the ohmic contact layer 103 has a first opening 16 exposing the dielectric film current blocking layer 102 in the middle region; in a direction parallel to the plane where the substrate 100 is located ( Figure 1 and Figure 2 In the lateral direction of the second semiconductor layer 13, the ohmic contact layer 103 and the dielectric film current blocking layer 102 have an overlapping portion 112. Since the ohmic contact layer 103 does not cover the entire surface of the second semiconductor layer 13, but a first opening 16 is provided above the dielectric film current blocking layer 102, the absorption of light by the ohmic contact layer 103 can be reduced.

[0094] The ohmic contact layer 103 and the dielectric film current blocking layer 102 are provided with an overlapping portion 112, that is, the lateral width of the first opening 16 is smaller than the lateral width of the dielectric film current blocking layer 102, and the surrounding area of ​​the surface of the dielectric film current blocking layer 102 facing away from the second semiconductor layer 13 is covered by the ohmic contact layer 103 to form the overlapping portion 112, which can better expand the current injected from the second through hole 15, improve the current crowding problem below the second through hole 15, reduce heat accumulation, and improve device reliability and light extraction efficiency.

[0095] Optionally, in a direction parallel to the plane where the substrate 100 is located ( Figure 1 and Figure 2 In the lateral direction of the first opening 16), the width of the overlapping portion 112 ranges from 5 μm to 15 μm. The width of the overlapping portion 112 is set to be not less than 5 μm to ensure the connection effect between the ohmic contact layer 103 and the metal material in the first opening 16 to achieve current conduction. The width of the overlapping portion 112 is set to be not more than 15 μm to avoid a large height difference and more light absorption caused by its excessive width. The ohmic contact layer 103 is generally a transparent conductive layer, and the dielectric film current blocking layer 102 is also a light-transmitting film layer. The ohmic contact layer 103 is generally an ITO film with a thickness range of 100 nm to 220 nm, which is relatively thick. Its transmittance is relatively low compared to the ultra-thin ITO film, and the light absorption loss is relatively large. In the embodiment of the present application, the ohmic contact layer 103 is set to cover part of the second semiconductor layer 13 and the dielectric film current blocking layer 102, and has a first opening 16 exposing the dielectric film current blocking layer 102, which avoids the relatively high light absorption problem caused by the ohmic contact layer 103 fully covering the surface of the second semiconductor layer 13.

[0096] In the embodiment of the present application, the dielectric film current blocking layer 102 is a single-layer insulating film, such as a layer of MgF2 film or SiO2 film with a low refractive index.

[0097] Or, the dielectric film current blocking layer 102 is a first DBR layer having multiple layers of insulating films. Based on the first DBR layer, the reflectivity can be improved, thereby improving the light extraction efficiency. The first DBR layer includes: a first high-low refractive index film stack, the first high-low refractive index film stack includes at least one high refractive index film and at least one low refractive index film, and the high refractive index film and the low refractive index film are alternately stacked. In the first high-low refractive index film stack, the high refractive index film can be a Nb2O5 film or a TiO2 film, and the low refractive index film can be a SiO2 film, but is not limited thereto.

[0098] The first DBR layer may also include a layer of Al2O3 film or HfO2 film with high light transmittance, and the Al2O3 film or HfO2 film is located on the surface of the first high-low refractive index film stack away from the second semiconductor layer 13. The surface of the dielectric film current blocking layer 102 away from the second semiconductor layer 13 is Al2O3 film or HfO2 film with high light transmittance, and the thickness of the Al2O3 film or HfO2 film is 5nm to 100nm.

[0099] In the first DBR layer, by adjusting the refractive index and film thickness of the high-refractive-index film and the low-refractive-index film, the first DBR layer can have one or more central reflection wavelengths. For example, the first DBR layer can be set to have a first central reflection wavelength and a second central reflection wavelength, and the spectrum of the light emitted by the light emitting diode is between the first central reflection wavelength and the second central reflection wavelength. In this way, the reflection band of the first DBR layer includes the wavelength range of the light emitting spectrum of the light emitting diode, which can achieve a better reflection effect. The first central reflection wavelength can be 400nm, and the second central reflection wavelength can be 620nm. For example, the first DBR layer has a large reflectivity for light with a wavelength of 400nm to 620nm, and the reflectivity is not less than 98%.

[0100] In the embodiment of the present application, a first insulating dielectric layer 106 is provided between the ohmic contact layer 103 and the electrode layer; wherein the first insulating dielectric layer 106 covers the sidewall and the bottom of the first through hole 14; at the bottom of the first through hole 14, there is a second opening 21 penetrating the first insulating dielectric layer 106, and the first electrode 110 is electrically connected to the first semiconductor layer 11 based on the first through hole 14. The first insulating dielectric layer 106 can be used to isolate the electrical connection structure in the first through hole 14 from the light-emitting layer 12 and the second semiconductor layer 13.

[0101] In one embodiment, the first insulating dielectric layer 106 may be a single-layer insulating film, such as a SiO2 film with a low refractive index.

[0102] In another embodiment, the first insulating dielectric layer 106 is a second DBR layer having multiple insulating films. In this embodiment, the second DBR layer includes: a second high-low refractive index film stack, the second high-low refractive index film stack includes at least one high refractive index film and at least one low refractive index film, and the high refractive index film and the low refractive index film are alternately stacked. In the second high-low refractive index film stack, the high refractive index film can be a TiO2 film, and the low refractive index film can be a SiO2 film, but is not limited thereto. The second DBR layer can also include a low refractive index dielectric film, and the second high-low refractive index film stack is located on the surface of the low refractive index dielectric film, that is, the second high-low refractive index film stack is located on the side of the low refractive index dielectric film away from the first semiconductor layer 11. The low refractive index dielectric film can be a SiO2 film.

[0103] like Figure 1 As shown, there is a patterned metal interconnection layer 108 between the electrode layer and the first insulating dielectric layer 106, the first electrode 110 is electrically connected to the first semiconductor layer 11 based on a part of the metal interconnection layer 108 (i.e., the first interconnection line 17 described below), and the second electrode 111 is electrically connected to the ohmic contact layer 103 based on another part of the metal interconnection layer 108 (i.e., the second interconnection line 18 described below), thereby achieving electrical connection with the second semiconductor layer 13.

[0104] refer to Figure 3 As shown, Figure 3 A top view of a metal interconnection layer provided in an embodiment of the present application, Figure 3 The middle dotted line corresponds to Figure 1 The cross-sectional position of the light-emitting diode shown, combined with Figure 1 and Figure 3 As shown, in the light-emitting diode, there is a second insulating dielectric layer 109 between the metal interconnection layer 108 and the electrode layer; the metal interconnection layer 108 includes: a first interconnection line 17, the first interconnection line 17 is partially located in the first through hole 14, and is electrically connected to the first semiconductor layer 11; a second interconnection line 18 is located above the ohmic contact layer 103, and is electrically connected to the ohmic contact layer 103 based on the second through hole 15; wherein the first electrode 110 is electrically in contact with the first interconnection line 17 based on the first electrode hole 22 that penetrates the second insulating dielectric layer 109; and the second electrode 111 is electrically in contact with the second interconnection line 18 based on the second electrode hole 23 that penetrates the second insulating dielectric layer 109.

[0105] The light emitting diode has a plurality of first through holes 14 and a plurality of second through holes 15 , wherein the first interconnection lines 17 in different first through holes 14 are connected as a whole, and the second interconnection lines 18 in different second through holes 15 are connected as a whole.

[0106] In one implementation of the present application, the Figure 1 As shown, a first metal reflective layer 104 is provided between the first insulating dielectric layer 106 and the ohmic contact layer 103; the first metal reflective layer 104 at least covers the first opening 16 and is electrically connected to the ohmic contact layer 103; wherein the second interconnection line 18 is electrically connected to the ohmic contact layer 103 through the first metal reflective layer 104. In this manner, the first metal reflective layer 104 is located on the ohmic contact layer 103 and the dielectric film current blocking layer 102, at least fills the first opening 16 and is in contact with the ohmic contact layer 103.

[0107] Optionally, the first metal reflective layer 104 includes an anti-oxidation metal film, which may be any one of an Ag film, an Rh film and a Pt film. The thickness of the anti-oxidation metal layer ranges from 60 nm to 500 nm.

[0108] When the first metal reflective layer 104 is provided, the dielectric film current blocking layer 102 can form an omnidirectional reflector with the first metal reflective layer 104, thereby improving the reflectivity at the position of the second through hole 15 and further improving the light extraction efficiency of the light emitting diode. The width value range of the overlapping portion 112 can be set to ensure the connection effect between the ohmic contact layer 103 and the metal material in the first opening 16 to achieve current conduction, while avoiding a large height difference caused by its excessive width.

[0109] The first metal reflective layer 104 at least fills the first opening 16 to be in electrical contact with the ohmic contact layer 103. The first metal reflective layer 104 also covers a portion of the ohmic contact layer 103 outside the first opening 16, that is, the first metal reflective layer 104 also extends outside the first opening 16 to cover a portion of the ohmic contact layer 103 to ensure electrical contact with the ohmic contact layer 103.

[0110] In the embodiment of the present application, the edge of the first metal reflective layer 104 and the overlapping portion 112 can be set to be flush or approximately flush based on the requirements. In this case, the edge of the first metal reflective layer 104 and the dielectric film current blocking layer 102 can be flush or approximately flush. Figure 1 and Figure 2 As shown, the edge of the first metal reflective layer 104 is set to exceed the edge of the overlapping portion 112 . At this time, the edge of the first metal reflective layer 104 exceeds the edge of the dielectric film current blocking layer 102 .

[0111] In another embodiment of the present application, a second interconnection line 18 may be provided in electrical contact with the ohmic contact layer 103 at the first opening 16. In this manner, there is no need to provide the first metal reflective layer 104, and the metal interconnection layer 108 is reused as the metal reflective layer. The dielectric film current blocking layer 102 can form an omnidirectional reflector with the metal interconnection layer 108, thereby improving the reflectivity and further improving the light extraction efficiency of the light-emitting diode. In this manner, the first interconnection line 17 located in the first through hole 14 can also improve the reflectivity at the position of the first through hole 14.

[0112] In the implementation of the present application, the first insulating dielectric layer 106 can form an omnidirectional reflector with the metal interconnect layer 108 to further improve the reflectivity.

[0113] refer to Figure 4 As shown, Figure 4 A schematic structural diagram of another light-emitting diode provided in an embodiment of the present application, based on any of the above-mentioned implementation modes, the bottom of the first through hole 14 has a second metal reflective layer 105 electrically in contact with the first semiconductor layer 11; at the bottom of the first through hole 14, the first electrode 110 is electrically connected to the first semiconductor layer 11 based on the second metal reflective layer 105.

[0114] The second metal reflective layer 105 is used to improve the reflectivity at the position of the first through hole 14, and is reused as an ohmic contact layer electrically connecting the first electrode 110 and the first semiconductor layer 11. The second metal reflective layer 105 can improve the reflectivity at the position of the first through hole 14, improve the light extraction efficiency of the light-emitting diode, and the second metal reflective layer 105 can also serve as an ohmic contact layer electrically connecting the first electrode 110 and the first semiconductor layer 11, thereby reducing the contact resistance.

[0115] In the embodiment of the present application, the second metal reflective layer 105 can be a single-layer metal film with high reflectivity or a stacked multi-layer composite metal film. Preferably, the second metal reflective layer 105 is a multi-layer metal film, which can achieve high reflectivity and also serve as a metal migration barrier.

[0116] Based on the high reflectivity of the first metal reflective layer 104 and the second metal reflective layer 105, the reflectivity of the light emitting diode at the through hole position can be improved, and the absorption of the light emitted by the light emitting diode at the through hole position can be reduced. In addition, the first metal reflective layer 104 and the second metal reflective layer 105 can be set to be a multi-layer metal film structure, and the multi-layer metal film structure includes a metal migration barrier film and an anti-oxidation film, which can improve the chip reliability.

[0117] As described below, in another embodiment of the present application, the epitaxial layer 101 can be divided into a plurality of light-emitting units 19, and at least two light-emitting units 19 can be connected in series through the metal interconnection layer 108 to increase the operating voltage of the light-emitting diode, thereby obtaining a high-voltage light-emitting diode.

[0118] refer to Figure 5 As shown, Figure 5 A schematic diagram of the structure of another light emitting diode provided in the embodiment of the present application, combined with Figure 2 and Figure 5 As shown, the light emitting diode shown comprises:

[0119] Substrate 100;

[0120] The epitaxial layer 101 includes a first semiconductor layer 11, a light emitting layer 12, and a second semiconductor layer 13 which are sequentially stacked from bottom to top on the surface of the substrate 100;

[0121] The epitaxial layer 101 has a plurality of light-emitting units 19 arranged in sequence; the light-emitting unit 19 has a step structure 24, and the step structure 24 sequentially penetrates the second semiconductor layer 13 and the light-emitting layer 12 to expose the first semiconductor layer 11; and a groove 20 penetrating the epitaxial layer 101 is provided between adjacent light-emitting units 19;

[0122] A dielectric film current blocking layer 102 and an ohmic contact layer 103 are sequentially formed on the second semiconductor layer 13 of each light emitting unit 19; for the same light emitting unit 19, the ohmic contact layer 103 and the peripheral portion of the dielectric film current blocking layer 102 have an overlapping portion 112, and the ohmic contact layer 103 has a first opening 16 exposing the middle region of the dielectric film current blocking layer 102;

[0123] A first insulating dielectric layer 106, the first insulating dielectric layer 106 covers the ohmic contact layer 103 of each light-emitting unit 19 and the side wall of the step structure 24; the first insulating dielectric layer 106 has a plurality of through holes (i.e., second through holes 15) penetrating the first insulating dielectric layer 106 and arranged one by one opposite to the first opening 16;

[0124] A patterned metal interconnection layer 108, the metal interconnection layer 108 is located on the surface of the first insulating dielectric layer 106, and at least two light-emitting units 19 are sequentially connected in series based on the step structure 24; the metal interconnection layer 108 is electrically connected to the ohmic contact layer 103 based on a through hole arranged in the first insulating dielectric layer 106 opposite to the first opening 16;

[0125] The electrode layer located on the side of the metal interconnect layer 108 away from the epitaxial layer 101 has a first electrode 110 and a second electrode 111; for the light-emitting units 19 connected in series, the first electrode 110 is electrically connected to the first semiconductor layer 11 of one light-emitting unit 19 based on the step structure 24, and the second electrode 111 is electrically connected to the ohmic contact layer 103 of another light-emitting unit 19 based on the metal interconnect layer 108.

[0126] Similarly, for Figure 5 In the high-voltage light-emitting diode shown in the figure, a dielectric film current blocking layer 102 is arranged under the second through hole 15 to block the current gathering under the second through hole 15, so that the current can spread to the epitaxial layer 101 in the area outside the second through hole 15 through the ohmic contact layer 103, and can block the current from diffusing toward the bottom of the second through hole 15, that is, block the current flowing to the light-emitting layer 12 under the second through hole 15, improve the internal current uniformity, avoid the problem of quantum efficiency reduction caused by excessive local current density, and thus improve the luminous efficiency of the light-emitting diode; and, because the dielectric The film current blocking layer 102 can guide the current to a region away from the second through hole 15, which can not only reduce the current crowding and electric field strength below the second through hole 15, but also reduce heat accumulation and improve device reliability; in addition, since the ohmic contact layer 103 does not cover the entire surface of the second semiconductor layer 12, but a first opening 16 is provided above the dielectric film current blocking layer 102, the absorption of light by the ohmic contact layer 103 can be reduced; in addition, the first insulating dielectric layer 106 can form an omnidirectional reflector with the metal interconnect layer 108 to further improve the reflectivity.

[0127] Optional, in Figure 5 The high-voltage light-emitting diode shown has an overlapping portion 112 with a width ranging from 5 μm to 15 μm in a direction parallel to the plane of the substrate 100, so as to ensure the connection between the ohmic contact layer 103 and the metal material in the first opening 16 to achieve current conduction while avoiding a large height difference caused by an excessive width.

[0128] Optional, in Figure 5 In the high-voltage light-emitting diode shown, the dielectric film current blocking layer 102 is a single-layer insulating film; or, the dielectric film current blocking layer 102 is a first DBR layer having multiple layers of insulating films. The implementation of the dielectric film current blocking layer 102 can refer to the description of the above embodiment, and will not be repeated in this embodiment.

[0129] exist Figure 5 The high-voltage light-emitting diode shown can form a groove 20 based on the step structure 24 to reduce the etching depth of the groove 20 , and the first semiconductor layer 11 in different light-emitting units 19 can be isolated through the groove 20 .

[0130] When the metal interconnect layer 108 connects at least two light-emitting units 19 in the light-emitting diode in series, the drawings of the embodiment of the present application illustrate three light-emitting units 19 connected in series. It should be noted that by setting the pattern structure of the metal interconnect layer 108, all the light-emitting units 19 in the light-emitting diode can be connected in series in sequence, or some of the light-emitting units 19 in the light-emitting diode can be connected in series and other parts of the light-emitting units 19 can be connected in parallel, which is not limited in the embodiment of the present application.

[0131] The at least two light-emitting units 19 connected in series by the metal interconnection layer 108 include: a first light-emitting unit to an Mth light-emitting unit, where M is a positive integer greater than 1; Figure 5 Take M=3 as an example for illustration. Figure 5 The three light emitting units 19 are the first light emitting unit, the second light emitting unit and the third light emitting unit from left to right. It is obvious that the number of light emitting units 19 in the light emitting diode can be set to any number based on the requirements, not limited to M=3, and M can be any positive integer greater than 1.

[0132] The metal interconnection layer 108 includes: first-level interconnection lines L1 to M-th-level interconnection lines L M ; The j-th level interconnection line L j Located above the j-th light-emitting unit, electrically connected to the ohmic contact layer 103 of the j-th light-emitting unit, where j is a positive integer not greater than M; the i+1-th interconnection line L i+1 The step structure 24 based on the i-th light emitting unit is electrically connected to the first semiconductor layer 11 of the i-th light emitting unit, where i is a positive integer less than M; wherein the first electrode 110 is electrically connected to the first semiconductor layer 11 of the M-th light emitting unit based on the step structure 24 of the M-th light emitting unit; and the second electrode 111 is electrically connected to the first-level interconnection line L1. In this way, the first light emitting unit to the M-th light emitting unit can be connected in series in sequence through the metal interconnection layer 108.

[0133] refer to Figure 6 and Figure 7 As shown, Figure 6 for Figure 5A top view of the epitaxial layers in the light emitting diode shown, Figure 7 for Figure 5 A top view of the metal interconnect layers in the light-emitting diode shown. Figure 6 The horizontal dashed line corresponds to Figure 5 The cross section of the light emitting diode shown in the figure is for the purpose of clearly illustrating the graphic structures of the first through hole 14, the second through hole 15, the light emitting unit 19, the step structure 24 and the groove 20. Figure 6 Only the substrate 100, the first semiconductor layer 11 and the second semiconductor layer 13 are shown in the figure, and other film layer structures can refer to the above embodiment description and related drawings.

[0134] in, Figure 6 and Figure 7 The through-hole positions in the same layout, Figure 6 The first through hole 14 in Figure 7 The first through holes 14 correspond one to one, Figure 6 The second through hole 15 in Figure 7 The second through holes 15 correspond one to one.

[0135] Combination Figure 5-Figure 7 As shown, each light-emitting unit 19 has a first through hole 14 penetrating the second semiconductor layer 13 and the light-emitting layer 12, and the first through hole 14 exposes the first semiconductor layer 11; the i+1-th level interconnection line L i+1 Based on the first through hole 14 , it is electrically connected to the first semiconductor layer 11 of the i-th light emitting unit.

[0136] like Figure 5 As shown, in the light-emitting diode having at least two light-emitting units 19 connected in series, the first insulating dielectric layer 106 also covers the sidewall of the first through hole 14 and the bottom of the step structure 24; at the bottom of the first through hole 14, there is a second opening penetrating the first insulating dielectric layer 106, and the i+1-th level interconnection line L i+1 The second opening is electrically connected to the first semiconductor layer 11 of the i-th light emitting unit. A third opening 25 penetrating the first insulating dielectric layer 106 is provided at the bottom of the step structure 24. i+1 The third opening 25 is electrically connected to the first semiconductor layer 11 of the i-th level light emitting unit. The through holes in the first insulating dielectric layer 106 that are arranged one-to-one with the first opening 16 are second through holes 15, and the second through holes 15 are arranged one-to-one with the first opening 16; j The second through hole 15 is electrically connected to the ohmic contact layer 103 of the j-th light emitting unit.

[0137] In the embodiment of the present application, a first insulating dielectric layer 106 is further provided to cover the surface of the step structure 24 and fill the groove 20. As described above, the first insulating dielectric layer 106 above the light-emitting unit 19 is provided with a second through hole 15 arranged one-to-one opposite to the first opening 16, so as to facilitate the electrical connection between the interconnection line and the ohmic contact layer 103 on the corresponding light-emitting unit 19; and a third opening 25 penetrating the first insulating dielectric layer 106 is provided at the bottom of the step structure 24, so as to facilitate the electrical connection between the first electrode 110 and the interconnection line and the first semiconductor layer 11 of the corresponding light-emitting unit 19 based on the third opening 25.

[0138] in, Figure 5 Since the cross-sectional position does not pass through the first through hole 14, the cross-sectional structure of the first through hole 14 is not shown. The first through hole 14, the second opening, and the film layer structure inside the first through hole 14 can refer to the above description of Figure 1 or Figure 4 Description of implementation method.

[0139] In a light-emitting diode having at least two light-emitting units 19 connected in series, the first insulating dielectric layer 106 can also be set as a single insulating film; or, the first insulating dielectric layer 106 can be a second DBR layer having multiple insulating films. The implementation of the first insulating dielectric layer 106 can refer to the above-mentioned embodiment.

[0140] In a light emitting diode having at least two light emitting units 19 connected in series, in one embodiment, the j-th interconnection line L j It is in electrical contact with the ohmic contact layer 103 of the j-th light emitting unit. At this time, it corresponds to the implementation method in the above embodiment where the first metal reflective layer 104 is not required.

[0141] In another embodiment, the light emitting diode further comprises: a first metal reflective layer 104 located between the first insulating dielectric layer 106 and the ohmic contact layer 103; the first metal reflective layer 104 at least covers the first opening 16 and is electrically connected to the ohmic contact layer 103; wherein the j-th level interconnection line L j The ohmic contact layer 103 is electrically connected via the first metal reflective layer 104. This corresponds to the implementation of providing the first metal reflective layer 104 in the above embodiment.

[0142] In a light emitting diode having at least two light emitting units 19 connected in series, it is also possible to arrange that the first metal reflective layer 104 also covers a portion of the ohmic contact layer 103 outside the first opening 16 .

[0143] In a light-emitting diode having at least two light-emitting units 19 connected in series, the bottom of the first through hole 14 may also be provided with a second metal reflective layer 105 electrically contacting the first semiconductor layer 11 as in the above embodiment; a third metal reflective layer 113 may also be provided at the bottom of the step structure 24. i+1 Based on the second metal reflective layer 105 being electrically connected to the first semiconductor layer 11 of the i-th level light emitting unit; and / or, the bottom of the step structure 24 has a third metal reflective layer 113 electrically contacting the first semiconductor layer 11; the i+1-th level interconnection line L i+1 The third metal reflective layer 113 is electrically connected to the first semiconductor layer 11 of the i-th light-emitting unit; the first electrode 110 is electrically connected to the first semiconductor layer 11 of the M-th light-emitting unit based on the third metal reflective layer 113. Optionally, the third metal reflective layer 113 and the second metal reflective layer 105 are of the same layer structure, and the two are prepared simultaneously. In other methods, the third metal reflective layer 113 and the second metal reflective layer 105 can also be prepared separately.

[0144] In a light-emitting diode having at least two light-emitting units 19 connected in series, a second insulating dielectric layer 109 may also be provided between the metal interconnection layer 108 and the electrode layer. In this case, at the bottom of the step structure 24 of the M-th level light-emitting unit, there is a first electrode hole 22 penetrating the second insulating dielectric layer 109, and the first electrode 110 is electrically connected to the first semiconductor layer 11 of the M-th level light-emitting unit based on the first electrode hole 22; above the first level interconnection line L1, there is a second electrode hole 23 penetrating the second insulating dielectric layer 109, and the second electrode 111 is electrically in contact with the first level interconnection line L1 based on the second electrode hole 23.

[0145] It should be noted that, by setting a graphic structure of the metal interconnection layer 108 in the light-emitting diode, not only can multiple light-emitting units 19 be connected in series, but the light-emitting diode can also have light-emitting units 19 connected in parallel, or have light-emitting units 19 connected in series and light-emitting units 19 connected in parallel.

[0146] For the light-emitting diode provided in the embodiment of the present application, a sapphire substrate can be used as the above-mentioned substrate 100, and its manufacturing method mainly includes the following steps: first, an epitaxial layer 101 is prepared on the sapphire substrate and a first through hole 14 is formed in the epitaxial layer 101; then, a dielectric film current blocking layer 102 is prepared on the surface of the epitaxial layer 101 in the area corresponding to the second through hole 15; further, a transparent conductive layer is prepared as an ohmic contact layer 103, and the ohmic contact layer 103 can also be reused as a current expansion layer. The ohmic contact layer 103 in the first through hole 14 and the ohmic contact layer 103 in the area corresponding to the second through hole 15 are etched and removed, and the ohmic contact layer 103 and the dielectric film current blocking layer 102 have an overlapping portion 112. Further, a first metal reflective layer 104 with high reflectivity is deposited, and the first metal reflective layer 104 can be a multi-layer metal film, including a metal reflective film and a metal migration blocking film covering the metal reflective film. Finally, a metal interconnection layer 108 and an electrode layer are formed above the first metal reflective layer 104 to complete the preparation of the flip-chip light-emitting diode.

[0147] In order to more clearly introduce the product structure of the light emitting diode provided in the embodiment of the present application, the following is respectively combined with Figure 1 The schematic diagram of the product structure of the flip-chip light-emitting diode in each process step is shown as well as Figure 5 The schematic diagram of the product structure of the flip-chip light-emitting diode in each process step is shown to further illustrate the product structure and preparation process of the light-emitting diode provided in the embodiment of the present application.

[0148] refer to Figure 8-Figure 15 As shown, Figure 8-Figure 15 A schematic diagram of the product structure of a light emitting diode manufacturing method in different process steps provided in an embodiment of the present application, the manufacturing method includes:

[0149] Step S101: Figure 8 As shown, an epitaxial layer 101 is prepared on a substrate 100 , and after a first through hole 14 is formed in the epitaxial layer 101 , a dielectric film current blocking layer 102 is prepared on the surface of the epitaxial layer 101 outside the first through hole 14 .

[0150] The substrate 100 may be a transparent heterogeneous substrate. The epitaxial layer 101 includes a first semiconductor layer 11, a light-emitting layer 12, and a second semiconductor layer 13 formed on the surface of the substrate 100 from bottom to top. The epitaxial growth method may be any one of metal organic chemical vapor deposition, laser assisted molecular beam epitaxy, laser sputtering, and hydride vapor phase epitaxy. The thin film in the epitaxial layer 101 may be a single crystal silicon structure or a polycrystalline structure.

[0151] Wherein, the substrate 100 includes but is not limited to any one of a sapphire substrate, a SiC substrate, an AlN substrate and a ZnO substrate. In order to reduce the growth defects of the epitaxial layer 101, the substrate 100 can be provided with a micro-pattern structure on the surface used to prepare the epitaxial layer 101. The micro-pattern structure is a micron-scale or nano-scale pattern structure. Preferably, in the embodiment of the present application, the substrate 100 is a sapphire substrate with a nano-scale micro-pattern structure. The epitaxial layer 101 includes a GaN epitaxial layer, and specifically, the light-emitting layer 12 is one of the reciprocating continuous progressive LED epitaxial structures containing an InGaN material system, preferably an InGaN structure containing different In components. The depth of the first through hole 14 is not less than the sum of the thicknesses of the light-emitting layer 12 and the second semiconductor layer 13, and is less than the thickness of the epitaxial layer 101, so as to expose the first semiconductor layer 11. A plurality of first through holes 14 arranged in an array can be formed in the epitaxial layer 101 by photolithography and dry etching processes. The first through holes 14 extend downward from the surface of the second semiconductor layer 13, penetrate the second semiconductor layer 13 and the light-emitting layer 12, and the bottom of the first through holes 14 extends to the surface of the first semiconductor layer 11 facing the light-emitting layer 12, or extends to the inside of the first semiconductor layer 11. The center distance between adjacent first through holes 14 is 100 μm to 200 μm. After the first through holes 14 are formed, a layer of MgF2 film can be prepared as the dielectric film current blocking layer 102. The thickness of the dielectric film current blocking layer 102 is λ is the central wavelength of the light emitted by the LED, and n1 is the refractive index of the dielectric film current blocking layer 102 relative to the light with wavelength λ. The dielectric film current blocking layer 102 covers a portion of the surface of the second semiconductor layer 13 and is disposed one-to-one with the second through hole 15 formed subsequently.

[0152] Step S102: Fig. 9 As shown, a patterned ohmic contact layer 103 is formed on the surface of the second semiconductor layer 13 .

[0153] In this step, the ohmic contact layer 103 can be sputtered on the entire surface by using a sputtering process. The ohmic contact layer 103 is, for example, an ITO film with a thickness of, for example, 110 nm. The ITO film covers the surface of the second semiconductor layer 13, the dielectric film current blocking layer 102 and the first through hole 14. The ITO film is annealed to form an ohmic contact with the second semiconductor layer 12. Then, the ITO film is patterned to remove the ITO film in the first through hole 14, and a first opening 16 is formed on the ITO film above the dielectric film current blocking layer 102. The first opening 16 exposes a portion of the surface of the dielectric film current blocking layer 102. Figure 2 and Fig. 9As shown, the ohmic contact layer 103 and the dielectric film current blocking layer 102 have an overlapping portion 112. The width of the overlapping portion 112 may be 10 μm.

[0154] Step S103: Fig.10 As shown, a first metal reflective layer 104 is formed on the surface of the ohmic contact layer 103 .

[0155] In this step, a first metal reflective layer 104 may be formed on the surface of the ohmic contact layer 103 by using a photolithography and sputtering process. The first metal reflective layer 104 fills the first opening 16 and extends to cover the surface of the ohmic contact layer 103 around the opening. The first metal reflective layer 104, for example, includes an Ag film-TiW film-Pt film-Ti film formed in sequence. The Ag film is a metal film with high reflectivity, and the stacked TiW film-Pt film-Ti film serves as a metal barrier layer. The thickness of the Ag film-TiW film-Pt film-Ti film is 200 Å and 100 Å, respectively.

[0156] Step S104: Fig.11 As shown, a first insulating dielectric layer 106 is deposited on the entire surface.

[0157] In this method, the first insulating dielectric layer 106 includes a low refractive index film and a second DBR layer located on the surface of the low refractive index film. In this step, the low refractive index dielectric film can be prepared by PECVD (plasma enhanced chemical vapor deposition) process. The low refractive index dielectric film can be a SiO2 film. The thickness of the low refractive index dielectric film is n2 is the refractive index of the low refractive index dielectric film relative to the light with a wavelength of λ. m is a positive integer, such as m can be equal to 6. Taking the low refractive index dielectric film as a SiO2 film as an example, n2 is about 1.47, and m=6, λ=460nm is set, then the thickness of the low refractive index dielectric film is about 469nm. Then, at least one layer of TiO2 film and SiO2 film is alternately deposited on the surface of the low refractive index film using the EB-PVD (electron beam physical vapor deposition) process as the second DBR layer. The second DBR layer also adopts a structural design with two central reflection wavelengths, and has a large reflectivity for light with a wavelength of 400nm to 620nm, and the reflectivity is not less than 98%.

[0158] Step S105: Fig.12 As shown, the first insulating dielectric layer 106 is etched to form the second through hole 15 , and the first insulating dielectric layer 106 at the bottom of the first through hole 14 is removed to form the second opening 21 .

[0159] In this step, photolithography and dry etching techniques can be used to remove the first insulating dielectric layer 106 at the bottom of the first through hole 14 and the preset second through hole area to expose the first semiconductor layer 11 and the first metal reflective layer 104 at the bottom of the first through hole 14. A plurality of second through holes 15 arranged in an array are arranged above the second semiconductor layer 13, the dielectric film current blocking layer 102 is arranged in a one-to-one correspondence with the second through holes 15, the first metal reflective layer 104 is arranged in a one-to-one correspondence with the second through holes 15, and a portion of the first metal reflective layer 104 is exposed at the bottom of each second through hole 15.

[0160] Step S106: Fig.13 As shown, a patterned metal interconnection layer 108 is prepared on the surface of the first insulating dielectric layer 106 .

[0161] In this step, the metal interconnection layer 108 may be prepared by photolithography and electron beam evaporation process. The metal interconnection layer 108 may include Ti film-Au film-Ti film-Pt film-Ti film stacked in sequence, and the thickness of Ti film-Au film-Ti film-Pt film-Ti film is

[0162] The metal interconnection layer 108 includes: a first interconnection line 17 and a second interconnection line 18. The first interconnection line 17 is located in the first through hole 14 and can cover the surface of the first insulating dielectric layer 106 or fill the first through hole 14; the second interconnection line 18 is located on the first insulating dielectric layer 106 above the second semiconductor layer 13 and fills the second through hole 15.

[0163] Step S107: Fig.14 As shown, a second insulating dielectric layer 109 is deposited on the entire surface. The second insulating dielectric layer 109 covers the metal interconnect layer 108 and the first insulating dielectric layer 106.

[0164] In this step, a SiO2 film with a thickness of 1000 nm may be deposited as the second insulating dielectric layer 109. The second insulating dielectric layer 109 covers the metal interconnection layer 108 and covers the first insulating dielectric layer 106 exposed by the metal interconnection layer 108.

[0165] Step S108: Fig.15 As shown, a plurality of openings (including the first electrode holes 22 and the second electrode holes 23 ) exposing the first interconnection lines 17 and the second interconnection lines 18 are formed in the second insulating dielectric layer 109 .

[0166] Finally, an electrode layer is formed on the surface of the second insulating medium layer 109 having the first electrode hole 22 and the second electrode hole 23, and the first electrode 110 and the second electrode 111 in the electrode layer are electrically contacted with the first interconnection line 17 and the second interconnection line 18 based on the corresponding first electrode hole 22 and the second electrode hole 23, respectively, to form a Figure 1 The light emitting diode shown in the figure can be prepared by photolithography and electron beam evaporation process to sequentially prepare a stacked Ti film-Pt film-Ni film-AuSn film as an electrode layer.

[0167] refer to Figure 16-Figure 23 As shown, Figure 16-Figure 23 A schematic diagram of a product structure of another light-emitting diode manufacturing method provided in an embodiment of the present application at different process steps, the manufacturing method comprising:

[0168] Step S201: Fig.16 As shown, an epitaxial layer 101 is prepared on a substrate 100, and the epitaxial layer 101 includes a first semiconductor layer 11, a light-emitting layer 12, and a second semiconductor layer 13 formed on the surface of the substrate 100 from bottom to top. After forming a first through hole 14 and a step structure 24 in the epitaxial layer 101, a groove 20 penetrating the epitaxial layer 101 is formed to separate the epitaxial layer 101 into a plurality of light-emitting units 19, and a dielectric film current blocking layer 102 is prepared on the surface of the second semiconductor layer 13 of the light-emitting unit 19, and the dielectric film current blocking layer 102 covers a portion of the surface of the second semiconductor layer 13 and the dielectric film current blocking layer 102 is arranged one-to-one with the second through hole 15 formed subsequently.

[0169] In this method, the substrate 100 may be a sapphire substrate having a micro-pattern structure at the micron level. The epitaxial layer 101 and the first through hole 14 may be implemented in the same manner as described in the above step S101.

[0170] In this method, the dielectric film current blocking layer 102 includes: an Al2O3 film and a first DBR layer located on the surface of the Al2O3 film. The Al2O3 film and the first DBR layer can be deposited in sequence by EB-PVD process as the dielectric film current blocking layer 102. The first DBR layer includes at least one layer of Nb2O5 film and SiO2 film alternately arranged on the surface of the Al2O3 film. The first DBR layer is a structural design with dual center reflection wavelengths, the first center reflection wavelength can be 420nm, the second center reflection wavelength can be 470nm, and the thickness of the Al2O3 film can be 30nm.

[0171] Step S202: Fig.17 As shown, a patterned ohmic contact layer 103 is formed on the surface of the second semiconductor layer 13 .

[0172] In this method, the ohmic contact layer 103 can be sputtered on the entire surface by using a sputtering process. The ohmic contact layer 103 is, for example, an ITO film with a thickness of, for example, 200 nm. Figure 2 and Figure 5 As shown, the width of the overlap portion 112 may be 6 μm.

[0173] Step S203: Fig.18 As shown, a first metal reflective layer 104 is formed on the surface of the ohmic contact layer 103, a second metal reflective layer 105 is formed at the bottom of the first through hole 14, and a third metal reflective layer 113 is formed at the bottom of the step structure 24. As described above, the second metal reflective layer 105 and the third metal reflective layer 113 can be simultaneously prepared based on the same process steps, or the second metal reflective layer 105 and the third metal reflective layer 113 can be separately prepared using different process steps.

[0174] In this method, the second metal reflective layer 105 and the third metal reflective layer 113 are prepared simultaneously in the same process step as an example. Specifically, a stacked Ag film-Pt film-Ti film can be sequentially formed on the surface of the ohmic contact layer 103 by photolithography and sputtering process as the first metal reflective layer 104. The Ag film is a metal film with high reflectivity, and the stacked Pt film-Ti film is used as a metal barrier layer. The thickness of the Ag film-Pt film-Ti film is A thin film A, a Ni film, a Pt film, and a Ti film are sequentially deposited at the bottom of the first through hole 14 and the step structure 24 as the second metal reflective layer 105 and the third metal reflective layer 113. The second metal reflective layer 105 and the third metal reflective layer 113 are high reflectivity ohmic contact layers stacked with multiple metal films.

[0175] Step S204: Fig.19 As shown, a first insulating dielectric layer 106 is deposited on the entire surface.

[0176] In this manner, the first insulating dielectric layer 106 can be implemented in the same manner as in the above step S104 . The first insulating dielectric layer 106 fills the trench 20 to achieve insulation isolation of the epitaxial layer 101 in different light-emitting units 19 .

[0177] Step S205: Fig. 20 As shown, the first insulating dielectric layer 106 is etched to form the second through hole 15 , and the first insulating dielectric layer 106 at the bottom of the first through hole 14 and the bottom of the step structure 24 is removed to expose the second metal reflective layer 105 and the third metal reflective layer 113 .

[0178] Step S206: Fig.21 As shown, a patterned metal interconnection layer 108 is prepared on the surface of the first insulating dielectric layer 106 .

[0179] In this method, the structure and thickness of each film layer in the metal interconnection layer 108 are the same as those in step S106. The difference from step S106 is that the pattern structure of the metal interconnection layer 108 is different. Figure 5-Figure 7 The metal interconnection layer 108 in the embodiment realizes the series connection of multiple light emitting units 19 .

[0180] Step S207: Fig. 22 As shown, a second insulating dielectric layer 109 is deposited on the entire surface. The second insulating dielectric layer 109 covers the metal interconnect layer 108 and the first insulating dielectric layer 106. The implementation method of the second insulating dielectric layer 109 in this step is the same as that in the above step S107.

[0181] Step S208: Fig.23 As shown, a first electrode hole 22 and a second electrode hole 23 are formed in the second insulating dielectric layer 109 to expose the first-level interconnection line L1 above the first light-emitting unit 19 and the third metal reflective layer 113 in the last light-emitting unit 19 .

[0182] Finally, an electrode layer is formed on the surface of the second insulating dielectric layer 109 having the first electrode hole 22 and the second electrode hole 23, the second electrode 111 is electrically connected to the first-level interconnection line L1 above the first light-emitting unit 19 based on the second electrode hole 23, and the first electrode 110 is electrically connected to the first semiconductor layer 11 in the last light-emitting unit 19 based on the step structure 24 of the last light-emitting unit 19, forming a structure as shown in FIG. Figure 5 The plurality of light emitting units 19 shown are light emitting diodes connected in series.

[0183] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. The implementation methods provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0184] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0185] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0186] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0187] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A light emitting diode, characterized in that: include: substrate; The epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked from bottom to top on the substrate; a first through hole, penetrating the second semiconductor layer and the light emitting layer to expose the first semiconductor layer; A dielectric film current blocking layer and an ohmic contact layer are sequentially formed above the second semiconductor layer; the ohmic contact layer has an overlapping portion with a peripheral portion of the dielectric film current blocking layer, and has a first opening exposing a middle region of the dielectric film current blocking layer; a first insulating dielectric layer, covering the ohmic contact layer and the sidewall of the first through hole, and having a second opening exposing the bottom of the first through hole; a second through hole penetrating the first insulating dielectric layer; the second through hole and the first opening are arranged one by one opposite to each other; The electrode layer located above the first insulating dielectric layer comprises a first electrode and a second electrode; the first electrode is electrically connected to the first semiconductor layer based on the first through hole; and the second electrode is electrically connected to the ohmic contact layer based on the second through hole.

2. The light emitting diode according to claim 1, characterized in that: In a direction parallel to the plane where the substrate is located, the width of the overlapping portion ranges from 5 μm to 15 μm.

3. The light emitting diode according to claim 1, characterized in that: The dielectric film current blocking layer is a single-layer insulating film; Alternatively, the dielectric film current blocking layer is a first DBR layer having multiple layers of insulating films.

4. The light emitting diode according to claim 1, characterized in that: The first insulating dielectric layer is a single-layer insulating film; Alternatively, the first insulating dielectric layer is a second DBR layer having multiple insulating films.

5. The light emitting diode according to claim 1, characterized in that: A patterned metal interconnection layer is provided between the electrode layer and the first insulating dielectric layer. The first electrode is electrically connected to the first semiconductor layer based on a portion of the metal interconnection layer. The second electrode is electrically connected to the ohmic contact layer based on another portion of the metal interconnection layer.

6. The light emitting diode according to claim 5, characterized in that: A second insulating dielectric layer is provided between the metal interconnect layer and the electrode layer; The metal interconnection layer includes: a first interconnection line, part of which is located in the first through hole and electrically connected to the first semiconductor layer; a second interconnection line, which is located above the ohmic contact layer and electrically connected to the ohmic contact layer based on the second through hole; The first electrode is electrically in contact with the first interconnection line based on a first electrode hole penetrating the second insulating dielectric layer; and the second electrode is electrically in contact with the second interconnection line based on a second electrode hole penetrating the second insulating dielectric layer.

7. The light emitting diode according to claim 6, characterized in that: having a plurality of the first through holes and a plurality of the second through holes; The first interconnection lines in different first through holes are connected as one body; and the second interconnection lines in different second through holes are connected as one body.

8. The light emitting diode according to claim 6, characterized in that: The second interconnection line is in electrical contact with the ohmic contact layer at the first opening; Or, there is a first metal reflective layer between the first insulating dielectric layer and the ohmic contact layer; the first metal reflective layer at least covers the first opening and is electrically connected to the ohmic contact layer; wherein the second interconnect line is electrically connected to the ohmic contact layer through the first metal reflective layer.

9. The light emitting diode according to claim 8, characterized in that: The first metal reflective layer also covers a portion of the ohmic contact layer outside the first opening.

10. The light emitting diode according to any one of claims 1 to 9, characterized in that: The bottom of the first through hole has a second metal reflective layer electrically contacting the first semiconductor layer; At the bottom of the first through hole, the first electrode is electrically connected to the first semiconductor layer based on the second metal reflective layer.

11. A light emitting diode, characterized in that: include: substrate; The epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially stacked from bottom to top on the surface of the substrate; The epitaxial layer has a plurality of light-emitting units arranged in sequence; the light-emitting units have a step structure, the step structure sequentially penetrates the second semiconductor layer and the light-emitting layer to expose the first semiconductor layer; and a groove penetrating the epitaxial layer is provided between adjacent light-emitting units; A dielectric film current blocking layer and an ohmic contact layer are sequentially formed on the second semiconductor layer of the light-emitting unit; for the same light-emitting unit, the ohmic contact layer has an overlapping portion with the peripheral portion of the dielectric film current blocking layer, and has a first opening exposing the middle region of the dielectric film current blocking layer; A first insulating dielectric layer, covering the ohmic contact layer of each of the light-emitting units and the sidewalls of the step structure; the first insulating dielectric layer has a plurality of through holes penetrating the first insulating dielectric layer and arranged one by one opposite to the first opening; A patterned metal interconnection layer, the metal interconnection layer is located on the surface of the first insulating dielectric layer, and at least two light-emitting units are connected in series in sequence based on the step structure; the metal interconnection layer is electrically connected to the ohmic contact layer based on a through hole arranged in the first insulating dielectric layer opposite to the first opening; The electrode layer located on the side of the metal interconnect layer away from the epitaxial layer has a first electrode and a second electrode; for the light-emitting units connected in series in sequence, the first electrode is electrically connected to the first semiconductor layer of one of the light-emitting units based on the step structure, and the second electrode is electrically connected to the ohmic contact layer of another light-emitting unit based on the metal interconnect layer.

12. The light emitting diode according to claim 11, characterized in that: In a direction parallel to the plane where the substrate is located, the width of the overlapping portion ranges from 5 μm to 15 μm.

13. The light emitting diode according to claim 11, characterized in that: The dielectric film current blocking layer is a single-layer insulating film; Alternatively, the dielectric film current blocking layer is a first DBR layer having multiple layers of insulating films.

14. The light emitting diode according to claim 11, characterized in that: The at least two light-emitting units include: a first-order light-emitting unit to an M-th-order light-emitting unit, where M is a positive integer greater than 1; The metal interconnection layer includes: a 1st-level interconnection line to an Mth-level interconnection line; a jth-level interconnection line is located above the jth-level light-emitting unit and is electrically connected to the ohmic contact layer of the jth-level light-emitting unit, where j is a positive integer not greater than M; an i+1th-level interconnection line is electrically connected to the first semiconductor layer of the ith-level light-emitting unit based on the step structure of the ith-level light-emitting unit, where i is a positive integer less than M; Wherein, the first electrode is electrically connected to the first semiconductor layer of the Mth-level light-emitting unit based on the step structure of the Mth-level light-emitting unit; and the second electrode is electrically connected to the first-level interconnection line.

15. The light emitting diode according to claim 14, characterized in that: Each of the light-emitting units has a first through hole penetrating the second semiconductor layer and the light-emitting layer, wherein the first through hole exposes the first semiconductor layer; The (i+1)th level interconnection line is also electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the first through hole.

16. The light emitting diode according to claim 15, characterized in that: The first insulating dielectric layer also covers the sidewall of the first through hole and the bottom of the step structure; A second opening penetrating the first insulating dielectric layer is provided at the bottom of the first through hole, and the (i+1)th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the second opening; A third opening penetrating through the first insulating dielectric layer is provided at the bottom of the step structure, and the (i+1)th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the third opening; The through holes in the first insulating medium layer that are arranged one-to-one with the first openings are second through holes; the j-th level interconnection line is electrically connected to the ohmic contact layer of the j-th level light-emitting unit based on the second through holes.

17. The light emitting diode according to claim 16, characterized in that: The first insulating dielectric layer is a single-layer insulating film; Alternatively, the first insulating dielectric layer is a second DBR layer having multiple insulating films.

18. The light emitting diode according to claim 16, characterized in that: The j-th level interconnection line is in electrical contact with the ohmic contact layer of the j-th level light emitting unit; Or, it also includes: a first metal reflective layer located between the first insulating medium layer and the ohmic contact layer; the first metal reflective layer at least covers the first opening and is electrically connected to the ohmic contact layer; wherein the j-th level interconnect line is electrically connected to the ohmic contact layer through the first metal reflective layer.

19. The light emitting diode according to claim 18, characterized in that: The first metal reflective layer also covers a portion of the ohmic contact layer outside the first opening.

20. The light emitting diode according to any one of claims 15 to 19, characterized in that: The bottom of the first through hole has a second metal reflective layer electrically in contact with the first semiconductor layer; the i+1th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light emitting unit based on the second metal reflective layer; And / or, the bottom of the step structure has a third metal reflective layer electrically in contact with the first semiconductor layer; the i+1th level interconnection line is electrically connected to the first semiconductor layer of the i-th level light-emitting unit based on the third metal reflective layer; and the first electrode is electrically connected to the first semiconductor layer of the M-th level light-emitting unit based on the third metal reflective layer.

21. The light emitting diode according to claim 14, characterized in that: A second insulating dielectric layer is provided between the metal interconnect layer and the electrode layer; A first electrode hole penetrating the second insulating medium layer is provided at the bottom of the step structure of the M-th light-emitting unit, and the first electrode is electrically connected to the first semiconductor layer of the M-th light-emitting unit based on the first electrode hole; A second electrode hole penetrating through the second insulating medium layer is provided above the first-level interconnection line, and the second electrode is electrically contacted with the first-level interconnection line based on the second electrode hole.

22. The light emitting diode according to claim 11, characterized in that: The first insulating dielectric layer also covers the surface of the step structure and fills the trench.

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