Three-dimensional capacitor structure

Abstract

The utility model provides a three-dimensional capacitor structure. The three-dimensional capacitor structure provided by the utility model comprises a substrate, at least one stacked structure, an isolation layer, a first electrode and a second electrode, wherein the at least one stack structure is formed on the substrate; the first side face and the second side face of each stacking structure in the at least one stacking structure are of a step-shaped structure. Each stacked structure comprises n + 1 electrode layers and n dielectric layers which are alternately stacked, and n is a positive integer; the isolation layer is formed on the at least one stack structure and forms a plane with the at least one stack structure; a first electrode wire group and a second electrode wire group are formed in the isolating layer; the first electrodes are communicated with the odd-level electrode layers on the first side surface and the second side surface of each stacked structure through first electrode wire groups; and the second electrode is communicated with the even-numbered electrode layers on the first side surface and the second side surface of each stacked structure through a second electrode wire group. The three-dimensional capacitor structure provided by the utility model can reduce equivalent series inductance.

Description

Technical Field

[0001] The present application relates to the field of electronic and electrical technology, and in particular to a three-dimensional capacitor structure. Background Art

[0002] Capacitors play a vital role in the electronic component family, widely used in various circuits and devices. Known for their ability to store and release charge, capacitors provide indispensable functionality for electronic systems. Among capacitor performance parameters, equivalent series resistance (ESR) and equivalent series inductance (ESL) are of particular concern, playing a key role in practical circuits.

[0003] Reducing the equivalent series inductance of capacitors is an urgent problem that needs to be solved. This not only affects the performance of capacitors in high-frequency circuits, but also directly affects the stability of power supply and the accuracy of signal transmission. Utility Model Content

[0004] In view of this, the present application provides a three-dimensional capacitor structure to reduce the equivalent series inductance of the three-dimensional capacitor structure.

[0005] Specifically, this application is implemented through the following technical solutions:

[0006] In a first aspect, the present application provides a three-dimensional capacitor structure, comprising a substrate, at least one stacked structure, an isolation layer, a first electrode, and a second electrode; wherein,

[0007] The at least one stacked structure is formed on the substrate; the first side surface and the second side surface of each stacked structure in the at least one stacked structure are both step-shaped structures; each stacked structure includes n+1 electrode layers and n dielectric layers alternately stacked, where n is a positive integer; the first side surface and the second side surface are two side surfaces on a designated side of each stacked structure; the designated side is a long side or a short side;

[0008] The isolation layer is formed on the at least one stacked structure and forms a plane with the at least one stacked structure;

[0009] A first electrode wire group and a second electrode wire group are formed inside the isolation layer; wherein, the first wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the first side of each stacked structure, and the second wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the second side of each stacked structure; the third wire group in the second electrode wire group is connected to the even-numbered electrode layers on the first side of each stacked structure, and the fourth wire group in the second electrode wire group is connected to the even-numbered electrode layers on the second side of each stacked structure; the wire groups connected to the same electrode layer include a plurality of dot-shaped connection holes, and from the first direction indicated by the designated edge, the connection holes of the first wire group and the connection holes of the third wire group are alternately arranged, and the connection holes of the fourth wire group and the connection holes of the second wire group are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group and the connection holes of the fourth wire group are oppositely arranged, and the connection holes of the third wire group and the connection holes of the second wire group are oppositely arranged;

[0010] The first electrode is connected to the odd-numbered electrode layers on the first side and the second side of each stacked structure through the first electrode wire group;

[0011] The second electrode is connected to the even-numbered electrode layers on the first side surface and the second side surface of each stacked structure through the second electrode wire group.

[0012] Optionally, the aspect ratio of each stacked structure is greater than 1, and the first side surface and the second side surface are two side surfaces on the long side of each stacked structure.

[0013] Optionally, the three-dimensional capacitor structure includes a stacked structure, and the long side direction of the stacked structure is along the length direction of the substrate.

[0014] Optionally, the three-dimensional capacitor structure includes a plurality of stacked structures, wherein the plurality of stacked structures are arranged in sequence along the length direction or the width direction of the substrate.

[0015] Optionally, the electrode layer is composed of one or more combinations of doped polysilicon, TiN, TaN, Ti, Ta, Al, Cu, Au, Ag, and W.

[0016] Optionally, the dielectric layer is formed by one or more of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide, aluminum oxide, hafnium oxide, and tantalum oxide.

[0017] Optionally, each stacking structure in the at least one stacking structure is formed by a nanoimprinting process.

[0018] Optionally, the thickness of the electrode layer is 5 nm to 1 mm.

[0019] Optionally, the dielectric layer has a thickness of 1 nm to 100 μm.

[0020] The three-dimensional capacitor structure provided by the present application is configured such that the first wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the first side of each stacked structure, the second wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the second side of each stacked structure, the third wire group in the second electrode wire group is connected to the even-numbered electrode layers on the first side of each stacked structure, and the fourth wire group in the second electrode wire group is connected to the even-numbered electrode layers on the second side of each stacked structure, and the wire groups connected to the same electrode layer include a plurality of point-shaped connection holes. From the first direction indicated by the designated edge, the connection holes of the first wire group and the connection holes of the third wire group are alternately arranged, and the connection holes of the fourth wire group and the connection holes of the second wire group are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group and the connection holes of the fourth wire group are relatively arranged, and the connection holes of the third wire group and the connection holes of the second wire group are relatively arranged. In this way, ESL can be reduced or even offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A cross-sectional view of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application;

[0022] Figure 2 A top view of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application;

[0023] Figure 3 This is a partial schematic diagram of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application.

[0024] Description of reference numerals:

[0025] 1: base;

[0026] 2: Stacked structure;

[0027] 21: electrode layer;

[0028] 22: dielectric layer;

[0029] 3: Isolation layer;

[0030] 31: first electrode wire group;

[0031] 311: first wire group;

[0032] 312: second wire group;

[0033] 32: second electrode wire group;

[0034] 321: third wire group;

[0035] 322: fourth wire group;

[0036] 4: first electrode;

[0037] 5: Second electrode. DETAILED DESCRIPTION

[0038] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0039] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0040] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0041] The present application provides a three-dimensional capacitor structure to reduce the equivalent series inductance of the three-dimensional capacitor structure.

[0042] The three-dimensional capacitor structure provided by the present application is configured such that the first wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the first side of each stacked structure, the second wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the second side of each stacked structure, the third wire group in the second electrode wire group is connected to the even-numbered electrode layers on the first side of each stacked structure, and the fourth wire group in the second electrode wire group is connected to the even-numbered electrode layers on the second side of each stacked structure, and the wire groups connected to the same electrode layer include a plurality of point-shaped connection holes. From the first direction indicated by the designated edge, the connection holes of the first wire group and the connection holes of the third wire group are alternately arranged, and the connection holes of the fourth wire group and the connection holes of the second wire group are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group and the connection holes of the fourth wire group are relatively arranged, and the connection holes of the third wire group and the connection holes of the second wire group are relatively arranged. In this way, ESL can be reduced or even offset.

[0043] Figure 1 is a cross-sectional view of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application. Figure 2 This is a top view of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application. Figure 1 and Figure 2 The three-dimensional capacitor structure provided in this embodiment includes a substrate 1, at least one stacked structure 2, an isolation layer 3, a first electrode 4 and a second electrode 5; wherein,

[0044] The at least one stacked structure 2 is formed on the substrate 1; the first side surface and the second side surface of each stacked structure in the at least one stacked structure 2 are both stepped structures; each stacked structure 2 includes n+1 electrode layers 21 and n dielectric layers 22 alternately stacked, where n is a positive integer; the first side surface and the second side surface are two side surfaces on a designated side of each stacked structure; the designated side is a long side or a short side;

[0045] The isolation layer 3 is formed on the at least one stacked structure 2 and forms a plane with the at least one stacked structure 2;

[0046] A first electrode wire group 31 and a second electrode wire group 32 are formed inside the isolation layer 3; wherein, the first wire group 311 in the first electrode wire group 31 is connected to the odd-numbered electrode layers on the first side of each stacked structure 2, and the second wire group 312 in the first electrode wire group 31 is connected to the odd-numbered electrode layers on the second side of each stacked structure 2; the third wire group 321 in the second electrode wire group 32 is connected to the even-numbered electrode layers on the first side of each stacked structure 2, and the fourth wire group 322 in the second electrode wire group 32 is connected to the even-numbered electrode layers on the first side of each stacked structure 2. an even-numbered electrode layer on the second side surface; a conductive line group connected to the same electrode layer includes a plurality of dot-shaped connection holes; when viewed from the first direction indicated by the designated side, the connection holes of the first conductive line group 311 and the connection holes of the third conductive line group 321 are alternately arranged, and the connection holes of the fourth conductive line group 322 and the connection holes of the second conductive line group 312 are alternately arranged; when viewed from a second direction perpendicular to the first direction, the connection holes of the first conductive line group 311 and the connection holes of the fourth conductive line group 322 are oppositely arranged, and the connection holes of the third conductive line group 321 and the connection holes of the second conductive line group 312 are oppositely arranged;

[0047] The first electrode 4 is connected to the odd-numbered electrode layers on the first side and the second side of each stacked structure 2 through the first electrode wire group 31;

[0048] The second electrode 5 is connected to the even-numbered electrode layers on the first side surface and the second side surface of each stacked structure 2 through the second electrode wire group 32 .

[0049] It should be noted that the substrate 1 can be a semiconductor material substrate, such as a silicon substrate, a Ge substrate, a SiGe substrate, an SOI substrate, or a GOI substrate; it can also be an insulating substrate, such as silicon nitride, silicon dioxide, silicon oxynitride, a flexible polymer substrate, a glass substrate, a sapphire substrate, or a silicon carbide substrate; it can also be a Group III-V substrate, such as a gallium nitride substrate or a gallium arsenide substrate, etc., and this embodiment is not limited to this. In specific implementation, the appropriate material can be selected as the substrate based on the actual requirements of the three-dimensional capacitor structure, and this is not limited here.

[0050] For details, please refer to Figure 1 The three-dimensional capacitor structure includes at least one stacked structure 2. For example, in one possible implementation, the three-dimensional capacitor structure includes one stacked structure; for another example, in another possible implementation, the three-dimensional capacitor structure includes multiple stacked structures.

[0051] It should be noted that the first side and the second side of each stacking structure 2 are both step-type structures, and the first side and the second side are the two sides on the long side or the two sides on the short side of each stacking structure. This is not limited in this embodiment.

[0052] Optionally, in a possible implementation, the aspect ratio of each stacked structure 2 is greater than 1, and the first side surface and the second side surface are two side surfaces on the long side of each stacked structure 2 .

[0053] Specifically, the width of the steps in the stepped structure is set according to actual needs. In this embodiment, the width of the steps is not limited. For example, in one possible implementation, the width of the steps is between 50 nanometers and 2 micrometers.

[0054] For further information, please refer to Figure 1 Each stack structure 2 includes n+1 alternating electrode layers 21 and n dielectric layers 22, where n is a positive integer. The specific value of n is determined based on practical needs and is not limited in this embodiment. In practice, very high capacitance density can be achieved by controlling the number of stacked layers.

[0055] Specifically, the material of the electrode layer 21 is composed of one or more combinations of doped polysilicon, TiN, TaN, Ti, Ta, Al, Cu, Au, Ag, and W, and the material of the dielectric layer 22 is composed of one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, magnesium oxide, aluminum oxide, hafnium oxide, and tantalum oxide. It should be noted that the thickness of the dielectric layer 22 is determined by the withstand voltage of the capacitor. Generally, high-voltage capacitors require thicker dielectric layers. The thickness of the electrode layer 21 determines the equivalent series resistance and equivalent series inductance of the capacitor. Different materials and thicknesses can be selected according to different needs. In this embodiment, the material and thickness of the electrode layer 21 and the material and thickness of the dielectric layer 22 are not limited. For example, in one embodiment, the thickness of the electrode layer 21 is 5nm to 1mm, and the thickness of the dielectric layer 22 is 1nm to 100μm.

[0056] Please continue to refer to Figure 1 The isolation layer 3 is formed on the at least one stacked structure 2 and forms a plane with the at least one stacked structure 2. The isolation layer 3 is typically made of a material with a low dielectric constant to prevent electromagnetic interference between different layers in the three-dimensional capacitor structure. Specifically, the material of the isolation layer 3 can be selected according to actual needs and is not limited in this embodiment. For example, in one embodiment, the material of the isolation layer 3 can be SiO2 material with a low dielectric constant.

[0057] For further information, please refer to Figure 2A first electrode wire group 31 and a second electrode wire group 32 are formed within the isolation layer 3; wherein a first wire group 311 of the first electrode wire group 31 connects to the odd-numbered electrode layers on the first side of each stacked structure 2, and a second wire group 312 of the first electrode wire group 31 connects to the odd-numbered electrode layers on the second side of each stacked structure 2. A third wire group 321 of the second electrode wire group 32 connects to the even-numbered electrode layers on the first side of each stacked structure 2, and a fourth wire group 322 of the second electrode wire group 32 connects to the even-numbered electrode layers on the second side of each stacked structure.

[0058] Specifically, the conductive material filled in the first electrode wire group 31 and the second electrode wire group 32 includes tungsten.

[0059] It can be understood that the first electrode wire group 31 allows electrical signals to be transmitted between odd-numbered electrode layers through the stacked structure 2. The second electrode wire group 32 allows electrical signals to be transmitted between even-numbered electrode layers through the stacked structure 2. This layered wire group design can effectively manage the electrical connections between different electrode layers in the three-dimensional capacitor structure, making it more orderly and controllable.

[0060] Please continue to refer to Figure 2 The wire group connected to the same electrode layer includes a plurality of point-shaped connection holes. It should be noted that the distance between two adjacent connection holes is between 50 nm and 600 nm. For example, in one possible implementation, the distance between two adjacent connection holes can be 100 nm, 300 nm, etc.

[0061] For further information, please refer to Figure 2 , viewed from a first direction indicated by the designated edge, the connection holes of the first wire group 311 and the connection holes of the third wire group 321 are alternately arranged, and the connection holes of the fourth wire group 322 and the connection holes of the second wire group 312 are alternately arranged; viewed from a second direction perpendicular to the first direction, the connection holes of the first wire group 311 and the connection holes of the fourth wire group 322 are oppositely arranged, and the connection holes of the third wire group 321 and the connection holes of the second wire group 312 are oppositely arranged.

[0062] Specifically, refer to Figure 2 The first electrode wire group 31 refers to the wire group connected to the odd-numbered electrode layers, which includes a first wire group 311 connected to the odd-numbered electrode layers on the first side, and a second wire group 312 connected to the odd-numbered electrode layers on the second side; similarly, the second electrode wire group 32 refers to the wire group connected to the even-numbered electrode layers, which includes a third wire group 321 connected to the even-numbered electrode layers on the first side, and a fourth wire group 322 connected to the even-numbered electrode layers on the second side.

[0063] For further information, please refer to Figure 2 Taking the first electrode layer as an example, it can be seen that the wire group connected to the same electrode layer includes a plurality of point-shaped connection holes. Furthermore, viewed from the second direction, on any cross-section parallel to the second direction, different electrode wire groups are distributed on the two side surfaces. For example, on the first cross-section (viewed from top to bottom), the first electrode wire group is distributed on the first side, and the second electrode wire group is distributed on the second side. On the second cross-section, the second electrode wire group is distributed on the first side, and the first electrode wire group is distributed on the second side. In other words, viewed from the first direction, in any one of the first side and the second side, the first electrode wire group and the second electrode wire group are alternately arranged, and viewed from the second direction, the first electrode wire group and the second electrode wire group are relatively arranged.

[0064] For further information, please refer to Figure 2 In a possible implementation, the direction of the current in the three-dimensional capacitor structure is as follows: Figure 2 As shown by the arrows in the figure, at this time, the currents in the two adjacent sections flow in opposite directions, which can reduce or even offset the ESL.

[0065] In addition, please continue to refer to Figure 2 By making the first side surface and the second side surface the two side surfaces on the long side, when the electrode wire group is led out through the step-type structure, the electrode wire group is located on the long side. In this way, the current will flow along the short side direction, the path through which the current flows is shorter, and the resistance of the capacitor is smaller.

[0066] The three-dimensional capacitor structure provided in this embodiment is configured such that the first wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the first side of each stacked structure, the second wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the second side of each stacked structure, the third wire group in the second electrode wire group is connected to the even-numbered electrode layers on the first side of each stacked structure, and the fourth wire group in the second electrode wire group is connected to the even-numbered electrode layers on the second side of each stacked structure, and the wire groups connected to the same electrode layer include a plurality of point-shaped connection holes. From the first aspect indicated by the designated edge, the connection holes of the first wire group and the connection holes of the third wire group are alternately arranged, and the connection holes of the fourth wire group and the connection holes of the second wire group are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group and the connection holes of the fourth wire group are oppositely arranged, and the connection holes of the third wire group and the connection holes of the second wire group are oppositely arranged. In this way, ESL can be reduced or even offset.

[0067] Optionally, the three-dimensional capacitor structure includes a stacked structure, and the long side direction of the stacked structure is along the length direction of the substrate.

[0068] It should be noted that the length direction of the substrate refers to the direction indicated by the long side of the substrate, and correspondingly, the width direction of the substrate refers to the direction indicated by the short side of the substrate.

[0069] Optionally, referring to the previous introduction, the three-dimensional capacitor structure may include one or more stacked structures. Furthermore, when the three-dimensional capacitor structure includes a stacked structure, the long side direction of the stacked structure may be along the length direction of the substrate or along the width direction of the substrate, which is not limited in this application. Preferably, in a possible implementation, when the three-dimensional capacitor structure includes a stacked structure, the long side direction of the stacked structure may be along the length direction of the substrate. In this way, by allowing the long side direction of the stacked structure to be along the length direction of the substrate, the size setting of the stacked structure can be made more reasonable, so that the long side of the stacked structure is relatively longer and the short side is relatively shorter, which can effectively reduce the resistance of the capacitor.

[0070] Optional, Figure 3 This is a schematic diagram of a three-dimensional capacitor structure shown in an exemplary embodiment of the present application. Figure 3 The three-dimensional capacitor structure provided in this embodiment includes a plurality of stacked structures, wherein the plurality of stacked structures are arranged in sequence along the length direction or the width direction of the substrate.

[0071] Specifically, when the three-dimensional capacitor structure includes multiple stacked structures, the multiple stacked structures can be arranged in sequence along the length direction of the substrate, or can be arranged in sequence along the width direction of the substrate, which is not limited in this embodiment. Figure 3 In the example shown, three stacked structures are sequentially arranged along the length direction of the substrate.

[0072] Reference Figure 3 , the two side surfaces on the long side of each stacking structure are stepped structures. In addition, for each of the three stacking structures, the arrangement of the electrode wire group is the same as Figure 2 Similar, no further description is given here.

[0073] It should be noted that, in a possible implementation of the present application, each stacking structure in the at least one stacking structure 2 is formed by a nanoimprinting process.

[0074] Specifically, nanoimprinting is a nanomanufacturing technology that aims to transfer the structure of a template or mold to a substrate. For example, in one possible implementation of the present application, electrode layers 21 and dielectric layers 22 are first alternately deposited on a substrate 1 to form a multilayer structure consisting of alternating electrode layers and dielectric layers on the substrate 1. Then, a pre-prepared template (the morphology of the template is set according to actual needs) is aligned with the corresponding position of the formed multilayer structure, and corresponding pressure is applied to make physical contact between the template and the formed multilayer structure, so that the structure on the template is transferred to the formed multilayer structure to form the required stacked structure.

[0075] It should be noted that by forming the stacked structure through nanoimprinting, the stacked structure can be produced in large quantities in a short time, thereby improving production efficiency. Nanoimprinting can also use templates for rapid batch production, resulting in low manufacturing costs.

[0076] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A three-dimensional capacitor structure, characterized in that: The three-dimensional capacitor structure includes a substrate, at least one stacked structure, an isolation layer, a first electrode and a second electrode; wherein, The at least one stacked structure is formed on the substrate; the first side surface and the second side surface of each stacked structure in the at least one stacked structure are both step-type structures; each stacked structure comprises n+1 electrode layers and n dielectric layers alternately stacked, wherein n is a positive integer; the first side surface and the second side surface are two side surfaces on a designated side of each stacked structure; the designated side is a long side or a short side; The isolation layer is formed on the at least one stacked structure and forms a plane with the at least one stacked structure; A first electrode wire group and a second electrode wire group are formed inside the isolation layer; wherein the first wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the first side of each stacked structure, and the second wire group in the first electrode wire group is connected to the odd-numbered electrode layers on the second side of each stacked structure; the third wire group in the second electrode wire group is connected to the even-numbered electrode layers on the first side of each stacked structure, and the fourth wire group in the second electrode wire group is connected to the even-numbered electrode layers on the second side of each stacked structure; the wire group connected to the same electrode layer includes a plurality of dot-shaped connection holes, and from the first direction indicated by the designated edge, the connection holes of the first wire group and the connection holes of the third wire group are alternately arranged, and the connection holes of the fourth wire group and the connection holes of the second wire group are alternately arranged; from the second direction perpendicular to the first direction, the connection holes of the first wire group and the connection holes of the fourth wire group are arranged oppositely, and the connection holes of the third wire group and the connection holes of the second wire group are arranged oppositely; The first electrode is connected to the odd-numbered electrode layers on the first side and the second side of each stacked structure through the first electrode wire group; The second electrode is connected to the even-numbered electrode layers on the first side surface and the second side surface of each stacked structure through the second electrode wire group.

2. The three-dimensional capacitor structure according to claim 1, characterized in that: The aspect ratio of each stacked structure is greater than 1, and the first side surface and the second side surface are two side surfaces on the long side of each stacked structure.

3. The three-dimensional capacitor structure according to claim 1 or 2, characterized in that: The three-dimensional capacitor structure includes a stacked structure, and the long side direction of the stacked structure is along the length direction of the substrate.

4. The three-dimensional capacitor structure according to claim 1 or 2, characterized in that: The three-dimensional capacitor structure includes a plurality of stacked structures, wherein the plurality of stacked structures are sequentially arranged along a length direction or a width direction of the substrate.

5. The three-dimensional capacitor structure according to claim 1, characterized in that: Each of the at least one stacked structure is formed by a nanoimprint process.

6. The three-dimensional capacitor structure according to claim 1, characterized in that: The thickness of the electrode layer is 5 nm to 1 mm.

7. The three-dimensional capacitor structure according to claim 1, characterized in that: The thickness of the dielectric layer is 1 nm to 100 μm.

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