Output stage dummy load circuit of programmable power supply

Abstract

The utility model discloses a programmable power supply output stage dummy load circuit, which adopts the technical scheme that an original fixed resistor is replaced by a constant-power electronic load circuit, when the voltage output is higher, the dummy load current is reduced, and when the voltage output is lower, the dummy load current is increased. When the dummy load works in one mode, the dummy load can automatically adapt to the output voltage of the power supply, and the same power can be consumed when each voltage is output, so that the power supply can enter a steady state under any output voltage when the power supply is in a no-load state, and the voltage can be rapidly reduced in time when the voltage is reduced. Some rapidly changing power supplies can easily draw rapidly changing ascending and descending curve waveforms by adopting the device provided by the utility model.

Description

Technical Field

[0001] The utility model relates to the technical field of program-controlled power supplies, in particular to a dummy load circuit at an output stage of a program-controlled power supply. Background Art

[0002] Current programmable power supplies cannot maintain a steady-state output without a load. Therefore, a very small load is added to the output stage to ensure a steady-state output. A common solution is to connect a fixed resistor in parallel with the output stage, but finding a suitable resistor value can be difficult when the output voltage has a wide adjustable range.

[0003] For example, Figure 1 As shown in the figure, a programmable power supply has an output range of 0-2000V. If the dummy load R1 is designed to be 1MΩ at 2000V, the power dissipated by the dummy load R1 is 4W. When the output voltage is adjusted to 1V, the power dissipated by the dummy load R1 is reduced to 0.000001W. This is so small that the load is negligible, and the power loop cannot enter steady state. Assuming the output voltage is 1V and the dummy load R1 is designed to be 100Ω, when the power supply is adjusted to 2000V, the power dissipated by the dummy load R1 will reach 40kW, which is unbearable for both the power supply and the dummy load R1. Currently, only an intermediate value can be selected, but it still cannot meet the full range of requirements. Furthermore, with a fixed dummy load R1, when the power supply is unloaded and the voltage is reduced, the voltage will slowly decrease due to the large resistance of the dummy load R1 and the output capacitance. Shutting down the output from 2000V takes several minutes. Utility Model Content

[0004] The main purpose of the utility model is to propose a programmable power supply output stage dummy load circuit, which aims to solve the problem that the programmable power supply dummy load with an extremely wide output range cannot select a suitable value, and achieve the effect of rapid drop when the voltage is lowered.

[0005] To achieve the above objectives, the present invention provides a programmable power supply output stage dummy load circuit, which is connected in parallel to both ends of a capacitor C of the power supply output stage. The programmable power supply output stage dummy load circuit includes a MOS transistor Q1, an operational amplifier APM1, an operational amplifier APM2, an operational amplifier APM3, and a resistor R2. Pin 2 of the MOS transistor Q1 is connected to the positive electrode of the capacitor C and pin 1 of the operational amplifier APM2. Pin 1 of the MOS transistor Q1 is connected to one end of the resistor R2 and pin 1 of the operational amplifier APM1. Pin 3 of the MOS transistor Q1 is connected to pin 3 of the operational amplifier APM3. The other end of the resistor R2 is connected to pin 2 of the operational amplifier APM1, pin 2 of the operational amplifier APM2, and the negative electrode of the capacitor C. Pin 2 of the operational amplifier APM3, pin 1 of the operational amplifier APM1, and pin 1 of the operational amplifier APM2 are connected to the load, and pin 1 of the operational amplifier APM3 is connected to a DAC.

[0006] A further technical solution of the present utility model is that the power supply output stage includes a MOS tube Q2, an operational amplifier APM4 and the capacitor C, pin 2 of the MOS tube Q2 is connected to the positive electrode of the power supply, pin 1 of the MOS tube Q2 is connected to the positive electrode of the capacitor C and pin 2 of the operational amplifier APM4, and pin 3 of the MOS tube Q2 is connected to pin 3 of the operational amplifier APM4.

[0007] The beneficial effects of the programmable power supply output stage dummy load circuit of the utility model are:

[0008] Through the above-mentioned technical solution, the present invention can automatically adapt the power supply output voltage, ensuring the same power consumption at each output voltage. This allows the power supply to enter a steady state at any output voltage when unloaded, and can quickly and promptly reduce the voltage when the voltage is adjusted downward. This invention can easily draw rapidly changing rise and fall curves for some rapidly changing power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0010] Figure 1 It is the basic block diagram of program-controlled power transmission in the existing technology;

[0011] Figure 2It is a structural diagram of a preferred embodiment of the programmable power supply output stage dummy load circuit of the present utility model.

[0012] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0014] Please refer to Figure 2 The utility model proposes a programmable power supply output stage dummy load circuit, which can replace Figure 1 In the prior art, resistor R1 is connected in parallel with the power supply's output stage as a dummy load to ensure steady-state operation when the power supply is unloaded. The present invention employs a constant-power electronic load circuit, replacing the existing fixed resistor. This circuit reduces the dummy load current when the output voltage is high and increases it when the output voltage is low. By maintaining the dummy load in a fixed mode, the circuit adapts to maintain steady-state output regardless of the power supply's output voltage, without consuming significant power.

[0015] For details, please refer to Figure 2 The programmable power supply output stage dummy load circuit of the present invention is connected in parallel to both ends of the capacitor C of the power supply output stage. A preferred embodiment of the programmable power supply output stage dummy load circuit includes a MOS transistor Q1, an operational amplifier APM1, an operational amplifier APM2, an operational amplifier APM3, and a resistor R2. Pin 2 of the MOS transistor Q1 is connected to the positive electrode of the capacitor C and pin 1 of the operational amplifier APM2. Pin 1 of the MOS transistor Q1 is connected to one end of the resistor R2 and pin 1 of the operational amplifier APM1. Pin 3 of the MOS transistor Q1 is connected to pin 3 of the operational amplifier APM3. The other end of the resistor R2 is connected to pin 2 of the operational amplifier APM1, pin 2 of the operational amplifier APM2, and the negative electrode of the capacitor C. Pin 2 of the operational amplifier APM3, pin 1 of the operational amplifier APM1, and pin 1 of the operational amplifier APM2 are connected to the load, and pin 1 of the operational amplifier APM3 is connected to a DAC.

[0016] In this embodiment, the power output stage includes a MOS transistor Q2, an operational amplifier APM4, and the capacitor C. Pin 2 of the MOS transistor Q2 is connected to the positive electrode of the power supply, pin 1 of the MOS transistor Q2 is connected to the positive electrode of the capacitor C and pin 2 of the operational amplifier APM4, and pin 3 of the MOS transistor Q2 is connected to pin 3 of the operational amplifier APM4.

[0017] The following combination Figure 2 The working principle of the output stage dummy load circuit of the programmable power supply of the utility model is described in detail.

[0018] The dummy load circuit of the programmable power supply output stage of the utility model is connected in parallel to the two ends of the capacitor C of the power supply output stage. The operational amplifier APM1 is used to collect the current signal of the dummy load, and the operational amplifier APM2 is used to collect the signal of the power supply output voltage. The actual power consumed by the dummy load can be obtained by multiplying the current and voltage signals. Figure 2 Where PSET is the fixed power value designed for the current dummy load. PSET is compared with the actual power consumed by the dummy load to control the conduction of diode Q1. When the voltage increases, diode Q1 is controlled to reduce the current. When the voltage decreases, diode Q1 is controlled to increase the current. The product of voltage and current is always equal to PSET, thus achieving automatic adaptation of the power supply output voltage and keeping the power supply in steady state.

[0019] In this embodiment, PSET may be controlled by a DAC or by resistor voltage division to obtain a fixed voltage.

[0020] When the power supply output is turned off, the PSET value is set to a large value (it can be switched to a fixed voltage through a switch or set through a DAC). At this time, the diode Q1 will be fully turned on due to the extremely large product of voltage and current, entering the saturation region. The capacitor C of the power supply output stage will be completely discharged instantly by the short-circuited diode Q1, achieving an extremely rapid drop in voltage when the power supply is turned off.

[0021] If the power supply does not shut down the output but instead reduces the output voltage, the new dummy load of the utility model will always operate in a constant power state, and the voltage drop speed will be much faster than the previous fixed resistor. If the drop time of the original solution is at the minute level, the drop time of the solution of the utility model can be at the millisecond level.

[0022] The beneficial effects of the programmable power supply output stage dummy load circuit of the utility model are:

[0023] Through the above-mentioned technical solution, the present invention can automatically adapt the power supply output voltage, ensuring the same power consumption at each output voltage. This allows the power supply to enter a steady state at any output voltage when unloaded, and can quickly and promptly reduce the voltage when the voltage is adjusted downward. This invention can easily draw rapidly changing rise and fall curves for some rapidly changing power supplies.

[0024] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made based on the contents of the present invention specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A programmable power supply output stage dummy load circuit, characterized in that: The programmable power supply output stage dummy load circuit is connected in parallel to both ends of the capacitor C of the power supply output stage. The programmable power supply output stage dummy load circuit includes a MOS tube Q1, an operational amplifier APM1, an operational amplifier APM2, an operational amplifier APM3 and a resistor R2. Pin 2 of the MOS tube Q1 is connected to the positive electrode of the capacitor C and pin 1 of the operational amplifier APM2. Pin 1 of the MOS tube Q1 is connected to one end of the resistor R2 and pin 1 of the operational amplifier APM1. Pin 3 of the MOS tube Q1 is connected to pin 3 of the operational amplifier APM3. The other end of the resistor R2 is connected to pin 2 of the operational amplifier APM1, pin 2 of the operational amplifier APM2 and the negative electrode of the capacitor C. Pin 2 of the operational amplifier APM3, pin 1 of the operational amplifier APM1 and pin 1 of the operational amplifier APM2 are connected to the load, and pin 1 of the operational amplifier APM3 is connected to the DAC.

2. The programmable power supply output stage dummy load circuit according to claim 1, characterized in that: The power output stage includes a MOS tube Q2, an operational amplifier APM4 and the capacitor C. Pin 2 of the MOS tube Q2 is connected to the positive electrode of the power supply, pin 1 of the MOS tube Q2 is connected to the positive electrode of the capacitor C and pin 2 of the operational amplifier APM4, and pin 3 of the MOS tube Q2 is connected to pin 3 of the operational amplifier APM4.

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