Display panel and display device

Abstract

The embodiment of the utility model discloses a display panel and a display device, the display panel comprises a first liquid crystal box, a second liquid crystal box and a third liquid crystal box which are stacked, and the first liquid crystal box, the second liquid crystal box and the third liquid crystal box reflect light of different colors respectively; a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, the plurality of first data lines are connected with the first liquid crystal box, the plurality of second data lines are connected with the second liquid crystal box, and the plurality of third data lines are connected with the third liquid crystal box; the plurality of first data lines are connected with one ends of the plurality of second data lines in a one-to-one correspondence manner through the first circuit board, and the other ends of the plurality of second data lines are connected with one ends of the plurality of third data lines in a one-to-one correspondence manner through the second circuit board; and corresponding data voltages are written into the first liquid crystal box, the second liquid crystal box and the third liquid crystal box in a time-sharing manner. According to the scheme, the number of used driving chips can be reduced, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Reflective display panels are widely used in e-readers or other electronic components (such as price tags) due to their advantages such as low power consumption and eye-friendliness.

[0003] Cholesteric liquid crystals, due to their unique optical properties, are often used to make reflective display panels. However, due to the pitch requirements of cholesteric liquid crystals, a cholesteric liquid crystal with a certain pitch can only reflect one color and transmit light of other colors. If a color image is required, a three-layer stacked liquid crystal cell architecture can be used to achieve multi-grayscale color display by controlling the states of different liquid crystal cells. However, during the display process, each layer of liquid crystal cells requires at least one driver chip to drive it, depending on the number of channels in the driver chip. For a three-layer liquid crystal cell display architecture, at least three driver chips are required. For large-size display panels, even more driver chips are required, significantly increasing production costs. Utility Model Content

[0004] The embodiments of the present invention provide a display panel and a display device, which can reduce the number of driving chips and thus lower the manufacturing cost.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising:

[0006] A first liquid crystal cell, a second liquid crystal cell, and a third liquid crystal cell are stacked, wherein the first liquid crystal cell, the second liquid crystal cell, and the third liquid crystal cell respectively reflect light of different colors;

[0007] a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines, wherein the plurality of first data lines are connected to the first liquid crystal cell, the plurality of second data lines are connected to the second liquid crystal cell, and the plurality of third data lines are connected to the third liquid crystal cell;

[0008] a first circuit board and a second circuit board, wherein the plurality of first data lines are connected to one ends of the plurality of second data lines in a one-to-one correspondence via the first circuit board, and the other ends of the plurality of second data lines are connected to one ends of the plurality of third data lines in a one-to-one correspondence via the second circuit board;

[0009] The first liquid crystal cell, the second liquid crystal cell and the third liquid crystal cell are written with corresponding data voltages in a time-sharing manner.

[0010] Optionally, the liquid crystal cell has a first surface and a second surface opposite to each other, the first circuit board and the second circuit board are both flexible circuit boards, the second surface of the second liquid crystal cell is folded onto the second surface of the first liquid crystal cell, and the second surface of the third liquid crystal cell is folded onto the first surface of the second liquid crystal cell;

[0011] The first circuit board is provided with a first connecting line, the second circuit board is provided with a second connecting line, the first data line is connected to the second data line through the first connecting line, and the second data line is connected to the third data line through the second connecting line.

[0012] Optionally, the first liquid crystal cell includes a first substrate, a second substrate, and a first liquid crystal layer located between the first substrate and the second substrate; the first substrate includes a plurality of first pixel electrodes and a plurality of first transistors; the second substrate includes a first common electrode; a first electrode of each first transistor is connected to a first data line, and a second electrode of the first transistor is connected to a first pixel electrode; each overlapping region of the first pixel electrode and the first common electrode forms a first pixel region;

[0013] The second liquid crystal cell includes a third substrate, a fourth substrate, and a second liquid crystal layer located between the third substrate and the fourth substrate. The third substrate includes a plurality of second pixel electrodes and a plurality of second transistors. The fourth substrate includes a second common electrode. A first electrode of each second transistor is connected to a second data line, and a second electrode of the second transistor is connected to a second pixel electrode. Each overlapping area of ​​the second pixel electrode and the second common electrode forms a second pixel area.

[0014] The third liquid crystal box includes a fifth substrate, a sixth substrate, and a third liquid crystal layer located between the fifth substrate and the sixth substrate. The fifth substrate includes a plurality of third pixel electrodes and a plurality of third transistors. The sixth substrate includes a third common electrode. The first electrode of each third transistor is connected to a third data line, and the second electrode of the third transistor is connected to a third pixel electrode. The overlapping area of ​​each third pixel electrode and the third common electrode forms a third pixel area.

[0015] Optionally, a chip binding area is provided on the first substrate to bind a driving chip connected to the first data line;

[0016] The first circuit board is bonded to a side of the first substrate opposite to the chip bonding area.

[0017] Optionally, the first liquid crystal layer, the second liquid crystal layer and the third liquid crystal layer all include cholesteric liquid crystal;

[0018] The first liquid crystal layer, the second liquid crystal layer and the third liquid crystal layer respectively reflect one of red light, green light and blue light.

[0019] Optionally, the display panel further includes a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines extending along a first direction, the plurality of first data lines, the plurality of second data lines, and the plurality of third data lines extending along a second direction, and the first direction intersects the second direction;

[0020] One of the first scan lines is connected to the gates of the first transistors in the same row, one of the second scan lines is connected to the gates of the second transistors in the same row, and one of the third scan lines is connected to the gates of the third transistors in the same row;

[0021] The first liquid crystal cell includes at least one first gate driving module, the first gate driving module includes a plurality of cascaded first gate driving units, and each stage of the first gate driving unit is connected to one of the first scanning lines;

[0022] The second liquid crystal cell includes at least one second gate driving module, the second gate driving module includes a plurality of cascaded second gate driving units, and each stage of the second gate driving unit is connected to one second scanning line;

[0023] The third liquid crystal cell includes at least one third gate driving module, the third gate driving module includes a plurality of cascaded third gate driving units, and each stage of the third gate driving unit is connected to one of the third scan lines;

[0024] The first-level second gate driving unit in the first second gate driving module is cascaded with the last-level first gate driving unit in the last first gate driving module, and the last-level second gate driving unit in the last second gate driving module is cascaded with the first-level third gate driving unit in the first third gate driving module.

[0025] Optionally, a third connecting line is provided on the first circuit board, and a fourth connecting line is provided on the second circuit board. The last-level first gate driving unit in the last first gate driving module is connected to the first-level second gate driving unit in the first second gate driving module through the third connecting line, and the last-level second gate driving unit in the last second gate driving module is connected to the first-level third gate driving unit in the first third gate driving module through the fourth connecting line.

[0026] Optionally, before folding, the first liquid crystal box, the second liquid crystal box and the third liquid crystal box are arranged along a first direction; or, the first liquid crystal box, the second liquid crystal box and the third liquid crystal box are arranged along a second direction; the first direction intersects the second direction perpendicularly.

[0027] According to another aspect of the present invention, a display device is provided, comprising the display panel provided by any embodiment of the present invention.

[0028] Optionally, the display device further includes a timing controller and a driver chip, and the timing controller is connected to the driver chip.

[0029] The technical solution provided by the embodiment of the present invention is that, in a three-layer stacked liquid crystal box, the first liquid crystal box and the second liquid crystal box are bridged by a first circuit board, and the second liquid crystal box and the third liquid crystal box are bridged by a second circuit board, so that the first data line corresponding to the first liquid crystal box, the second data line corresponding to the second liquid crystal box, and the third data line corresponding to the third liquid crystal box are connected together, and a time-sharing drive method is adopted to write data voltages to the first liquid crystal box, the second liquid crystal box, and the third liquid crystal box in sequence, thereby eliminating the need to set driver chips on the second liquid crystal box and the third liquid crystal box, reducing the number of driver chips by two-thirds, and helping to reduce production costs.

[0030] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic side view of a display panel provided by an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present utility model;

[0034] Figure 3 A schematic cross-sectional view of a display panel provided in an embodiment of the present invention;

[0035] Figure 4A schematic diagram of the planar structure of another display panel provided by an embodiment of the present utility model;

[0036] Figure 5 A schematic diagram of the planar structure of another display panel provided by an embodiment of the present utility model;

[0037] Figure 6 A schematic diagram of a partially enlarged structure of a display panel provided by an embodiment of the present utility model;

[0038] Figure 7 A schematic diagram of a partially enlarged structure of another display panel provided by an embodiment of the present utility model;

[0039] Figure 8 A schematic diagram of a partially enlarged structure of another display panel provided by an embodiment of the present utility model;

[0040] Figure 9 A schematic diagram of the planar structure of another display panel provided by an embodiment of the present utility model;

[0041] Among them, 10 is the first liquid crystal cell; 111 is the first substrate; 112 is the second substrate; 113 is the first liquid crystal layer; 101 is the first gate; 102 is the first active layer; 103 is the first drain; 104 is the first source; 11 is the first pixel electrode; 12 is the first common electrode;

[0042] 20 - second liquid crystal cell; 211 - third substrate; 212 - fourth substrate; 213 - second liquid crystal layer; 201 - second gate electrode; 202 - second active layer; 203 - second drain electrode; 204 - second source electrode; 21 - second pixel electrode; 22 - second common electrode;

[0043] 30 - third liquid crystal cell; 311 - fifth substrate; 312 - sixth substrate; 313 - third liquid crystal layer; 301 - third gate electrode; 302 - third active layer; 303 - third drain electrode; 304 - third source electrode; 31 - third pixel electrode; 32 - third common electrode;

[0044] 41 - first circuit board; 42 - second circuit board; 51 - chip bonding area; 50 - driver chip; 61 - first gate driver module; 62 - second gate driver module; 63 - third gate driver module;

[0045] DL1 - first data line; DL2 - second data line; DL3 - third data line; GL1 - first scan line; GL2 - second scan line, GL3 - third scan line. DETAILED DESCRIPTION

[0046] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] Figure 1 This is a schematic side view of a display panel provided by an embodiment of the present invention. Figure 2 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, specifically a schematic diagram of a planar structure of a multi-layer liquid crystal cell before folding, with reference to FIG. Figure 1 and Figure 2 , the display panel provided in this embodiment includes:

[0049] A first liquid crystal cell 10, a second liquid crystal cell 20 and a third liquid crystal cell 30 are stacked, and the first liquid crystal cell 10, the second liquid crystal cell 20 and the third liquid crystal cell 30 respectively reflect light of different colors;

[0050] a plurality of first data lines DL1, a plurality of second data lines DL2, and a plurality of third data lines DL3, wherein the plurality of first data lines DL1 are connected to the first liquid crystal cell 10, the plurality of second data lines DL2 are connected to the second liquid crystal cell 20, and the plurality of third data lines DL3 are connected to the third liquid crystal cell 30;

[0051] A first circuit board 41 and a second circuit board 42, wherein the plurality of first data lines DL1 are connected to one ends of the plurality of second data lines DL2 in a one-to-one correspondence via the first circuit board 41, and the other ends of the plurality of second data lines DL2 are connected to one ends of the plurality of third data lines DL3 in a one-to-one correspondence via the second circuit board 42;

[0052] The first liquid crystal cell 10 , the second liquid crystal cell 20 and the third liquid crystal cell 30 are written with their corresponding data voltages in a time-sharing manner.

[0053] Specifically, the display panel can be a reflective display panel, which uses ambient light as a light source. By reflecting the ambient light through the panel's internal structure, the light is reflected into the human eye, thereby forming an image. The first liquid crystal cell 10, the second liquid crystal cell 20, and the third liquid crystal cell 30 are stacked in sequence. By adjusting the three liquid crystal cells to reflect different colors of light, multi-grayscale color display is achieved.

[0054] A first circuit board 41 is connected between the first liquid crystal box 10 and the second liquid crystal box 20, and a second circuit board 42 is connected between the second liquid crystal box 20 and the third liquid crystal box 30. The first data line DL1 and the second data line DL2 can be connected through the first circuit board 41, and the second data line DL2 and the third data line DL3 can be connected through the second circuit board 42, so that the first data line DL1, the second data line DL2 and the third data line DL3 are connected in series in sequence.

[0055] In this embodiment, corresponding data voltages are written to the first, second, and third liquid crystal cells 10, 20, and 30 in a time-sharing manner. For example, one end of a first data line DL1 is connected to a driver chip 50, the other end of the first data line DL1 is connected to one end of a second data line DL2, and the other end of the second data line DL2 is connected to one end of a third data line DL3. Each subpixel within the first liquid crystal cell 10 is connected to a corresponding first data line DL1, each subpixel within the second liquid crystal cell 20 is connected to a corresponding second data line DL2, and each subpixel within the third liquid crystal cell 30 is connected to a corresponding third data line DL3. When the driver chip 50 transmits a data voltage corresponding to the first liquid crystal cell 10 (e.g., a first data voltage), the first data voltage is transmitted to each of the first, second, and third data lines DL1, DL2, and DL3. However, only the transistors within the first liquid crystal cell 10 are turned on, causing the first data voltage to be written only to the first liquid crystal cell 10. When the data voltage corresponding to the second liquid crystal cell 20 (e.g., the second data voltage) is transmitted via the driver chip 50, the second data voltage is transmitted on the first data line DL1, the second data line DL2, and the third data line DL3. However, only the transistors in the second liquid crystal cell 20 are controlled to be turned on, so that the second data voltage is only written into the second liquid crystal cell 20. When the data voltage corresponding to the third liquid crystal cell 30 (e.g., the third data voltage) is transmitted via the driver chip 50, the third data voltage is transmitted on the first data line DL1, the second data line DL2, and the third data line DL3. However, only the transistors in the third liquid crystal cell 10 are controlled to be turned on, so that the third data voltage is only written into the third liquid crystal cell 10.

[0056] The technical solution provided by the embodiment of the present invention is that, in a stacked three-layer liquid crystal cell, the first liquid crystal cell 10 and the second liquid crystal cell 20 are bridged by a first circuit board 41, and the second liquid crystal cell 20 and the third liquid crystal cell 30 are bridged by a second circuit board 42, so that the first data line DL1 corresponding to the first liquid crystal cell 10, the second data line DL2 corresponding to the second liquid crystal cell 20, and the third data line DL3 corresponding to the third liquid crystal cell 30 are connected together, and data voltages are written to the first liquid crystal cell 10, the second liquid crystal cell 20, and the third liquid crystal cell 30 in sequence in a time-sharing drive manner, thereby eliminating the need to set a driver chip 50 on the second liquid crystal cell 20 and the third liquid crystal cell 30, thereby reducing the number of driver chips 50 by two-thirds, which is conducive to reducing production costs.

[0057] Continue to refer Figure 2 Optionally, a first connection line L1 is provided on the first circuit board 41, a second connection line L2 is provided on the second circuit board 42, the first data line DL1 is connected to the second data line DL2 through the first connection line L1, and the second data line DL2 is connected to the third data line DL3 through the second connection line L2.

[0058] Figure 3 A schematic cross-sectional view of a display panel according to an embodiment of the present invention is provided. Figure 3 Based on the above embodiments, optionally, the first liquid crystal cell 10 includes a first substrate 111, a second substrate 112, and a first liquid crystal layer 113 located between the first substrate 111 and the second substrate 112. The first substrate 111 includes a plurality of first pixel electrodes 11 and a plurality of first transistors Q1. The second substrate 112 includes a first common electrode 12. The first electrode of each first transistor Q1 is connected to a first data line DL1 (not shown in the figure), and the second electrode of the first transistor Q1 is connected to a first pixel electrode 11. The overlapping area of ​​each first pixel electrode 11 and the first common electrode 12 forms a first pixel region. The first transistor Q1 includes a first gate 201, a first active layer 202, a first source 204, and a first drain 203.

[0059] The second liquid crystal cell 20 includes a third substrate 211, a fourth substrate 212, and a second liquid crystal layer 213 located between the third and fourth substrates 211 and 212. The third substrate 212 includes a plurality of second pixel electrodes 21 and a plurality of second transistors Q2. The fourth substrate 212 includes a second common electrode 22. The first electrode of each second transistor Q2 is connected to a second data line DL2 (not shown), and the second electrode of the second transistor Q2 is connected to a second pixel electrode 21. The overlapping area of ​​each second pixel electrode 21 and the second common electrode 22 forms a second pixel region. The second transistor Q2 includes a second gate 201, a second active layer 202, a second source 204, and a second drain 203.

[0060] The third liquid crystal cell 30 includes a fifth substrate 311, a sixth substrate 312, and a third liquid crystal layer 313 located between the fifth and sixth substrates 311 and 312. The fifth substrate 311 includes a plurality of third pixel electrodes 31 and a plurality of third transistors Q3. The sixth substrate 312 includes a third common electrode 32. The first electrode of each third transistor Q3 is connected to a third data line DL3 (not shown), and the second electrode of the third transistor Q3 is connected to a third pixel electrode 31. The overlapping region of each third pixel electrode 31 and the third common electrode 32 forms a third pixel region. The third transistor Q3 includes a third gate 301, a third active layer 302, a third source 304, and a third drain 303.

[0061] Specifically, the first substrate 111, the third substrate 211, and the fifth substrate 311 are all array substrates, on which array traces and transistors are formed; the second substrate 112, the fourth substrate 212, and the sixth substrate 312 are all opposing substrates. A liquid crystal layer is disposed in the pixel region between the array substrate and the opposing substrate. For example, the first pixel region is provided with liquid crystal for reflecting red light, the second pixel region is provided with liquid crystal for reflecting green light, and the third pixel region is provided with liquid crystal for reflecting blue light. The first, second, and third liquid crystal layers 113, 213, and 313 all comprise cholesteric liquid crystal, which has two stable textures: the P state (planar) and the FC state (focal conic). Under a certain electric field, the P state and the FC state can be converted to each other. Neither the P state nor the FC state requires voltage maintenance. In the absence of voltage, the P state or the FC state can be maintained for a long time, facilitating low-power operation. When the cholesteric liquid crystal is in the P state, its reflection spectrum is in the visible spectrum. The cholesteric liquid crystal reflects bright colored light. The specific reflected color can be set according to the pitch of the cholesteric liquid crystal. By changing the pitch of the cholesteric liquid crystal, the wavelength of the reflected light can be controlled. When the cholesteric liquid crystal is in the FC state, the cholesteric liquid crystal no longer reflects the above-mentioned colored light, and light can be scattered and transmitted through the cholesteric liquid crystal. For example, at zero voltage, the initial state of the cholesteric liquid crystal is the P state. Different arrangement directions of the cholesteric liquid crystal reflect different visible light spectra. The reflection spectrum band is proportional to the pitch and birefringence of the cholesteric liquid crystal. When a voltage is applied across the cholesteric liquid crystal and slowly reduced to zero, the cholesteric liquid crystal rotates and stagnates in the FC state.

[0062] The first liquid crystal layer 113, the second liquid crystal layer 213 and the third liquid crystal layer 313 respectively reflect one of red light, green light and blue light. For example, the first liquid crystal layer 113 reflects red light, the second liquid crystal layer 213 reflects green light and the third liquid crystal layer 313 reflects blue light.

[0063] Optionally, continue to refer to Figure 3 The liquid crystal box has a first surface and a second surface arranged opposite to each other, for example, the first surface A1 of the first liquid crystal box 10 can be a surface of the second substrate 112, the second surface A2 of the first liquid crystal box 10 can be a surface of the first substrate 111, the first surface H1 of the second liquid crystal box 20 can be a surface of the fourth substrate 212, the second surface H2 of the second liquid crystal box 20 can be a surface of the third substrate 211, the first surface J1 of the third liquid crystal box 30 can be a surface of the sixth substrate 312, and the second surface J2 of the third liquid crystal box 30 can be a surface of the fifth substrate 311.

[0064] Combine Figure 2 and Figure 3 The first circuit board 41 and the second circuit board 42 are both flexible circuit boards. The second surface H2 of the second liquid crystal cell 20 is folded onto the second surface A2 of the first liquid crystal cell 10, and the second surface J2 of the third liquid crystal cell 30 is folded onto the first surface H1 of the second liquid crystal cell 20. This reduces the number of crossover traces on the first and second circuit boards 41 and 42, facilitating wiring. If the first surface is the front and the second surface is the back, then after folding, the second liquid crystal cell 20 is located on the back of the first liquid crystal cell 10, and the third liquid crystal cell 30 is located on the front of the second liquid crystal cell. That is, relative to the first liquid crystal cell 10, the second and third liquid crystal cells 20 and 30 are both in an inverted state. The subpixel R1 in the upper left corner (first in the first row) of the first liquid crystal cell 10, the subpixel R2 in the upper right corner (last in the first row) of the second liquid crystal cell 20, and the subpixel B1 in the upper left corner (first in the first row) of the third liquid crystal cell 30 together form the first pixel unit in the first row.

[0065] Figure 4 This is a schematic diagram of the planar structure of another display panel provided by an embodiment of the present invention, referring to Figures 3 and 4 Based on the above embodiments, optionally, a chip binding area 51 is provided on the first substrate 111 in the first liquid crystal box 10 for binding the driving chip 50, and the first circuit board 41 is bound to the side of the first substrate 111 opposite to the chip binding area 51 to facilitate wiring.

[0066] Of course, in other embodiments, the chip bonding area 51 may also be provided on the fifth substrate 311 in the third liquid crystal cell 30 , and may be provided according to actual needs and wiring space.

[0067] Figure 5 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present utility model is shown. Figure 6 This is a schematic diagram of a partially enlarged structure of a display panel provided by an embodiment of the present utility model. Figure 7This is a partial enlarged structural diagram of another display panel provided by an embodiment of the present utility model. Figure 8 This is a partial enlarged structural diagram of another display panel provided by an embodiment of the present invention, referring to Figures 5 to 8 The display panel further includes a plurality of first scan lines GL1, a plurality of second scan lines GL2, and a plurality of third scan lines GL3 extending along a first direction X, a plurality of first data lines DL1, a plurality of second data lines DL2, and a plurality of third data lines DL3 extending along a second direction Y, and the first direction X intersects the second direction Y; a first scan line GL1 is connected to the gate of the first transistor Q1 in the same row, a second scan line GL2 is connected to the gate of the second transistor Q2 in the same row, and a third scan line GL3 is connected to the gate of the third transistor Q3 in the same row. For example, in the first liquid crystal box 10, the first first scan line G11 is connected to the gate of each first transistor Q1 in the first row, the second first scan line G12 is connected to the gate of each first transistor Q1 in the second row, and the third first scan line G13 is connected to the gate of each first transistor Q1 in the third row; the first first data line D11 is connected to the source of each first transistor Q1 in the first column, the second first data line D12 is connected to the source of each first transistor Q1 in the second column, and the third first data line D13 is connected to the source of each first transistor Q1 in the third column. The drain of the first transistor Q1 is connected to the corresponding first pixel electrode 11. In the second liquid crystal box 20, the first second scan line G21 is connected to the gate of each second transistor Q2 in the first row, the second second scan line G22 is connected to the gate of each second transistor Q2 in the second row, and the third second scan line G23 is connected to the gate of each second transistor Q2 in the third row; the first second data line D21 is connected to the source of each second transistor Q2 in the first column, the second second data line D22 is connected to the source of each second transistor Q2 in the second column, and the third second data line D23 is connected to the source of each second transistor Q1 in the third column. The drain of the second transistor Q2 is connected to the corresponding second pixel electrode 21. In the third liquid crystal cell 30, a first third scan line G31 is connected to the gate of each third transistor Q3 in the first row, a second third scan line G32 is connected to the gate of each third transistor Q3 in the second row, and a third third scan line G33 is connected to the gate of each third transistor Q3 in the third row. A first third data line D31 is connected to the source of each third transistor Q3 in the first column, a second third data line D32 is connected to the source of each third transistor Q3 in the second column, and a third third data line D33 is connected to the source of each third transistor Q3 in the third column. The drain of the third transistor Q3 is connected to the corresponding third pixel electrode 31. The first direction X may be a row direction, and the second direction Y may be a column direction.

[0068] Combine Figure 3 、 Figure 4 and Figure 5The first liquid crystal cell 10 includes at least one first gate driver module 61, which can be disposed on the first substrate 111 of the first liquid crystal cell 10. The first gate driver module 61 includes a plurality of cascaded first gate driver units, with each stage of the first gate driver unit connected to a first scan line GL1. The second liquid crystal cell 20 includes at least one second gate driver module 62, which can be disposed on the third substrate 211 of the second liquid crystal cell 20. The second gate driver module 62 includes a plurality of cascaded second gate driver units, with each stage of the second gate driver unit connected to a second scan line GL2. The third liquid crystal cell 30 includes at least one third gate driver module 63, which can be disposed on the fifth substrate 311 of the third liquid crystal cell 30. The third gate driver module 63 includes a plurality of cascaded third gate driver units, with each stage of the third gate driver unit connected to a third scan line GL3. The first gate driver module 61, the second gate driver module 62, and the third gate driver module 63 are all disposed in the non-display area, and each liquid crystal layer is disposed in the display area.

[0069] refer to Figure 5 , wherein the first-stage first gate driving unit in the first first gate driving module 61 receives the start signal STV, and the first gate driving module 61 outputs the scanning signal step by step. The first-stage second gate driving unit in the first second gate driving module 62 is cascaded with the last-stage first gate driving unit in the last first gate driving module 61, and the last-stage second gate driving unit in the last second gate driving module 62 is cascaded with the first-stage third gate driving unit in the first third gate driving module 63.

[0070] Specifically, a third connecting line L3 is provided on the first circuit board 41, and a fourth connecting line L4 is provided on the second circuit board 42. The last-level first gate driving unit in the last first gate driving module 61 is connected to the first-level second gate driving unit in the first second gate driving module 62 through the third connecting line L4, and the last-level second gate driving unit in the last second gate driving module 62 is connected to the first-level third gate driving unit in the first third gate driving module 63 through the fourth connecting line L4, thereby realizing time-sharing driving of the first liquid crystal box 10, the second liquid crystal box 20 and the third liquid crystal box 30.

[0071] In this embodiment, when the front-end timing controller transmits a first source signal, causing the driver chip 50 to transmit the first data voltage to the first liquid crystal cell 10, the first scan line GL1 corresponding to the first liquid crystal cell 10 is turned on row by row from subpixels R1 to RM, and the first data line DL1 writes the first data voltage row by row into the rows of subpixels R1 to RM. After the first data voltage is written, each first gate driver module 61 is controlled to be turned off, and the cascade control signal of the first gate driver module 61 is transmitted to the second gate driver module 62. The second scan line GL2 corresponding to the second liquid crystal cell 20 is turned on row by row from subpixels G1 to GM, and the timing controller outputs a second source signal, causing the driver chip 50 to output the second data voltage corresponding to the second liquid crystal cell 20. After the second data voltage is written, each second gate driver module 62 is controlled to be turned off, and the cascade control signal of the second gate driver module 62 is transmitted to the third gate driver module 63. The third scan line GL3 corresponding to the third liquid crystal cell 30 is turned on row by row from the sub-pixel B1 to the sub-pixel BM. At the same time, the timing controller outputs the third source signal, and the driving chip 50 outputs the third data voltage corresponding to the third liquid crystal cell 20. When the third data voltage is written, the third gate driving module 63 is turned off.

[0072] For example, taking three driver chips 50 as an example, for a single-layer 1920*1080 resolution liquid crystal cell, the timing controller only needs to send 1080*3=3240 signals to the driver chips 50 to complete the writing of the data voltage required by the three-layer liquid crystal cell. In contrast, the prior art solution requires three driver chips 50 for each layer of liquid crystal cell, requiring 1080*9=9720 signals. Therefore, the technical solution provided by this embodiment, by cascading the corresponding data lines and scan lines of each liquid crystal cell, can significantly reduce the number of driver chips 50 and also reduce the power consumption of the timing controller.

[0073] In the above embodiments, the first liquid crystal cell 10, the second liquid crystal cell 20, and the third liquid crystal cell 30 are folded horizontally, that is, the three liquid crystal cells are arranged along the first direction X and folded sequentially toward the back of the first liquid crystal cell 10. In other embodiments, the first liquid crystal cell 10, the second liquid crystal cell 20, and the third liquid crystal cell 30 may also be folded vertically. Figure 9 This is a schematic diagram of the planar structure of another display panel provided by an embodiment of the present invention, referring to Figure 9 The first liquid crystal box 10, the second liquid crystal box 20 and the third liquid crystal box 30 are arranged along the second direction Y, the first circuit board 41 is connected between the first liquid crystal box 10 and the second liquid crystal box 20 along the second direction Y, and the second circuit board 42 is connected between the second liquid crystal box 20 and the third liquid crystal box 30 along the second direction Y. When folded, they are folded toward the back of the first liquid crystal box 10 in sequence. Figure 9The wiring of the display panel shown may refer to the horizontally folded wiring structure in the above embodiment, which will not be described again here, and has the same beneficial effects.

[0074] Optionally, an embodiment of the present invention further provides a display device. The display device provided in this embodiment can be an e-reader (such as an e-book or e-newspaper), or can be other electronic products such as price tags. The display device includes the display panel provided in any embodiment of the present invention, and thus, the display device has the beneficial effects described in any of the above embodiments.

[0075] Optionally, the display device provided in this embodiment further includes a timing controller and a driver chip. The timing controller is connected to the driver chip. The timing controller can be used to output a control signal to the driver chip to control the driver chip to transmit data voltages to each data line.

[0076] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this utility model can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this utility model can be achieved. This is not limited herein.

[0077] The above specific embodiments do not limit the scope of protection of this utility model. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model shall be included within the scope of protection of this utility model.

Claims

1. A display panel, characterized in that: include: A first liquid crystal cell, a second liquid crystal cell, and a third liquid crystal cell are stacked, wherein the first liquid crystal cell, the second liquid crystal cell, and the third liquid crystal cell respectively reflect light of different colors; a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines, wherein the plurality of first data lines are connected to the first liquid crystal cell, the plurality of second data lines are connected to the second liquid crystal cell, and the plurality of third data lines are connected to the third liquid crystal cell; a first circuit board and a second circuit board, wherein the plurality of first data lines are connected to one ends of the plurality of second data lines in a one-to-one correspondence via the first circuit board, and the other ends of the plurality of second data lines are connected to one ends of the plurality of third data lines in a one-to-one correspondence via the second circuit board; The first liquid crystal cell, the second liquid crystal cell and the third liquid crystal cell are written with corresponding data voltages in a time-sharing manner.

2. The display panel according to claim 1, wherein: The liquid crystal cell has a first surface and a second surface opposite to each other, the first circuit board and the second circuit board are both flexible circuit boards, the second surface of the second liquid crystal cell is folded onto the second surface of the first liquid crystal cell, and the second surface of the third liquid crystal cell is folded onto the first surface of the second liquid crystal cell; The first circuit board is provided with a first connecting line, the second circuit board is provided with a second connecting line, the first data line is connected to the second data line through the first connecting line, and the second data line is connected to the third data line through the second connecting line.

3. The display panel according to claim 1, wherein: The first liquid crystal cell includes a first substrate, a second substrate, and a first liquid crystal layer located between the first substrate and the second substrate. The first substrate includes a plurality of first pixel electrodes and a plurality of first transistors. The second substrate includes a first common electrode. A first electrode of each first transistor is connected to a first data line, and a second electrode of the first transistor is connected to a first pixel electrode. Each overlapping area of ​​the first pixel electrode and the first common electrode forms a first pixel region. The second liquid crystal cell includes a third substrate, a fourth substrate, and a second liquid crystal layer located between the third substrate and the fourth substrate. The third substrate includes a plurality of second pixel electrodes and a plurality of second transistors. The fourth substrate includes a second common electrode. A first electrode of each second transistor is connected to a second data line, and a second electrode of the second transistor is connected to a second pixel electrode. Each overlapping area of ​​the second pixel electrode and the second common electrode forms a second pixel area. The third liquid crystal box includes a fifth substrate, a sixth substrate, and a third liquid crystal layer located between the fifth substrate and the sixth substrate. The fifth substrate includes a plurality of third pixel electrodes and a plurality of third transistors. The sixth substrate includes a third common electrode. The first electrode of each third transistor is connected to a third data line, and the second electrode of the third transistor is connected to a third pixel electrode. The overlapping area of ​​each third pixel electrode and the third common electrode forms a third pixel area.

4. The display panel according to claim 3, wherein: A chip binding area is provided on the first substrate for binding a driving chip connected to the first data line; The first circuit board is bonded to a side of the first substrate opposite to the chip bonding area.

5. The display panel according to claim 3, wherein: The first liquid crystal layer, the second liquid crystal layer and the third liquid crystal layer all include cholesteric liquid crystal; The first liquid crystal layer, the second liquid crystal layer and the third liquid crystal layer respectively reflect one of red light, green light and blue light.

6. The display panel according to claim 3, wherein: The display panel further includes a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines extending along a first direction, the plurality of first data lines, the plurality of second data lines, and the plurality of third data lines extending along a second direction, and the first direction intersects the second direction; One of the first scan lines is connected to the gates of the first transistors in the same row, one of the second scan lines is connected to the gates of the second transistors in the same row, and one of the third scan lines is connected to the gates of the third transistors in the same row; The first liquid crystal cell includes at least one first gate driving module, the first gate driving module includes a plurality of cascaded first gate driving units, and each stage of the first gate driving unit is connected to one of the first scanning lines; The second liquid crystal cell includes at least one second gate driving module, the second gate driving module includes a plurality of cascaded second gate driving units, and each stage of the second gate driving unit is connected to one second scanning line; The third liquid crystal cell includes at least one third gate driving module, the third gate driving module includes a plurality of cascaded third gate driving units, and each stage of the third gate driving unit is connected to one of the third scan lines; The first-level second gate driving unit in the first second gate driving module is cascaded with the last-level first gate driving unit in the last first gate driving module, and the last-level second gate driving unit in the last second gate driving module is cascaded with the first-level third gate driving unit in the first third gate driving module.

7. The display panel according to claim 6, wherein: A third connecting line is provided on the first circuit board, and a fourth connecting line is provided on the second circuit board. The last-level first gate driving unit in the last first gate driving module is connected to the first-level second gate driving unit in the first second gate driving module through the third connecting line, and the last-level second gate driving unit in the last second gate driving module is connected to the first-level third gate driving unit in the first third gate driving module through the fourth connecting line.

8. The display panel according to claim 1, wherein: Before folding, the first liquid crystal cell, the second liquid crystal cell and the third liquid crystal cell are arranged along a first direction; or, the first liquid crystal cell, the second liquid crystal cell and the third liquid crystal cell are arranged along a second direction; The first direction intersects the second direction perpendicularly.

9. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 8.

10. The display device according to claim 9, wherein The display device further includes a timing controller and a driving chip, and the timing controller is connected to the driving chip.

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