Verification device and verification system of field programmable gate array

Abstract

The utility model discloses a verification device and a verification system of a field programmable gate array. The verification device comprises a configuration circuit, a configuration input end of which is connected with a serial port signal and a configuration output end of which outputs a first configuration signal and a second configuration signal; each first input end of the first signal selection circuit is connected with a first to-be-verified signal, a first high-order output end outputs a first high-order signal, and a first low-order output end outputs a first low-order signal; each second input end of the second signal selection circuit is connected with a first to-be-verified signal, a second high-order output end outputs a second high-order signal, and a second low-order output end outputs a second low-order signal; and the output end of the first signal combination circuit outputs the combined verification signal to a logic analyzer. According to the verification device provided by the utility model, free combination and selection of the signals to be verified are realized, the flexibility of observing the verification signals is improved, the consumption of internal resources of the FPGA is reduced, and the verification device is suitable for various use scenes.

Description

Technical Field

[0001] The present application relates to the field of field programmable gate array verification signals, and in particular to a field programmable gate array verification device and verification system. Background Art

[0002] With the rise of technologies such as communications, digital signal processing, and semiconductors, field-programmable gate arrays (FPGAs) are now enabling the implementation of specific hardware logic. To verify that the logic circuits in an FPGA are operating as expected, observation signals are selected in advance and fed into the internal logic analyzer provided by the FPGA development tool. The internal logic analyzer logic code is then generated into a downloadable file and transferred to the development tool via the JTAG interface and a downloader for observation.

[0003] However, when observing multiple modules to be verified, it's impossible to freely combine and select different signals to be verified based on test needs. Multiple signals must be connected to multiple internal logic analyzers, consuming significant amounts of the FPGA's internal resources. Excessive internal logic analyzers can lead to insufficient FPGA resources. Furthermore, existing signal observation methods can only be implemented through JTAG and downloaders transmitted to the software interface provided by the development tool. The FPGA must maintain a physical connection to the computer development tool for communication, making it unsuitable for a variety of use cases. Summary of the Invention

[0004] In order to solve the problem of free combination and selection between signals to be verified, the utility model provides a verification device and verification system for a field programmable gate array. The specific technical solution is as follows:

[0005] The utility model provides a verification device for a field programmable gate array, comprising:

[0006] The configuration circuit includes a configuration input terminal and a configuration output terminal, wherein the configuration input terminal is connected to a serial port signal, and the configuration output terminal outputs a first configuration signal and a second configuration signal; a first signal selection circuit includes a plurality of first input terminals, a first configuration control terminal, a first high-order output terminal, and a first low-order output terminal; each first input terminal is connected to a first signal to be verified, and when the first configuration control terminal receives the first configuration signal, the first signal selection circuit selects a first signal to be verified and splits it into a first high-order signal and a first low-order signal, the first high-order output terminal outputs the first high-order signal, and the first low-order output terminal outputs the first low-order signal; a second signal selection circuit includes a plurality of second input terminals, a second configuration control terminal, a second high-order output terminal, and a second low-order output terminal; each second input terminal is connected to a first signal to be verified, and when the first configuration control terminal receives the first configuration signal, the first signal selection circuit selects a first signal to be verified and splits it into a first high-order signal and a first low-order signal, the first high-order output terminal outputs the first high-order signal, and the first low-order output terminal outputs the first low-order signal; A first signal to be verified. When the second configuration control terminal receives the first configuration signal, the second signal selection circuit selects a first signal to be verified and splits it into a second high-order signal and a second low-order signal. The second high-order output terminal outputs the second high-order signal, and the second low-order output terminal outputs the second low-order signal. A first signal combination circuit includes a third configuration control terminal and multiple first combination input terminals, and receives the first high-order signal, the first low-order signal, the second high-order signal, and the second low-order signal. When the third configuration control terminal receives the first configuration signal, the first signal combination circuit selects any two of the first high-order signal, the first low-order signal, the second high-order signal, and the second low-order signal to combine to form a combined verification signal. The first signal combination circuit outputs the combined verification signal to a logic analyzer.

[0007] Specifically, through the field programmable gate array verification device proposed in the present invention, the first / second signal selection circuit splits the signal to be verified into a high-order signal and a low-order signal, and the first signal combination circuit selects two from the four high-order and low-order signals according to configuration requirements to combine to form a combined verification signal, thereby realizing free combination and selection between different signals to be verified.

[0008] Furthermore, it also includes:

[0009] Multiple second signal combination circuits include multiple second combination input terminals and a fourth configuration control terminal, each second combination input terminal is connected to a second signal to be verified, and the fourth configuration control terminal is connected to the configuration output terminal; when the fourth configuration control terminal receives the first configuration signal, the second signal combination circuit selects the second signal to be verified and combines it to form a first signal to be verified, and the second signal combination circuit outputs the first signal to be verified to the first signal selection circuit and the second signal selection circuit.

[0010] Specifically, through the field programmable gate array verification device proposed in the present invention, the second signal combination circuit selects the combination of the original signals to be verified according to the selection of the configuration signal, and outputs the preliminary combined first signals to be verified to the two signal selection circuits.

[0011] 8. Furthermore, the first signal selection circuit, the second signal selection circuit, the first signal combination circuit, and the second signal combination circuit each include a multiplexer or an integrated circuit that implements a multiplexer selection function.

[0012] Furthermore, the circuit is configured to include:

[0013] The verification circuit includes a configuration input terminal; the configuration input terminal is connected to the serial port signal, the verification circuit verifies and analyzes the serial port signal to form a data signal and a verification result signal, and the output terminal of the verification circuit outputs the data signal and the verification result signal; the receiving control circuit is connected to the verification circuit and includes a configuration output terminal; the input terminal of the receiving control circuit is connected to the data signal, the verification result signal and the clock signal, and the receiving control circuit configures the data signal and outputs a first configuration signal and / or a second configuration signal.

[0014] Specifically, through the field programmable gate array verification device proposed in the present invention, the verification circuit will verify the serial port signal, and the receiving control circuit will convert the serial port serial signal into a received configuration signal. At the same time, the configuration signal can only be output if the verification result signal is correct.

[0015] Furthermore, the verification circuit includes:

[0016] The serial port register receives the serial port signal at one end and outputs the data signal and the check signal at the other end. The XOR logic gate receives the data signal and the check signal at one end and outputs the check result signal at the other end.

[0017] Furthermore, the receiving control circuit includes:

[0018] A counting register, one end of which receives the clock signal and the other end of which is connected to the adder; an equal logic gate and the adder, one end of which is connected to the adder and the other end of which is connected to the multiplexer; a multiplexer, the multiplexer being connected to the check circuit and the equal logic gate, the multiplexer outputting a data signal; a data register, one end of which is connected to the multiplexer and the other end of which outputs a first configuration signal and / or a second configuration signal.

[0019] Furthermore, it also includes:

[0020] The output circuit includes a fifth configuration control terminal, an input terminal of the output circuit is connected to the output terminal of the first signal combination circuit, and the fifth configuration control terminal is connected to the configuration output terminal; when the fifth configuration control terminal receives the second configuration signal, the input terminal of the output circuit receives the combination verification signal, and the output terminal of the output circuit outputs the combination verification signal to the pin of the field programmable gate array.

[0021] Specifically, the field programmable gate array verification device proposed in the present invention outputs the pins of the FPGA itself, which is not limited to the traditional observation method, thus allowing for more usage scenarios.

[0022] Furthermore, the output circuit includes a signal multiplexer, or an integrated circuit that implements a multiplexing function.

[0023] The present invention also proposes a field programmable gate array verification system, comprising any one of the field programmable gate array verification devices, and further comprising: a plurality of modules to be verified, the modules to be verified outputting signals to be verified, the signals to be verified being combined by the field programmable gate array verification device, and a combined verification signal being output.

[0024] Furthermore, it also includes: an interface chip for outputting configuration information; a serial port chip for outputting the configuration information as a serial port signal, and outputting the serial port signal to the verification device of the field programmable gate array.

[0025] Through the field programmable gate array verification device and verification system proposed by the utility model, the verification signals of all modules are managed in a unified manner, and the signals to be verified are flexibly selected based on verification requirements. It is possible to use only one internal logic analyzer to switch the observed signals between different modules, and it is also possible to switch the pin output signals of the FPGA, so as to observe the status of the pin output signals in more usage scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0027] Figure 1 It is a structural diagram of a verification device for a field programmable gate array according to an embodiment of the present invention;

[0028] Figure 2 It is a structural diagram of a field programmable gate array verification device according to another embodiment of the present invention;

[0029] Figure 3 This is a digital circuit diagram of a second signal combination circuit according to an embodiment of the present invention;

[0030] Figure 4 This is a digital circuit diagram of a first signal selection circuit, a second signal selection circuit, and a first signal combination circuit in one embodiment of the present utility model;

[0031] Figure 5It is a structural diagram of a field programmable gate array verification device according to another embodiment of the present invention;

[0032] Figure 6 This is a digital circuit diagram of an output circuit of an embodiment of the present utility model;

[0033] Figure 7 It is a digital circuit diagram of a configuration circuit of an embodiment of the utility model;

[0034] Figure 8 This is a circuit diagram of an output serial port signal according to an embodiment of the present invention;

[0035] Reference numerals: verification device for field programmable gate array 100 , configuration circuit 110 , first signal selection circuit 120 , second signal selection circuit 130 , first signal combination circuit 140 , second signal combination circuit 150 , output circuit 160 . DETAILED DESCRIPTION

[0036] In the following description, specific details such as specific system structures and technologies are provided for illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obstructing the description of the present application with unnecessary details.

[0037] It will be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0038] It should be further understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0039] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive work.

[0041] A field-programmable gate array (FPGA) is a flexible hardware platform that can be programmed to implement specific hardware logic. When developing on an FPGA platform, the designed logic code is synthesized and placed and routed using development tools to generate a downloadable file. This file is then downloaded to the FPGA to form the logic circuit.

[0042] During the actual development process, there are usually some design issues. It is necessary to use an internal logic analyzer to observe the signals during FPGA operation to verify whether the FPGA's operating status meets the expected design, thereby discovering some problems in the designed logic code for subsequent modification and optimization.

[0043] Typically, when verifying a single functional module, a corresponding internal logic analyzer is added for verification. However, when observing multiple modules, it's impossible to freely combine and select different verification signals based on test requirements. Instead, multiple verification signals must be connected to multiple internal logic analyzers. For example, when verifying inter-module communication functionality, the current verification method involves using a separate internal logic analyzer for each functional module requiring verification.

[0044] However, both the internal logic analyzer and functional modules require the use of internal FPGA logic resources, which are limited. As the number of functional modules increases and the use of multiple logic analyzers consumes too much FPGA logic, insufficient FPGA resources can result, leading to errors when generating download files. Furthermore, reducing resource consumption by reducing the number of logic analyzers introduces new challenges. Each change in the verification module requires redeveloping the synthesis tool and layout and routing, making the entire process time-consuming and labor-intensive. Furthermore, verification environments involving multi-module communication are inconvenient and lack flexibility.

[0045] In addition, the signals sampled by the on-chip logic analyzer generally need to be transmitted through JTAG and a downloader to the software interface provided by the development tool for observation. The FPGA must maintain a physical connection with the computer development tool in real time for communication. The observation method is limited and not suitable for various usage scenarios.

[0046] Therefore, the utility model proposes a verification device for a field programmable gate array, wherein the second signal combination circuit preliminarily combines all the signals to be verified to form a first signal to be verified, the first signal selection circuit and / or the second signal selection circuit splits the first signal to be verified into a high-order signal and a low-order signal, and the first signal combination circuit combines the high-order signal and the low-order signal according to the configuration signal to form a combined verification signal, so as to realize the combined output of multiple verification signals of multiple modules.

[0047] Through the field programmable gate array verification device of the utility model, the signals to be verified are selected and combined, and the signals between different modules are combined into a combined verification signal. The signals to be verified can cover all modules that need to be verified, reducing the number of logic analyzers used, supporting switching to FPGA pin output, and realizing flexible observation of the signals to be verified.

[0048] In one embodiment of the present invention, a verification system for a field programmable gate array is provided, including a verification device 100 for a field programmable gate array, a plurality of modules to be verified 200 , an interface chip 300 and a serial port chip 400 .

[0049] There are several modules 200 to be verified, each module 200 outputs a signal to be verified, and the verification device 100 of the field programmable gate array combines the signals to be verified and outputs a combined verification signal.

[0050] The interface chip 300 is used to output configuration information; the serial port chip 400 is used to output the configuration information as a serial port signal, and output the serial port signal to the field programmable gate array verification device 100.

[0051] Specifically, the modules to be verified 200 typically refer to functional modules that require testing and verification, and the field programmable gate array verification device 100 can be used to verify the signals generated by these modules to be verified 200. The verification system uses a hardware interface to transmit the configuration information of the signals to be verified via the interface chip 300 to the serial port chip 400. The serial port chip 400 then transmits the configuration information to the field programmable gate array in the form of serial port signals.

[0052] The field programmable gate array verification device 100 receives signals from the module to be verified 200 and combines them to generate combined verification signals. These combined verification signals include verification signals generated by multiple functional modules. By combining different verification signals for output verification and observing the real-time status of the combined verification signals in the FPGA logic circuit, it is determined whether the designed logic code meets the expected functionality.

[0053] Through the field programmable gate array verification system proposed by the utility model, the signals to be verified can be freely combined, and the signals to be verified between different modules form a combined verification signal, which reduces the number of logic analyzers used and thus reduces the consumption of FPGA internal resources.

[0054] An embodiment of the present invention, please refer to Figure 1 The present invention provides a field programmable gate array verification device 100 , including a configuration circuit 110 , a first signal selection circuit 120 , a second signal selection circuit 130 and a first signal combination circuit 140 .

[0055] The configuration circuit 110 includes a configuration input terminal and a configuration output terminal. The configuration input terminal receives a serial port signal, and the configuration output terminal outputs a first configuration signal and a second configuration signal.

[0056] The first signal selection circuit 120 includes a plurality of first input terminals, a first configuration control terminal, a first high-order output terminal, and a first low-order output terminal. Each first input terminal receives a first signal to be verified. When the first configuration control terminal receives the first configuration signal, the first signal selection circuit 120 selects a first signal to be verified and splits it into a first high-order signal and a first low-order signal. The first high-order output terminal outputs the first high-order signal, and the first low-order output terminal outputs the first low-order signal.

[0057] The second signal selection circuit 130 includes multiple second input terminals, a second configuration control terminal, a second high-order output terminal and a second low-order output terminal; each second input terminal is connected to a first signal to be verified. When the second configuration control terminal receives the first configuration signal, the second signal selection circuit 130 selects a first signal to be verified and splits it into a second high-order signal and a second low-order signal. The second high-order output terminal outputs the second high-order signal, and the second low-order output terminal outputs the second low-order signal.

[0058] The first signal combination circuit 140 includes a third configuration control terminal and multiple first combination input terminals, and receives a first high-order signal, a first low-order signal, a second high-order signal, and a second low-order signal. When the third configuration control terminal receives the first configuration signal, the first signal combination circuit 140 selects any two of the first high-order signal, the first low-order signal, the second high-order signal, and the second low-order signal to combine to form a combination verification signal, and the first signal combination circuit 140 outputs the combination verification signal to the logic analyzer.

[0059] Specifically, the configuration input end is specifically used to receive external serial port signals. These serial port signals are usually digital signals transmitted through a serial communication interface and can come from a computer, a microcontroller or other electronic devices.

[0060] The configuration output terminal is responsible for outputting the processed serial port signals. The first and second configuration signals are two different output signals, representing different control commands. The first configuration signal is used to combine, select, and split the verification signals, while the second configuration signal is used to switch the output mode of the combined verification signal.

[0061] The first signal selection circuit 120 receives multiple first signals to be verified. Based on the first configuration signal output by the configuration circuit 110, the first signal selection circuit 120 selects one of the multiple first signals to be verified and splits it into a first high-order signal and a first low-order signal. For example, if there are 32 first signals to be verified, the first signal selection circuit 120 selects one of the 32 signals to be verified and splits it.

[0062] The second signal selection circuit 130 has the same working mechanism as the first signal selection circuit 120 . The difference lies in that the first signal selection circuit 120 and the second signal selection circuit 130 select different first signals to be verified, which will not be described in detail here.

[0063] The first select input and second select input of first signal combination circuit 140 are two data input ports within first signal combination circuit 140. These inputs can receive multiple signals, originating from the first high-order output, the first low-order output, the second high-order output, and the second low-order output. Specifically, these signals receive four high-order and low-order signals from first signal selection circuit 120 and second signal selection circuit 130. Based on the first configuration signal, any two of the four high-order and low-order signals can be selected and combined into a combined verification signal. If the second configuration signal is not received, first signal combination circuit 140 defaults to outputting the combined verification signal to the internal logic analyzer.

[0064] The verification device provided by the utility model realizes free combination and selection between different signals to be verified by configuring the circuit to control the selection of the first signal selection circuit, the second signal selection circuit and the first signal combination circuit.

[0065] An embodiment of the present invention, based on the above embodiment, please refer to Figure 2 The field programmable gate array verification device 100 further includes: a plurality of second signal combination circuits 150 .

[0066] The second signal combination circuit 150 includes multiple second combination input terminals and a fourth configuration control terminal. Each second combination input terminal receives a second signal to be verified, and the fourth configuration control terminal is connected to the configuration output terminal. When the fourth configuration control terminal receives the first configuration signal, the second signal combination circuit 150 selects the second signals to be verified and combines them into a first signal to be verified. The second signal combination circuit 150 outputs the first signal to be verified to the first signal selection circuit 120 and the second signal selection circuit 130.

[0067] Specifically, the second signal combination circuit 150 includes several multiplexers, and a total of 16 32-bit second signals to be verified are connected to the second signal combination circuit 150. After the second signal combination circuit 150 splits and combines the 16 second signals to be verified, 32 32-bit first signals to be verified can be formed.

[0068] like Figure 3 As shown, a single second signal to be verified is split and combined to form a first signal to be verified. The following only describes the input of a 32-bit second signal to be verified. After the second signal to be verified is input, each 32-bit second signal to be verified is first split into 0-7bit Signal, 8-15bit Signal, 16-23bit Signal, and 24-31bit Signal according to the high and low bits of the data, and input them into the first multiplexer 151a, the first multiplexer 151b, the first multiplexer 151c, and the first multiplexer 151d respectively, with each Byte signal being 8 bits. All the split Byte signals are rearranged, and the 0-7bit Signals split from the 16 second signals to be verified are all connected to the first multiplexer 151a. The splitting mechanism of the first multiplexer 151b, the first multiplexer 151c, and the first multiplexer 151d is similar and will not be elaborated on here.

[0069] Based on the byte signal selection of the first configuration signal, a byte signal is selected from each of the four first multiplexers and combined to form a 32-bit first signal to be verified. In the present invention, the four first multiplexers are grouped to form one first signal to be verified. To form 32 first signals to be verified, 32 groups of byte signals are required.

[0070] Through the field programmable gate array verification device proposed by the present invention, the second signal combination circuit selects the combination of the original to-be-verified signals according to the selection of the configuration signal, and outputs the preliminary combined first to-be-verified signals to the two signal selection circuits.

[0071] One embodiment of the present invention, as Figure 4 As shown, the first signal selection circuit 120 , the second signal selection circuit 130 , and the first signal combination circuit 140 all include multiplexers.

[0072] Specifically, the second and third multiplexers receive 32 32-bit first signals to be verified. Based on the first configuration signal, the second multiplexer selects one signal from the 32 first signals to be verified and then splits the first signal to be verified into a 16-bit first high-bit signal and a 16-bit first low-bit signal based on the high and low bits. Similarly, the third multiplexer splits the signal into a second high-bit signal and a second low-bit signal.

[0073] The fourth multiplexer receives four 16-bit signals from the second multiplexer and the third multiplexer, and according to the first configuration signal, can select any two 16-bit information and combine them into a 32-bit combined verification signal for output.

[0074] Through the verification device of the field programmable gate array proposed in the utility model, the first / second channel multiplexer splits the first signal to be verified into a high-order signal and a low-order signal, and the dual-channel multiplexer selects two from the four high-order and low-order signals according to configuration requirements to combine to form a combined verification signal, thereby realizing free combination and selection between different signals to be verified.

[0075] An embodiment of the present invention, please refer to Figure 5 Based on the above embodiment, the field programmable gate array verification device 100 further includes: an output circuit 160.

[0076] The output circuit 160 includes a fifth configuration control terminal. The input terminal of the output circuit 160 is connected to the output terminal of the first signal combination circuit 140, and the fifth configuration control terminal is connected to the configuration output terminal. When the fifth configuration control terminal receives the second configuration signal, the input terminal of the output circuit 160 receives the combination verification signal, and the output terminal of the output circuit 160 outputs the combination verification signal to the pin of the field programmable gate array.

[0077] Specifically, such as Figure 6 As shown, the output circuit 160 is composed of a multiplexer. When the configuration circuit 110 outputs the second configuration signal to the output circuit 160, the output mode of the output combination verification signal is switched, that is, the function pin signal of the FPGA is set from 0 to 1, and the combination verification signal is output to the FPGA pin through the fifth multiplexer.

[0078] Using an oscilloscope or external logic analyzer, you can directly observe verification signals on FPGA pins. This eliminates the limitations of using an internal logic analyzer, which requires a downloader to connect to FPGA development tools on a computer, making it applicable to a wider range of scenarios. Furthermore, when the number of available FPGA pins is limited, you can switch the output of combined verification signals by simply routing the combined verification signals of the modules you want to observe to specific pins.

[0079] Through the field programmable gate array verification device proposed in the utility model, the output of the FPGA's own pins is not limited to traditional observation methods, and an external logic analyzer or oscilloscope can be used for analysis and observation, which is applicable to more scenarios.

[0080] In one embodiment of the present invention, the configuration circuit 110 includes: a verification circuit 111 and a receiving control circuit 112 .

[0081] The verification circuit 111 includes a configuration input terminal; the configuration input terminal receives the serial port signal, the verification circuit 111 verifies and analyzes the serial port signal to form a data signal and a verification result signal, and the output terminal of the verification circuit 111 outputs the data signal and the verification result signal;

[0082] The receiving control circuit 112 is connected to the verification circuit 111 and includes a configuration output terminal; the input terminal of the receiving control circuit 112 receives the data signal, the verification result signal and the clock signal, and the receiving control circuit 112 configures the data signal and outputs the first configuration signal and / or the second configuration signal at the output terminal.

[0083] Specifically, verification circuit 111 verifies the serial port signal. Only if the verification result signal is correct can reception control circuit 112 convert the serial port signal into the first configuration signal or the second configuration signal. The first / second configuration signal includes four parts: byte signal selection, combination verification signal selection, high and low bit signal selection, and output type selection.

[0084] like Figure 7 As shown, the verification circuit 111 includes a serial port register and an XOR logic gate, while the reception control circuit 112 includes a multiplexer, a counter register, an adder, an equals logic gate, and a data register. The serial port signal is first output to the serial port register, then split into a data signal and a verification result signal. The verification result signal is then transmitted to the sixth multiplexer via an XOR logic gate.

[0085] The counting register is driven by the clock signal (CLK) to accumulate through the adder. When the result of the counting register is equal to the set serial port baud rate parameter after being determined by the equal logic gate, the signal is transmitted to the sixth multiplexer.

[0086] The serial port multiplexer places the check result signal and the data signal into different bits of the 8-bit receive data register. When all 8 bits of data in the receive data register are placed, they are buffered in the FIFO as the first configuration signal / second configuration signal. The data output from the FIFO is then used as the configuration signal.

[0087] like Figure 8The figure shows a schematic diagram of the circuit for outputting the configuration information of the verification signal as a serial port signal. The TYPE-C chip is used to implement the TYPE interface; the serial port chip converts the configuration information of the verification signal into a serial port signal and sends it to the configuration circuit 110; UART_XI0 is a crystal oscillator that provides the operating clock for the serial port.

[0088] The configuration circuit 110 forms an 8-bit configuration signal. For example, when the second signal combination circuit combines the second to-be-verified signal to form the first to-be-verified signal, the lower 4 bits are selected by one multiplexer from 16 verification signals, and the upper 4 bits are selected by another multiplexer from 16 verification signals. For example, when the value is equal to 0xa6, the first multiplexer selects the 6th verification signal, and the other multiplexer selects the 10th verification signal.

[0089] When the first signal combination circuit selects the high-order signal and the low-order signal in the first / second signal selection circuit, the lower five bits are selected from the 32 high-order / low-order signals in the first / second channel selector. For example, when it is equal to 0x1a, channel A selects the 26th combination signal.

[0090] When the first signal combination circuit is combining, the upper 2 bits are used by the dual-channel multiplexer to select the combination of the four 16-bit signals output by the first signal selection circuit and the second signal selection circuit, namely 00 (first high-order signal + first low-order signal), 01 (first high-order signal + second low-order signal), 10 (second high-order signal + first low-order signal), and 11 (second high-order signal + second low-order signal).

[0091] When the output circuit switches the FPGA pin, the lower bit is selected. Configuring it to 0 selects the FPGA's function pin signal, and configuring it to 1 selects the output verification signal.

[0092] Through the field programmable gate array verification device proposed by the utility model, the verification circuit will verify the serial port signal, and the receiving control circuit will convert the serial port serial signal into a received configuration signal. At the same time, the configuration signal can only be output if the verification result signal is correct.

[0093] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0094] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0096] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0097] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A field programmable gate array verification device, characterized in that: include: A configuration circuit includes a configuration input terminal and a configuration output terminal, wherein the configuration input terminal receives a serial port signal and the configuration output terminal outputs a first configuration signal and a second configuration signal; A first signal selection circuit includes a plurality of first input terminals, a first configuration control terminal, a first high-order output terminal, and a first low-order output terminal; each first input terminal is connected to a first signal to be verified, and when the first configuration control terminal receives the first configuration signal, the first signal selection circuit selects one of the first signal to be verified and splits it into a first high-order signal and a first low-order signal, the first high-order output terminal outputs the first high-order signal, and the first low-order output terminal outputs the first low-order signal; The second signal selection circuit includes a plurality of second input terminals, a second configuration control terminal, a second high-order output terminal, and a second low-order output terminal; each second input terminal is connected to a first signal to be verified, and when the second configuration control terminal receives the first configuration signal, the second signal selection circuit selects one of the first signal to be verified and splits it into a second high-order signal and a second low-order signal, the second high-order output terminal outputs the second high-order signal, and the second low-order output terminal outputs the second low-order signal; The first signal combination circuit includes a third configuration control terminal and multiple first combination input terminals, and receives the first high-order signal, the first low-order signal, the second high-order signal, and the second low-order signal; when the third configuration control terminal receives the first configuration signal, the first signal combination circuit selects any two of the first high-order signal, the first low-order signal, the second high-order signal, and the second low-order signal to combine to form a combination verification signal, and the first signal combination circuit outputs the combination verification signal to the logic analyzer.

2. The field programmable gate array verification device according to claim 1, wherein: Also includes: Multiple second signal combination circuits include multiple second combination input terminals and a fourth configuration control terminal, each second combination input terminal is connected to a second signal to be verified, and the fourth configuration control terminal is connected to the configuration output terminal; when the fourth configuration control terminal receives the first configuration signal, the second signal combination circuit selects the second signal to be verified and combines it to form the first signal to be verified, and the second signal combination circuit outputs the first signal to be verified to the first signal selection circuit and the second signal selection circuit.

3. The field programmable gate array verification device according to claim 2, wherein: The first signal selection circuit, the second signal selection circuit, the first signal combination circuit, and the second signal combination circuit respectively include a multiplexer or an integrated circuit that implements a multiplex selection function.

4. The field programmable gate array verification device according to claim 1, wherein: The configuration circuit includes: A verification circuit, comprising the configuration input terminal; the configuration input terminal is connected to the serial port signal, the verification circuit verifies and analyzes the serial port signal to form a data signal and a verification result signal, and the output terminal of the verification circuit outputs the data signal and the verification result signal; A receiving control circuit is connected to the verification circuit and includes the configuration output end; the input end of the receiving control circuit is connected to the data signal, the verification result signal and the clock signal, and the receiving control circuit configures the data signal and outputs a first configuration signal and / or a second configuration signal.

5. The field programmable gate array verification device according to claim 4, characterized in that: The verification circuit comprises: A serial port register, one end of which receives the serial port signal and the other end of which outputs the data signal and the check signal; An XOR logic gate receives the data signal and the verification signal at one end and outputs the verification result signal at the other end.

6. The field programmable gate array verification device according to claim 4, characterized in that: The receiving control circuit includes: an equal logic gate and an adder, wherein one end of the equal logic gate is connected to the adder; a counting register, one end of which receives the clock signal and the other end of which is connected to the adder; a multiplexer, the multiplexer being connected to the verification circuit and the equal logic gate, the other end of the equal logic gate being connected to the multiplexer, and the multiplexer outputting the data signal; A data register, one end of which is connected to the multiplexer, and the other end of which outputs the first configuration signal and / or the second configuration signal.

7. The field programmable gate array verification device according to any one of claims 1 to 6, characterized in that: Also includes: an output circuit, comprising a fifth configuration control terminal, wherein the input terminal of the output circuit is connected to the output terminal of the first signal combination circuit, and the fifth configuration control terminal is connected to the configuration output terminal; When the fifth configuration control terminal receives the second configuration signal, the input terminal of the output circuit receives the combination verification signal, and the output terminal of the output circuit outputs the combination verification signal to the pin of the field programmable gate array.

8. The field programmable gate array verification device according to claim 7, characterized in that: The output circuit includes a multiplexer or an integrated circuit that implements a multiplex selection function.

9. A field programmable gate array verification system, characterized in that: A verification device comprising a field programmable gate array according to any one of claims 1 to 8, further comprising: A plurality of modules to be verified output signals to be verified, and the signals to be verified are combined by the verification device of the field programmable gate array to output a combined verification signal.

10. The field programmable gate array verification system according to claim 9, wherein: Also includes: Interface chip, used to output configuration information; A serial port chip is used to output the configuration information as a serial port signal, and output the serial port signal to the verification device of the field programmable gate array.

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