Power input switching circuit and power supply device

Abstract

The utility model discloses a power supply input switching circuit and a power supply device. The power supply input switching circuit comprises a buck converter module and a switch control module. The buck converter module is connected in parallel with the switch control module, the input end of the buck converter module is connected with an input power supply, and the output end of the buck converter module is connected with a post-stage circuit; wherein the buck converter module is used for enabling conduction when an input voltage provided by an input power supply exceeds a preset voltage threshold value and closing when the input voltage does not exceed the preset voltage threshold value; the switch control module is used for conducting when the input voltage provided by the input power supply does not exceed a preset voltage threshold value and closing when the input voltage exceeds the preset voltage threshold value. According to the utility model, the power supply access of the buck converter module or the switch control module to the post-stage circuit is automatically switched according to the specific condition of the input voltage provided by the input power supply, the circuit cost is low, and the power supply efficiency during low voltage input is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to power supply switching circuit technical field, concretely relates to power input switching circuit and power supply device. BACKGROUND

[0002] At present, partial electric equipment supports wide voltage input, and the range of input voltage is 9V~32V. Generally, BUCK-BOOST type DC-DC converter (BUCK-BOOST is BUCK-BOOST Converter and represents buck-boost converter, and DC-DC converter represents direct current-direct current converter) is added to the power input end of electric equipment in actual circuit, and the input voltage is converted to 12V vicinity, to meet the use demand of the subsequent circuit.

[0003] In order to meet the demand of high power of electric equipment, the DC-DC converter in BUCK-BOOST type DC-DC converter will adopt the form of external MOSFET (the full name of MOSFET is Metal-Oxide-Semiconductor Field-Effect Transistor, which represents metal-oxide semiconductor field effect transistor, and is commonly divided into P channel MOSFET and N channel MOSFET). The power supply topology of BUCK-BOOST type DC-DC converter has the following defects:

[0004] 1) it needs at least 4 NMOSFET tubes, and the circuit design is relatively complex, the PCB (circuit board) occupies larger area, and the cost is also relatively high;

[0005] 2) when the input power is less than 12V, BUCK-BOOST type DC-DC converter works in BOOST or BUCK-BOOST mixed mode, and the maximum working current of inductance is much larger than BUCK mode;

[0006] 3) when the input power is 12V, BUCK-BOOST type DC-DC converter still works, and the power conversion efficiency is reduced;

[0007] 4) the influence of power ripple at the switching frequency of BUCK-BOOST type DC-DC converter working on radio frequency circuit must be considered under any input voltage;

[0008] It can be seen that the power supply topology of the above-mentioned BUCK-BOOST type DC-DC converter has the problems of complex design, large occupied area, high cost and low voltage input power efficiency. SUMMARY

[0009] The utility model provides a kind of power input switching circuit and power supply device, to solve the power supply topology of the power consumption equipment using BUCK-BOOST type DC-DC converter in prior art, there is the problem of complex design and low-voltage input power supply efficiency.

[0010] In the first aspect, the utility model provides a kind of power input switching circuit, it is characterized in that, including step-down converter module and switch control module;The step-down converter module is connected in parallel with the switch control module, the input end of the step-down converter module is connected with input power supply, and the output end of the step-down converter module is connected with the circuit of later stage;

[0011] The step-down converter module is used to enable conduction when the input voltage provided by input power supply exceeds preset voltage threshold, and is closed when the input voltage provided by input power supply does not exceed preset voltage threshold;

[0012] The switch control module is used to conduct when the input voltage provided by input power supply does not exceed preset voltage threshold, and is closed when the input voltage provided by input power supply exceeds preset voltage threshold.

[0013] In the second aspect, the utility model further provides a kind of power supply device, including the power input switching circuit and input power supply described in the first aspect, the input end of the power input switching circuit is connected with input power supply, and the output end of the power input switching circuit is used to be connected with electric device to carry out power supply.

[0014] Compared with prior art, the utility model provides power input switching circuit and power supply device, including step-down converter module and switch control module;The step-down converter module is connected in parallel with the switch control module, the input end of the step-down converter module is connected with input power supply, and the output end of the step-down converter module is connected with the circuit of later stage;The step-down converter module is used to enable conduction when the input voltage provided by input power supply exceeds preset voltage threshold, and is closed when the input voltage provided by input power supply does not exceed preset voltage threshold;The switch control module is used to conduct when the input voltage provided by input power supply does not exceed preset voltage threshold, and is closed when the input voltage provided by input power supply exceeds preset voltage threshold.The utility model automatically switches the power supply path of step-down converter module or switch control module to the circuit of later stage by the specific situation of input voltage provided by input power supply. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the utility model embodiment technical scheme, the following will be needed to use the drawings in embodiment description briefly introduced, obviously, the following description in the drawings is some embodiments of the utility model, for those skilled in the art, without creating labor, according to these drawings, other drawings can also be obtained.

[0016] Figure 1 a schematic block diagram of the power input switching circuit provided by the present application;

[0017] Figure 2 a schematic block diagram of the first embodiment of the power input switching circuit provided by the present application;

[0018] Figure 3 a circuit structure schematic diagram of the first reference voltage stabilizing unit in the first embodiment of the power input switching circuit provided by the present application;

[0019] Figure 4 a circuit structure schematic diagram of the first voltage comparator unit in the first embodiment of the power input switching circuit provided by the present application;

[0020] Figure 5 a circuit structure schematic diagram of the first reset unit in the first embodiment of the power input switching circuit provided by the present application;

[0021] Figure 6 a circuit structure schematic diagram of the first PMOSFET switch unit in the first embodiment of the power input switching circuit provided by the present application;

[0022] Figure 7 a circuit structure schematic diagram of the first DC-DC step-down converter unit in the first embodiment of the power input switching circuit provided by the present application;

[0023] Figure 8 a schematic block diagram of the second embodiment of the power input switching circuit provided by the present application;

[0024] Figure 9 a circuit structure schematic diagram of the second PMOSFET switch unit and the second DC-DC step-down converter unit in the second embodiment of the power input switching circuit provided by the present application;

[0025] Figure 10 a circuit structure schematic diagram of the third PMOSFET switch unit in the second embodiment of the power input switching circuit provided by the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0027] The terms of direction mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side surface" and the like, are only the directions of reference to the attached drawings. Therefore, the terms of direction are used to explain and understand the present application, but not to limit the present application. In addition, in the drawings, the structures similar or identical are indicated by the same reference numerals.

[0028] It should be understood that the terms "comprise" and "include" as used in the specification and the appended claims indicate the presence of the recited features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should be further understood that the term "and / or" as used in the present application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0031] Please refer to Figure 1 , which is a schematic block diagram of the power input switching circuit provided by the present application. As Figure 1 shown, the present application embodiment provides a power input switching circuit, which comprises: a step-down converter module 10 and a switch control module 20; the step-down converter module 10 and the switch control module 20 are connected in parallel, the input end of the step-down converter module 10 is connected with an input power 30, and the output end of the step-down converter module 10 is connected with a rear-stage circuit 40;

[0032] The step-down converter module 10 is used to enable conduction when the input voltage provided by the input power 30 exceeds the preset voltage threshold, and is used to close when the input voltage provided by the input power 30 does not exceed the preset voltage threshold.

[0033] The switch control module 20 is used to conduct when the input voltage provided by the input power 30 does not exceed the preset voltage threshold, and is used to close when the input voltage provided by the input power 30 exceeds the preset voltage threshold.

[0034] In the embodiment, the power input switching circuit can be applied to the electrical equipment powered by the DC power supply. Specifically, the input end of the power input switching circuit is connected with the output end of the DC power supply, and the output end of the power input switching circuit is connected with the rear circuit in the electrical equipment. For example, one of the 12V storage battery or the 24V storage battery is taken as the power supply battery (i.e. the DC power supply) in the application, that is, the power supply of the power supply battery is one of the 12V or 24V system. The voltage range of the 12V storage battery is 10V-16V, and the voltage range of the 24V storage battery is 19V-28V. The voltage ranges of the two have no intersection. In the case that the power supply of the power supply battery is the 12V or 24V system, only one of the buck converter module 10 and the switch control module 20 included in the power input switching circuit is in the on state and the other is in the off state.

[0035] In order to more accurately determine the on / off state of the buck converter module 10 and the on / off state of the switch control module 20, the output voltage of the input power supply 30 needs to be sampled first to obtain the input voltage. When it is determined that the input voltage exceeds the preset voltage threshold (such as 16V, of course, the specific implementation is not limited to 16V, and other voltage values based on actual needs can also be set), the buck converter module 10 is enabled to be on and the switch control module 20 is off; when it is determined that the input voltage does not exceed the preset voltage threshold, the buck converter module 10 is off and the switch control module 20 is on. As can be seen, by using the above circuit structure, the specific situation of the input voltage provided by the input power supply is used to automatically switch the power supply path of the rear circuit, that is, one of the buck converter module and the switch control module is automatically selected to be on to supply power to the rear circuit. Moreover, in the case of low voltage input in which the input voltage provided by the input power supply does not exceed the preset voltage threshold, the power supply efficiency can be ensured to be close to 100%, and there is no EMI (full name is Electromagnetic Interference, which means electromagnetic interference) problem.

[0036] It should be noted that the input voltage of the input power supply 30 can be fixed or variable. The specific technical solutions of the power input switching circuit when the input voltage of the input power supply 30 is fixed and the specific technical solutions of the power input switching circuit when the input voltage of the input power supply 30 is variable will be described below.

[0037] In an embodiment, when the input voltage of the input power supply 30 is fixed, the first embodiment of the buck converter module 10 is taken as an example, as shown in FIG. 1, the input end of the power input switching circuit is connected with the output end of the DC power supply, and the output end of the power input switching circuit is connected with the rear circuit in the electrical equipment. Figure 2As shown, the buck converter module 10 includes a first DC-DC buck converter unit 11; the input end of the first DC-DC buck converter unit 11 is connected to the input power supply 30, and the output end of the first DC-DC buck converter unit 11 is connected to the subsequent circuit 40.

[0038] In this embodiment, in the first embodiment of the buck converter module 10, the buck converter module 10 used is specifically a first DC-DC buck converter unit 11, which is a BUCK DC-DC converter (which supports most BUCK DC-DC chips and is easy to select), and the corresponding working mode is the buck mode (there is no boost mode and buck-boost mixed mode).

[0039] The first DC-DC buck converter unit 11 is enabled to conduct when it is determined that the input voltage provided by the input power source exceeds the preset voltage threshold, and the input voltage is stepped down to a preset operating voltage (wherein the preset operating voltage is less than the preset voltage threshold, for example, the preset operating voltage is 13.6V. Of course, in the specific implementation, it is not limited to 13.6V, and can also be other voltage values ​​set based on actual needs), and the preset operating voltage output by the first DC-DC buck converter unit 11 is provided to the subsequent circuit 40. At the same time, the switch control module 20 is turned off (turning off can also be understood as cutting off) when the first DC-DC buck converter unit 11 is enabled to conduct. Among them, the above-mentioned working mode of the power input switching circuit can be regarded as a buck mode.

[0040] The first DC-DC buck converter unit 11 is turned off when it is determined that the input voltage provided by the input power supply does not exceed the preset voltage threshold. At the same time, the switch control module 20 is turned on when the first DC-DC buck converter unit 11 is turned off, and the output voltage of the switch control module 20 is equal to the input voltage provided by the input power supply, and the output voltage of the switch control module 20 is provided to the subsequent circuit 40. Among them, the above-mentioned working mode of the power input switching circuit can be regarded as a bypass mode (i.e., Bypass mode). It can be seen that the first DC-DC buck converter unit used when the input power supply has a fixed input voltage can effectively reduce the input voltage provided by the input power supply when it is determined that the input voltage provided by the input power supply exceeds the preset voltage threshold.

[0041] It should be noted that the first DC-DC step-down converter unit 11 and the switch control module 20 need to confirm the working state of the entire circuit when the power input switching circuit starts to work. For example, the first DC-DC step-down converter unit 11 and the switch control module 20 are initially in the off state to ensure that the entire circuit will not cause damage to the subsequent circuit 40 when powered on. Then, after the entire circuit state is stable and the input voltage provided by the input power is determined, one of the first DC-DC step-down converter unit 11 and the switch control module 20 is turned on.

[0042] In an embodiment, as the first embodiment of the switch control module 20, it is used in combination with the first embodiment of the step-down converter module 10. As shown in FIG. 2, the switch control module 20 includes a first reference voltage stabilizing unit 21, a first voltage comparator unit 22, a first reset unit 23, and a first PMOSFET switch unit 24. The first reference voltage stabilizing unit 21 is connected to the input power 30. The first voltage comparator unit 22 is connected to the input power 30, the first reference voltage stabilizing unit 21, and the first PMOSFET switch unit 24. The first reset unit 23 is connected to the first reference voltage stabilizing unit 21 and the first PMOSFET switch unit 24. The first PMOSFET switch unit 24 is connected to the subsequent circuit 40. Figure 2 In this embodiment, the switch control module 20 is the core module of the power input switching circuit in the bypass mode. Specifically, the first voltage comparator unit 22 compares the size relationship between the voltage corresponding to the voltage corresponding to the voltage provided by the first reference voltage stabilizing unit 21 (such as 5V) and the voltage corresponding to the input voltage provided by the input power 30. When the first voltage comparator unit 22 determines that the voltage corresponding to the input voltage provided by the input power 30 is greater than the voltage corresponding to the voltage provided by the first reference voltage stabilizing unit 21, a low voltage (such as 0V) is output. When the first voltage comparator unit 22 determines that the voltage corresponding to the input voltage provided by the input power 30 is less than or equal to the voltage corresponding to the voltage provided by the first reference voltage stabilizing unit 21, a specified output voltage (such as 5V, which is equal to the voltage provided by the first reference voltage stabilizing unit 21) is output.

[0043] Moreover, the first reset unit 23 can first forcibly clamp and close the first DC-DC step-down converter unit 11 and the first PMOSFET switch unit 24 when the entire circuit is powered on, and the subsequent circuit has no power supply at this time. The first reset unit 23 establishes a stable system state within a short reset time (such as 0.14s).

[0044]

[0045] ​Assuming that the input voltage Vin provided by the input power supply 30 is 12V, the first state signal V_DET outputted by the first voltage comparator unit 22 is 5V, at this time the first PMOSFET switch unit 24 is turned on, the voltage of the enable pin in the first DC-DC step-down converter unit 11 is close to 0V, and the first DC-DC step-down converter unit 11 is turned off. At this time, the output voltage of the first PMOSFET switch unit 24 is Vout=Vin=12V.

[0046] Assuming that the input voltage Vin provided by the input power supply 30 is 24V, the first state signal V_DET outputted by the first voltage comparator unit 22 is 0V, at this time the first PMOSFET switch unit 24 is turned off, the voltage of the enable pin in the first DC-DC step-down converter unit 11 is greater than 0V, so that the first DC-DC step-down converter unit 11 is turned on, and the preset operating voltage outputted by the first DC-DC step-down converter unit 11 is provided to the subsequent circuit 40. It can be seen that the parallel arrangement of the above-mentioned switch control module and step-down converter module can effectively automatically switch the power supply path according to the input voltage.

[0047] In an embodiment, as shown in Figure 2 and Figure 3 The first reference voltage source chip U1, the first resistor R1, the second resistor R2, the third resistor R3 and the first capacitor C1 are connected in series. The first end of the first resistor R1 is connected with the input power supply 30, the second end of the first resistor R1 is connected with the CAT pin of the first reference voltage source chip U1 and the first end of the second resistor R2, and the second end of the first resistor R1 is also grounded through the first capacitor C1. The second end of the second resistor R2 is connected with the REF pin of the first reference voltage source chip U1, and is also grounded through the third resistor R3. The ANO pin of the first reference voltage source chip U1 is grounded.

[0048] In the embodiment, when the first reference voltage source chip U1 needs to provide a stable and accurate 5V power supply, the output voltage Vcc of the CAT pin of the first reference voltage source chip U1 corresponds to the calculation formula Vcc=(1+R2 / R3)*2.5V, and when the resistance values of the first resistor R2 and the third resistor R3 are equal, the output voltage Vcc is 5V. It can be seen that the first reference voltage source chip U1 can provide a stable and accurate 5V power supply and supply power to other circuit units.

[0049] In the embodiment, the first reference voltage source chip U1 can be a reference voltage source chip TL431, and the above chip model is only used as an example. In the embodiment, the first reference voltage source chip U1 can also be a reference voltage source chip of other models according to actual needs.

[0050] In one embodiment, if Figures 2-4 As shown, the first voltage comparator unit 22 includes a first comparator U2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a second capacitor C2; a first end of the fourth resistor R4 is connected to the input power supply 30, a second end of the fourth resistor R4 is connected to the negative input pin of the first comparator U2, and a second end of the fourth resistor R4 is also grounded through the fifth resistor R5; a first end of the sixth resistor R6 is connected to the CAT pin of the first reference voltage source chip, a second end of the sixth resistor R6 is connected to the positive input pin of the first comparator U2, and a second end of the sixth resistor R6 is also grounded through the seventh resistor R7; a Vcc pin of the first comparator U2 is connected to the CAT pin of the first reference voltage source chip and is also grounded through the second capacitor C2; a Vss pin of the first comparator U2 is grounded; a Vo pin of the first comparator U2 is connected to the first PMOSFET switch unit 24 and is also connected to the Vcc pin of the first comparator U2 through the eighth resistor R8.

[0051] In this embodiment, the first comparator U2 can be implemented as an SGM8701 comparator, which is a single-channel push-pull output ultra-low power comparator with a quiescent current of 295nA and a supply voltage of 1.4V to 5.5V. Of course, the above chip model is for example only, and the first comparator U2 can also use other models in specific implementations according to actual needs.

[0052] The input voltage Vin provided by the input power source 30 is divided by the fourth resistor R4 and the fifth resistor R5, and the voltage across the fifth resistor R5 serves as the input voltage of the negative input pin of the first comparator U2. The 5V voltage provided by the first reference voltage stabilizing unit 21 is divided by the sixth resistor R6 and the seventh resistor R7, and the voltage across the seventh resistor R7 serves as the input voltage of the positive input pin of the first comparator U2. When the input voltage Vin exceeds a preset voltage threshold (e.g., 16V), the input voltage of the negative input pin of the first comparator U2 is greater than the input voltage of the positive input pin of the first comparator U2. At this time, the output voltage corresponding to the Vo pin of the first comparator U2 is 0V (i.e., the first state signal V_DET = 0V). When the input voltage Vin does not exceed a preset voltage threshold (e.g., 16V), the input voltage at the negative input pin of the first comparator U2 is less than or equal to the input voltage at the positive input pin of the first comparator U2. At this time, the output voltage corresponding to the Vo pin of the first comparator U2 is 5V (i.e., the first state signal V_DET = 5V). When the output voltage corresponding to the Vo pin of the first comparator U2 is 0V or 5V, respectively, the specific conduction status of the first PMOSFET switch unit 24 can be determined. It can be seen that the first voltage comparator unit based on the above circuit structure can compare the magnitude relationship between the input voltage and the standard regulated voltage provided by the first reference voltage regulator unit to obtain a first state signal, and select one path from the first DC-DC buck converter unit and the switch control module to conduct based on the first state signal.

[0053] In one embodiment, if Figures 2-5 As shown, the first reset unit 23 includes a first reset chip U3, a ninth resistor R9, a tenth resistor R10, a third capacitor C3 and a fourth capacitor C4; the VIN pin of the first reset chip U3 is connected to the CAT pin of the first reference voltage source chip U1; the VSEN pin of the first reset chip U3 is connected to the CAT pin of the first reference voltage source chip U1 through the ninth resistor R9, and is also grounded through the third capacitor C3; the CD pin of the first reset chip U3 is grounded through the fourth capacitor C4; the VOUT pin of the first reset chip U3 is connected to the CAT pin of the first reference voltage source chip U1 through the tenth resistor R10, and is also connected to the first PMOSFET switch unit 24; the VSS pin of the first reset chip U3 is grounded.

[0054] In this embodiment, the first reset chip U3 can be implemented as a reset chip model XC6118N28AMR, which has an independent voltage detection terminal and an external capacitive voltage detector. Of course, the above chip model is for example only, and the first reset chip U3 can also use other reset chip models according to actual needs.

[0055] When the entire circuit is powered on, the first reset chip U3 forcibly clamps and shuts down the first DC-DC buck converter unit 11 and the first PMOSFET switch unit 24. Specifically, the VOUT pin of the first reset chip U3 outputs a second state signal, RESET = 0V. Upon receiving this low-level 0V signal, the first PMOSFET switch unit 24 is forced to clamp and shut down, forcing the first DC-DC buck converter unit to also be clamped shut. After the entire circuit establishes a stable system state within a short reset time (e.g., 0.14s), the Vo pin of the first comparator U2 outputs V_DET. Thus, the first reset unit, employing the above circuit structure, can provide a second state signal corresponding to the actual operating state of the entire circuit.

[0056] In one embodiment, if Figures 2-6 As shown, the first PMOSFET switch unit 24 includes a first PMOSFET tube Q1, a first MOS tube Q2, a first diode D1, a second diode D2, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a fifth capacitor C5; the cathode of the first diode D1 is connected to the VOUT pin of the first reset chip U3; the anode of the first diode D2 is connected to the CAT pin of the first reference voltage source chip U1 through the eleventh resistor R11, and is also connected to the gate of the first MOS tube Q2; the cathode of the second diode D2 is connected to the Vo pin of the first comparator U2 The anode of the second diode D2 is connected to the gate of the first MOS transistor Q2; the source of the first MOS transistor Q2 is grounded, and the drain of the first MOS transistor Q2 is connected to the first end of the twelfth resistor R12; the second end of the twelfth resistor R12 is connected to the gate of the first PMOSFET transistor Q1, and is connected to the input power supply 30 through the thirteenth resistor R13, and is also connected to the input power supply 30 through the fifth capacitor C5; the source of the first PMOSFET transistor Q1 is connected to the input power supply 30, and the drain of the first PMOSFET transistor Q1 is connected to the post-stage circuit 40.

[0057] In this embodiment, the first PMOSFET transistor Q1 used in the first PMOSFET switch unit 24 is a P-channel metal-oxide semiconductor field-effect transistor. When the gate of the first PMOSFET transistor Q1 is grounded (i.e., a low level is provided), the first PMOSFET transistor Q1 is in the on state; when the first PMOSFET transistor Q1 is directly connected to the input power supply 30 (i.e., a high level is provided), the first PMOSFET transistor Q1 is in the off state.

[0058] The input voltage of the gate of the first MOS Q2 is determined by the first state signal V_DET outputted from the Vo pin of the first comparator U2 and the second state signal RESET outputted from the VOUT pin of the first reset chip U3. For example, when the first MOS Q2 is an N-type MOS, if the first state signal V_DET is 0V and the second state signal RESET is 5V, the gate of the first MOS Q2 inputs a low level, so that the first MOS Q2 is in a cut-off state, and the gate of the first PMOSFET Q1 connected to the drain of the first MOS Q2 is directly connected to the input power supply 30 (equivalent to inputting a high level), so that the first PMOSFET Q1 is in a cut-off state, and the first DC-DC step-down converter unit 11 is in a conducting state.

[0059] When the first state signal V_DET is 5V and the second state signal RESET is 5V, the gate of the first MOS Q2 inputs a high level, so that the first MOS Q2 is in a conducting state, and the gate of the first PMOSFET Q1 connected to the drain of the first MOS Q2 is grounded (equivalent to inputting a low level, wherein the source of the first MOS Q2 is grounded when the first MOS Q2 is in a conducting state, so that the gate of the first PMOSFET Q1 is grounded at this time), so that the first PMOSFET Q1 is in a conducting state, and the first DC-DC step-down converter unit 11 is in a cut-off state. Moreover, when the first PMOSFET Q1 is in a conducting state, the input voltage Vin provided by the input power supply 30 is directly provided to the subsequent circuit 40, that is, the output voltage of the first PMOSFET Q1 is Vout=Vin.

[0060] However, as long as the second state signal RESET is pulled down from 5V to 0V, whether the first state signal V_DET is 0V or 5V, the gate of the first MOS Q2 inputs a low level, so that the first MOS Q2 is in a cut-off state, and the gate of the first PMOSFET Q1 connected to the drain of the first MOS Q2 is directly connected to the input power supply 30, so that the first PMOSFET Q1 is in a cut-off state. Generally, the second state signal RESET is pulled down from 5V to 0V when the entire circuit is powered on, at which time the first DC-DC step-down converter unit 11 is also in a cut-off state. Moreover, the phenomenon that the second state signal RESET is pulled down from 5V to 0V generally lasts for a short time, for example, the entire time corresponds to the reset time and is equal to 0.14s. After the reset time ends, the second state signal RESET quickly returns to a high level state of 5V, and the entire circuit can also provide a stable first state signal V_DET. It can be seen that the first PMOSFET switching unit can more accurately determine whether to be in a conducting state or a cut-off state in combination with the output signal of the first reset chip and the output signal of the first comparator.

[0061] In one embodiment, if Figures 2-7 As shown, the first DC-DC step-down converter unit 11 includes a first DC-DC converter chip U4, a second MOS transistor Q3, a third diode D3, a fourteenth resistor R14, a fifteenth resistor R15, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a first ferrite bead FB1, a ninth capacitor C9, a fourth diode D4, a tenth capacitor C10, a first inductor L1, a sixteenth resistor R16, a seventeenth resistor R17, an eleventh capacitor C11, a twelfth capacitor C12, and a thirteenth capacitor C13; the EN pin of the first DC-DC converter chip U4 is connected to the VOUT pin of the first reset chip U3 through the third diode D3, and is grounded through the sixth capacitor C6, and is also connected to the drain of the second MOS transistor Q3; the source of the second MOS transistor Q3 is connected to the CAT pin of the first reference voltage source chip U1 through the fourteenth resistor R14, and the gate of the second MOS transistor Q3 is connected to the Vo pin of the first comparator U2 through the fifteenth resistor R15; the The GND pin and PowerPAD pin of the DC-DC converter chip U4 are both grounded; the VIN pin of the first DC-DC converter chip U4 is grounded through the seventh capacitor C7 and the eighth capacitor C8 connected in parallel, and is also connected to the input power supply 30 through the first ferrite bead FB1; the PH pin of the first DC-DC converter chip U4 is connected to the BOOT pin of the first DC-DC converter chip U4 through the ninth capacitor C9, and is grounded through the fourth diode D4 and the tenth capacitor C10 connected in parallel, and is also connected to the first end of the first inductor L1; the second end of the first inductor L1 is connected to the VSENSE pin of the first DC-DC converter chip U4 through the sixteenth resistor R11 and the eleventh capacitor C11 connected in parallel, and is grounded through the twelfth capacitor C12 and the thirteenth capacitor C13 connected in parallel, and is also connected to the post-stage circuit 40; the VSENSE pin of the first DC-DC converter chip U4 is also grounded through the seventeenth resistor R17.

[0062] In this embodiment, the first DC-DC converter chip U4 can be implemented as a high-output current PWM converter of the TPS5430 model (PWM stands for Pulse Width Modulation, which means pulse width modulation), which integrates low resistance and high-side N-channel MOSFET, and has an input voltage range of 5.5V to 36V, which can meet the input voltage requirement of 9V to 32V.

[0063] The EN pin of the first DC-DC converter chip U4 is connected with the positive pole of the third diode D3, and the negative pole of the third diode D3 is connected with the VOUT pin of the first reset chip U3 when the EN pin of the first DC-DC converter chip U4 is connected with the VOUT pin of the first reset chip U3 through the third diode D3. The PH pin of the first DC-DC converter chip U4 is grounded through the fourth diode D4 and the tenth capacitor C10 in parallel, and the positive pole of the fourth diode D4 is grounded and the negative pole of the fourth diode D4 is connected with the PH pin of the first DC-DC converter chip U4.

[0064] Moreover, the second state signal RESET corresponds to 5V when the whole circuit has been powered on and the stable circuit state is established, and the input voltage of the gate of the second MOS Q3 is determined by the first state signal V_DET output from the Vo pin of the first comparator U2. For example, when the second MOS Q3 is a P-type MOS, when the first state signal V_DET is 0V, the gate of the second MOS Q3 is connected with low voltage, so that the second MOS Q3 is turned on, the EN pin of the first DC-DC converter chip U4 is the enable pin, and the voltage is 5V, and the first DC-DC converter unit 11 is in the on state. When the first state signal V_DET is 5V, the gate of the second MOS Q3 is connected with high voltage, so that the second MOS Q3 is turned off, the EN pin of the first DC-DC converter chip U4 is the enable pin, and the voltage is 0V, and the first DC-DC converter unit 11 is in the off state. Of course, when the whole circuit is in the power-on state, the second state signal RESET corresponds to 0V, and no matter whether the second MOS Q3 is in the on or off state, the EN pin of the first DC-DC converter chip U4 is the enable pin, and the voltage is 0V, and the first DC-DC converter unit 11 is in the off state.

[0065] When the input voltage provided by the input power supply 30 (such as 24V) exceeds the preset voltage threshold (such as 16V), the first state signal V DET is 0V, and the EN pin of the first DC-DC converter chip U4 is used as an enable pin with a voltage of 5V, so that the first DC-DC step-down converter unit 11 is in a conducting state, and the input voltage is reduced to a preset working voltage (such as 13.6V) by the first DC-DC converter chip U4 and then provided to the subsequent circuit 40. When the input voltage provided by the input power supply 30 (such as 12V) does not exceed the preset voltage threshold (such as 16V), the first state signal V DET is 5V, and the EN pin of the first DC-DC converter chip U4 is used as an enable pin with a voltage of 0V, so that the first DC-DC step-down converter unit 11 is in a cut-off state. At the same time, the switch control module 20 is conducting when the first DC-DC step-down converter unit 11 is cut off, and the output voltage of the switch control module 20 is equal to the input voltage provided by the input power supply, and the output voltage of the switch control module 20 is provided to the subsequent circuit 40. It can be seen that the first DC-DC step-down converter unit with the above circuit structure can more accurately determine the conducting state or the cut-off state by combining the output signal of the first reset chip and the output signal of the first comparator.

[0066] In an embodiment, when the input voltage provided by the input power supply 30 changes, as a second embodiment of the step-down converter module 10, as shown in FIG. 2, the step-down converter module 10 includes a second DC-DC step-down converter unit 12 and a second PMOSFET switch unit 13. The input end of the second DC-DC step-down converter unit 12 is connected with the input power supply 30, and the output end of the second DC-DC step-down converter unit 12 is connected with the subsequent circuit 40 through the second PMOSFET switch unit 13. Figure 8

[0067] In this embodiment, as a second embodiment of the step-down converter module 10, the difference from the first embodiment of the step-down converter module 10 is that the second PMOSFET switch unit 13 is added between the second DC-DC step-down converter unit 12 (the circuit structure of which can refer to the first DC-DC step-down converter unit 11) and the subsequent circuit 40.

[0068] ​In order to prevent the output voltage Vout from being unstable due to repeated switching of the circuit when the input voltage Vin of the input power supply 30 approaches the preset voltage threshold (e.g. 16V), hysteresis control is added to the paths where the buck converter module 10 and the switching control module 20 are located respectively, so as to enhance the stability of the entire circuit. When the hysteresis control is added, the hysteresis voltage amplitude can be set to 0.5V.

[0069] For example, when the input voltage Vin decreases from more than 16.5V to 16.5V, the second DC-DC buck converter unit 12 is turned off under the hysteresis control of the second PMOSFET switching unit 13, and the switching control module 20 is turned on, so that the entire circuit enters the bypass mode. Only when the input voltage Vin rises and rises to more than 17V, the second DC-DC buck converter unit 12 is turned on under the hysteresis control of the second PMOSFET switching unit 13, and the switching control module 20 is turned off, so that the entire circuit enters the buck mode.

[0070] For another example, when the input voltage Vin rises from less than 15.5V to 15.5V, the second DC-DC buck converter unit 12 is turned on under the hysteresis control of the second PMOSFET switching unit 13, and the switching control module 20 is turned off, so that the entire circuit enters the buck mode. Only when the input voltage Vin decreases and decreases to less than 15V, the second DC-DC buck converter unit 12 is turned off under the hysteresis control of the second PMOSFET switching unit 13, and the switching control module 20 is turned on, so that the entire circuit enters the bypass mode.

[0071] In an embodiment, as a second embodiment of the switching control module 20, it is used in combination with the second embodiment of the buck converter module 10, as shown in FIG. 2B. Figure 8 As shown in FIG. 2B, the switching control module 20 includes a second reference voltage stabilizing unit 25, a second voltage comparator unit 26, a second reset unit 27, a third PMOSFET switching unit 28, and a CPU control unit 29. The second reference voltage stabilizing unit 25 is connected with the input power supply 30. The second voltage comparator unit 26 is connected with the input power supply 30, the second reference voltage stabilizing unit 25, and the third PMOSFET switching unit 28. The second reset unit 27 is connected with the second reference voltage stabilizing unit 25 and the third PMOSFET switching unit 28. The third PMOSFET switching unit 28 is connected with the CPU control unit 29 and the subsequent circuit 40. The CPU control unit 29 is connected with the second DC-DC buck converter unit 25 and the input power supply 30.

[0072] In this embodiment, which serves as a second embodiment of the switch control module 20, the second reference voltage stabilizing unit 25 has the same circuit structure as the first reference voltage stabilizing unit 21 in the first embodiment of the switch control module 20, the second voltage comparator unit 26 has the same circuit structure as the first voltage comparator unit 22 in the first embodiment of the switch control module 20, and the second reset unit 27 has the same circuit structure as the first reset unit 23 in the first embodiment of the switch control module 20. It should be noted that the third PMOSFET switch unit 28 has a different circuit structure than the first PMOSFET switch unit 24 in the first embodiment of the switch control module 20. Furthermore, a CPU control unit 29 is added to the second embodiment of the switch control module 20.

[0073] Similarly, the switch control module 20 serves as the core module of the power input switching circuit in the bypass mode. After the entire circuit is stable, the switch control module 20 is turned off as long as the buck converter module 10 is turned on, and the switch control module 20 is turned on when the buck converter module 10 is turned off.

[0074] In one embodiment, if Figure 8 and Figure 9 As shown, the second PMOSFET switch unit 13 includes a third MOS transistor Q4, a fourth MOS transistor Q5, a fifth MOS transistor Q7, a second PMOSFET transistor Q6, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, and a twenty-first resistor R21; the source of the third MOS transistor Q4 is connected to the second reference voltage stabilizing unit 25 through the eighteenth resistor R18; the gate of the third MOS transistor Q4 is connected to the drain of the fourth MOS transistor Q5 and also to the source of the third MOS transistor Q4; the drain of the third MOS transistor Q4 is connected to the second DC-DC buck converter unit 12 and also to the tenth resistor R19. A ninth resistor R19 is grounded; a gate of the fourth MOS transistor Q5 is connected to the CPU control unit 29, and a source of the fourth MOS transistor Q5 is grounded; a drain of the second PMOSFET transistor Q6 is connected to the second DC-DC step-down converter unit 12; a source of the second PMOSFET transistor Q6 is connected to the post-stage circuit 40; a gate of the second PMOSFET transistor Q6 is connected to the post-stage circuit 40 via a twentieth resistor R20, and is also connected to the drain of the fifth MOS transistor Q7 via a twenty-first resistor R21; a source of the fifth MOS transistor Q7 is grounded, and a gate of the fifth MOS transistor Q7 is connected to the CPU control unit 29.

[0075] In this embodiment, the specific circuit of the second DC-DC buck converter unit 12 is completely referred to as follows: Figure 2 and Figure 7The drain of the third MOS Q4 is connected to the EN pin of the first DC-DC converter chip U4 in the second DC-DC step-down converter unit 12. Moreover, the third MOS Q4 is a P-type MOS, the fourth MOS Q5 is an N-type MOS, and the fifth MOS Q7 is an N-type MOS.

[0076] The CPU control unit 29 can output five control signals, CPU_CTL1, CPU_CTL2, CPU_CTL3, CPU_CTL4 and CPU_CTL5. Specifically, the CPU_CTL3 control signal output by the CPU control unit 29 is input to the gate of the fourth MOS Q5, and the CPU_CTL4 control signal output by the CPU control unit 29 is input to the gate of the fifth MOS Q7. The CPU_CTL3 control signal output by the CPU control unit 29 can control the on / off of the fourth MOS Q5, and the CPU_CTL4 control signal output by the CPU control unit 29 can control the on / off of the fifth MOS Q7. The remaining three control signals output by the CPU control unit 29 will be described later after the specific circuit structure of the third PMOSFET switch unit 28 is introduced. It can be seen that the second PMOSFET switch unit with the above circuit structure can increase hysteresis control in combination with the control signals output by the CPU control unit and the output voltage of the second DC-DC step-down converter unit, so as to enhance the stability of the entire circuit.

[0077] In an embodiment, as shown in FIG. 6, the first DC-DC step-down converter unit 11 is connected to the second DC-DC step-down converter unit 12 through the third PMOSFET switch unit 28. Figures 8-10As shown, the third PMOSFET switch unit 28 comprises a third PMOSFET Q8, a fourth PMOSFET Q9, a sixth MOS Q10, a seventh MOS Q11, an eighth MOS Q12, a ninth MOS Q13, a fifth diode D5, a sixth diode D6, a fourteenth capacitor C14, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26 and a twenty-seventh resistor R27; the source of the third PMOSFET Q8 is connected with the input power supply 30, and the drain of the third PMOSFET Q8 is connected with the drain of the fourth PMOSFET Q9; the gate of the third PMOSFET Q8 is connected with the input power supply 30 through the parallel connection of the fourteenth capacitor C14 and the twenty-second resistor R22, and is also connected with the first end of the twenty-third resistor R23; the second end of the twenty-third resistor R23 is connected with the drain of the seventh MOS Q11 and the drain of the eighth MOS Q12; the gate of the sixth MOS Q10 is connected with the CPU control unit 29, and is also grounded through the twenty-fourth resistor R24; the source of the sixth MOS Q10 is grounded; the drain of the sixth MOS Q10 is connected with the gate of the seventh MOS Q11; the gate of the seventh MOS Q11 is connected with the second voltage comparator unit 26 through the fifth diode D5, is connected with the second reset unit 27 through the sixth diode D6, and is also connected with the second reference voltage unit 25 through the twenty-fifth resistor R25; the source of the seventh MOS Q11 is grounded; the source of the eighth MOS Q12 is grounded; the gate of the eighth MOS Q12 is connected with the CPU control unit 29; the source of the fourth PMOSFET Q9 is connected with the subsequent circuit 40; the gate of the fourth PMOSFET Q9 is connected with the subsequent circuit 40 through the twenty-sixth resistor R26, and is also connected with the drain of the ninth MOS Q13 through the twenty-seventh resistor R27; the source of the ninth MOS Q13 is grounded; the gate of the ninth MOS Q13 is connected with the CPU control unit 29.

[0078] In the embodiment, as the third PMOSFET switch unit 28 adopted in the second embodiment of the switch control module 20, the sixth MOS Q10, the seventh MOS Q11, the eighth MOS Q12 and the ninth MOS Q13 are all N-type MOS. Moreover, the gate of the seventh MOS Q11 is connected with the second voltage comparator unit 26 through the fifth diode D5 and connected with the second reset unit 27 through the sixth diode D6, specifically, the gate of the seventh MOS Q11 is connected with the positive pole of the fifth diode D5, the negative pole of the fifth diode D5 is connected with the second voltage comparator unit 26, the gate of the seventh MOS Q11 is connected with the positive pole of the sixth diode D6, and the negative pole of the sixth diode D6 is connected with the second reset unit 27. The CPU_CTL1 control signal outputted by the CPU control unit 29 is inputted to the gate of the eighth MOS Q12, the CPU_CTL2 control signal outputted by the CPU control unit 29 is inputted to the gate of the ninth MOS Q13, and the CPU_CTL5 control signal outputted by the CPU control unit 29 is inputted to the gate of the sixth MOS Q10.

[0079] The CPU_CTL1 control signal outputted by the CPU control unit 29 can control the on / off of the eighth MOS Q12, the CPU_CTL2 control signal outputted by the CPU control unit 29 can control the on / off of the ninth MOS Q13, and the CPU_CTL5 control signal outputted by the CPU control unit 29 can control the on / off of the sixth MOS Q10. It can be seen that, by adopting the third PMOSFET switch unit with the above circuit structure, the corresponding hysteresis control can be added in combination with the control signal outputted by the CPU control unit, the output signal of the second reset unit and the output signal of the second voltage comparator unit, so as to enhance the stability of the whole circuit.

[0080] In order to more clearly understand the specific working condition of the power input switching circuit when the input voltage of the input power 30 changes, the following working conditions are specifically combined for description:

[0081] Working condition one) the input voltage linearly decreases from 24V to below 16V

[0082] When the input voltage Vin is 24V, CPU_CLT1 is L, CPU_CTL2 is L, CPU_CTL3 is H, CPU_CTL4 is H, CPU_CTL5 is H, and V_DET is 0V. At this time, the DC-DC path is selected, that is, the path where the second DC-DC step-down converter unit 12 and the second PMOSFET switch unit 13 are located, and Vout=13.6V.

[0083] When the input voltage Vin drops to 16.5V, the control timing is executed in the following steps:

[0084] 11) CPU_CTL4 is set to L, then Vout = 13.6V - 0.6V = 13V;

[0085] 12) CPU_CTL1 is set to H, the third PMOSFET switch unit 28 is turned on; Vout = Vin - 0.6V = 15.9V;

[0086] 13) CPU_CTL3 is set to L, then Vout = Vin - 0.6V = 15.9V;

[0087] 14) CPU_CTL2 is set to H, then Vout = Vin = 16.5V;

[0088] When the input voltage continues to drop below 16V:

[0089] 15) V_DET is 5V, DCDC is off, Vout = Vin = 16V.

[0090] In this condition, the power supply is seamlessly switched from the DC-DC path (i.e. the path where the second DC-DC buck converter unit 12 and the second PMOSFET switch unit 13 are located) to the bypass mode, and the output voltage Vout will not be interrupted.

[0091] Condition two) The input voltage drops from 24V to below 16.5V, and then oscillates, with a range of less than 17V

[0092] When the input voltage Vin drops from 24V to below 16.5V, the control timing refers to steps 11) ~ 14) of condition one, and then the input voltage Vin oscillates below 17V:

[0093] When Vin≥16V, V_DET is 0V, the DC-DC path is turned on and the third PMOSFET switch unit 28 is turned on, Vout = Vin;

[0094] When Vin<16V, V_DET is 5V, the DC-DC path is turned off and the third PMOSFET switch unit 28 is turned on, Vout = Vin;

[0095] At this time, whether the DC-DC path is turned on or not, the entire circuit works in the bypass mode.

[0096] When the input voltage exceeds 17V, then the following condition three is executed.

[0097] Condition three) The input voltage linearly increases from 12V to above 16V

[0098] When input voltage Vin is 12V, CPU_CTL1 is H, CPU_CTL2 is H, CPU_CTL3 is L, CPU_CTL4 is L, CPU_CTL5 is H, V_DET is 5V, the whole circuit works in bypass mode, and Vout = Vin.

[0099] When input voltage Vin rises to 15.5V, the control timing is executed in the following steps:

[0100] 31) CPU_CTL2 is set to L, then Vout = Vin - 0.6V = 14.9V;

[0101] 31) CPU_CTL3 is set to H and DC-DC path, then Vout = Vin - 0.6V = 14.9V;

[0102] 33) CPU_CTL1 is set to L and the third PMOSFET switch unit 28 is off, then Vout = 13.6V - 0.6V = 13V;

[0103] 34) CPU_CTL4 is set to H, then Vout = 13.6V;

[0104] When input voltage continues to rise above 16V:

[0105] 35) V_DET is 0V, then Vout = 13.6V;

[0106] In this working condition three, the input power supply is seamlessly switched from bypass mode to DC-DC path, and the output voltage Vout will not be interrupted.

[0107] Working condition four) voltage linearly increases from 12V to more than 15.5V, and then oscillates, ranging above 15V

[0108] When input voltage Vin increases from 12V to more than 15.5V, the control timing refers to steps 31) ~ 34) of working condition three, and then the input voltage Vin oscillates above 15V:

[0109] When Vin≥16V, the third PMOSFET switch unit 28 is off, the DC-DC path is on, and Vout = 13.6V;

[0110] When Vin<16V, the third PMOSFET switch unit 28 is off, the DC-DC path is on, and Vout = 13.6V;

[0111] It can be seen that at this time, since the CPU_CTL5 is H and the CPU_CTL2 is L, the third PMOSFET switch unit 28 is cut off regardless of the state of the V_DET. The CPU_CTL3 is H, and regardless of the state of the V_DET, the DC-DC path works, and the entire circuit must work in the DC-DC path opening mode. And when the input voltage is lower than 15V, the above-mentioned working condition one is executed.

[0112] The above-mentioned four working conditions have included all possible changes of the input voltage, and in any case, seamless connection of the switching circuit output can be guaranteed.

[0113] Another embodiment of the present application provides a power supply device, which comprises the above-mentioned power input switching circuit and further comprises an input power supply; the input end of the power input switching circuit is connected with the input power supply, and the output end of the power input switching circuit is used for connecting with a power consumption device for power supply. Specifically, the power consumption device in the embodiment can be a vehicle radio, a backpack radio, an aviation radio, a battery charging circuit, etc., which is not limited within the understanding range of the person skilled in the art.

[0114] In summary, the utility model provides power input switching circuit and power supply device, power input switching circuit includes step -down converter module and switch control module, step -down converter module and switch control module parallel connection, step -down converter module's input end is connected with input power supply, and step -down converter module's output end is connected with the back -stage circuit, among them, step -down converter module is used to enable conduction when the input voltage provided by input power supply exceeds the preset voltage threshold, and is closed when the input voltage provided by input power supply does not exceed the preset voltage threshold, switch control module is used to conduct when the input voltage provided by input power supply does not exceed the preset voltage threshold, and is closed when the input voltage provided by input power supply exceeds the preset voltage threshold. The utility model automatically switches the power supply path of step -down converter module or switch control module to the back -stage circuit according to the specific situation of the input voltage provided by the input power supply, the circuit cost is low and the power supply efficiency is improved when the low voltage input.

[0115] The above-mentioned is only the specific implementation of the utility model, but the protection scope of the utility model is not limited to this, any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the utility model, and these modifications or replacements should be covered in the protection scope of the utility model. Therefore, the protection scope of the utility model should be subject to the protection scope of the claims.

Claims

1. A power input switching circuit, characterized in that: The invention comprises a buck converter module and a switch control module; the buck converter module and the switch control module are connected in parallel, the input end of the buck converter module is connected to the input power supply, and the output end of the buck converter module is connected to the subsequent circuit; wherein the buck converter module is configured to enable conduction when the input voltage provided by the input power supply exceeds a preset voltage threshold, and to be shut down when the input voltage provided by the input power supply does not exceed the preset voltage threshold; the switch control module is configured to enable conduction when the input voltage provided by the input power supply does not exceed the preset voltage threshold, and to be shut down when the input voltage provided by the input power supply exceeds the preset voltage threshold.

2. The power input switching circuit according to claim 1, wherein: The buck converter module includes a first DC-DC buck converter unit; an input end of the first DC-DC buck converter unit is connected to the input power supply, and an output end of the first DC-DC buck converter unit is connected to the subsequent circuit.

3. The power input switching circuit according to claim 2, wherein: The switch control module includes a first reference voltage stabilizing unit, a first voltage comparator unit, a first reset unit and a first PMOSFET switch unit; the first reference voltage stabilizing unit is connected to the input power supply; the first voltage comparator unit is connected to the input power supply, the first reference voltage stabilizing unit and the first PMOSFET switch unit; the first reset unit is connected to the first reference voltage stabilizing unit and the first PMOSFET switch unit; and the first PMOSFET switch unit is connected to the subsequent circuit.

4. The power input switching circuit according to claim 3, wherein: The first reference voltage stabilizing unit includes a first reference voltage source chip, a first resistor, a second resistor, a third resistor and a first capacitor; the first end of the first resistor is connected to the input power supply, the second end of the first resistor is connected to the CAT pin of the first reference voltage source chip and the first end of the second resistor, and the second end of the first resistor is also connected to the ground through the first capacitor; the second end of the second resistor is connected to the REF pin of the first reference voltage source chip and is also grounded through the third resistor; the ANO pin of the first reference voltage source chip is grounded.

5. The power input switching circuit according to claim 4, wherein: The first voltage comparator unit includes a first comparator, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second capacitor; the first end of the fourth resistor is connected to the input power supply, the second end of the fourth resistor is connected to the negative input pin of the first comparator, and the second end of the fourth resistor is also grounded through the fifth resistor; the first end of the sixth resistor is connected to the CAT pin of the first reference voltage source chip, the second end of the sixth resistor is connected to the positive input pin of the first comparator, and the second end of the sixth resistor is also grounded through the seventh resistor; the Vcc pin of the first comparator is connected to the CAT pin of the first reference voltage source chip and is also grounded through the second capacitor; the Vss pin of the first comparator is grounded; the Vo pin of the first comparator is connected to the first PMOSFET switch unit and is also connected to the Vcc pin of the first comparator through the eighth resistor.

6. The power input switching circuit according to claim 5, wherein: The first reset unit includes a first reset chip, a ninth resistor, a tenth resistor, a third capacitor, and a fourth capacitor; the VIN pin of the first reset chip is connected to the CAT pin of the first reference voltage source chip; the VSEN pin of the first reset chip is connected to the CAT pin of the first reference voltage source chip through the ninth resistor, and is also grounded through the third capacitor; the CD pin of the first reset chip is grounded through the fourth capacitor; the VOUT pin of the first reset chip is connected to the CAT pin of the first reference voltage source chip through the tenth resistor, and is also connected to the first PMOSFET switch unit; the VSS pin of the first reset chip is grounded.

7. The power input switching circuit according to claim 6, wherein: The first PMOSFET switch unit includes a first PMOSFET tube, a first MOS tube, a first diode, a second diode, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fifth capacitor; the cathode of the first diode is connected to the VOUT pin of the first reset chip; the anode of the first diode is connected to the CAT pin of the first reference voltage source chip through the eleventh resistor, and is also connected to the gate of the first MOS tube; the cathode of the second diode is connected to the Vo pin of the first comparator, and the anode of the second diode is connected to the gate of the first MOS tube; the source of the first MOS tube is grounded, and the drain of the first MOS tube is connected to the first end of the twelfth resistor; the second end of the twelfth resistor is connected to the gate of the first PMOSFET tube, and is connected to the input power supply through the thirteenth resistor, and is also connected to the input power supply through the fifth capacitor; the source of the first PMOSFET tube is connected to the input power supply, and the drain of the first PMOSFET tube is connected to the post-stage circuit.

8. The power input switching circuit according to claim 7, wherein: The first DC-DC step-down converter unit includes a first DC-DC converter chip, a second MOS transistor, a third diode, a fourteenth resistor, a fifteenth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first ferrite bead, a ninth capacitor, a fourth diode, a tenth capacitor, a first inductor, a sixteenth resistor, a seventeenth resistor, an eleventh capacitor, a twelfth capacitor, and a thirteenth capacitor; the EN pin of the first DC-DC converter chip is connected to the VOUT pin of the first reset chip through the third diode, and is grounded through the sixth capacitor, and is also connected to the drain of the second MOS transistor; the source of the second MOS transistor is connected to the CAT pin of the first reference voltage source chip through the fourteenth resistor, and the gate of the second MOS transistor is connected to the Vo pin of the first comparator through the fifteenth resistor; the first DC-DC converter chip Both the GND pin and the PowerPAD pin are grounded; the VIN pin of the first DC-DC converter chip is grounded through the seventh capacitor and the eighth capacitor in parallel, and is also connected to the input power supply through the first ferrite bead; the PH pin of the first DC-DC converter chip is connected to the BOOT pin of the first DC-DC converter chip through the ninth capacitor, and is grounded through the fourth diode and the tenth capacitor in parallel, and is also connected to the first end of the first inductor; the second end of the first inductor is connected to the VSENSE pin of the first DC-DC converter chip through the sixteenth resistor and the eleventh capacitor in parallel, and is grounded through the twelfth capacitor and the thirteenth capacitor in parallel, and is also connected to the subsequent circuit; the VSENSE pin of the first DC-DC converter chip is also grounded through the seventeenth resistor.

9. The power input switching circuit according to claim 1, wherein: The buck converter module includes a second DC-DC buck converter unit and a second PMOSFET switch unit; the input end of the second DC-DC buck converter unit is connected to the input power supply, and the output end of the second DC-DC buck converter unit is connected to the subsequent circuit through the second PMOSFET switch unit.

10. The power input switching circuit according to claim 9, wherein: The switch control module includes a second reference voltage stabilizing unit, a second voltage comparator unit, a second reset unit, a third PMOSFET switch unit and a CPU control unit; the second reference voltage stabilizing unit is connected to the input power supply; the second voltage comparator unit is connected to the input power supply, the second reference voltage stabilizing unit and the third PMOSFET switch unit; the second reset unit is connected to the second reference voltage stabilizing unit and the third PMOSFET switch unit; the third PMOSFET switch unit is connected to the CPU control unit and the subsequent circuit; the CPU control unit is connected to both the second DC-DC buck converter unit and the input power supply.

11. The power input switching circuit according to claim 10, wherein: The second PMOSFET switch unit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a second PMOSFET transistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, and a twenty-first resistor; the source of the third MOS transistor is connected to the second reference voltage stabilizing unit through the eighteenth resistor; the gate of the third MOS transistor is connected to the drain of the fourth MOS transistor and is also connected to the source of the third MOS transistor; the drain of the third MOS transistor is connected to the second DC-DC buck converter unit and is also grounded through the nineteenth resistor; the gate of the fourth MOS transistor is connected to the CPU control unit, and the source of the fourth MOS transistor is grounded; the drain of the second PMOSFET transistor is connected to the second DC-DC buck converter unit; the source of the second PMOSFET transistor is connected to the subsequent circuit; the gate of the second PMOSFET transistor is connected to the subsequent circuit through the twenty-first resistor and is also connected to the drain of the fifth MOS transistor through the twenty-first resistor; the source of the fifth MOS transistor is grounded, and the gate of the fifth MOS transistor is connected to the CPU control unit.

12. The power input switching circuit according to claim 11, wherein: The third PMOSFET switch unit includes a third PMOSFET tube, a fourth PMOSFET tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a fifth diode, a sixth diode, a fourteenth capacitor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, and a twenty-seventh resistor; the source of the third PMOSFET tube is connected to the input power supply, and the drain of the third PMOSFET tube is connected to the drain of the fourth PMOSFET tube; the gate of the third PMOSFET tube is connected to the input power supply through the fourteenth capacitor and the twenty-second resistor connected in parallel, and is also connected to the first end of the twenty-third resistor; the second end of the twenty-third resistor is connected to the drain of the seventh MOS tube and the drain of the eighth MOS tube; the gate of the sixth MOS tube is connected to the CPU control unit , and is also grounded through the twenty-fourth resistor; the source of the sixth MOS tube is grounded; the drain of the sixth MOS tube is connected to the gate of the seventh MOS tube; the gate of the seventh MOS tube is connected to the second voltage comparator unit through the fifth diode, and is connected to the second reset unit through the sixth diode, and is also connected to the second reference voltage stabilization unit through the twenty-fifth resistor; the source of the seventh MOS tube is grounded; the source of the eighth MOS tube is grounded; the gate of the eighth MOS tube is connected to the CPU control unit; the source of the fourth PMOSFET tube is connected to the subsequent circuit; the gate of the fourth PMOSFET tube is connected to the subsequent circuit through the twenty-sixth resistor, and is also connected to the drain of the ninth MOS tube through the twenty-seventh resistor; the source of the ninth MOS tube is grounded; and the gate of the ninth MOS tube is connected to the CPU control unit.

13. A power supply device, characterized in that: It comprises at least one power input switching circuit and an input power supply according to any one of claims 1 to 12, wherein the input end of the power input switching circuit is connected to the input power supply, and the output end of the power input switching circuit is used to connect to an electrical device for power supply.

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