High-precision integrated temperature sensor circuit and temperature sensor

Abstract

A high-precision integrated temperature sensor circuit and a temperature sensor relate to the technical field of integrated circuits, and comprise a band-gap reference circuit, a buffer circuit, an analog-to-digital conversion circuit, a two-phase non-overlapping clock generation circuit and an FIR digital filter. It needs to be explained that a key circuit sigma-delta modulator adopts an integrator cascade feed-forward structure CIFF, compared with a CIFB with a feedback structure, an STF function of an ADC of a feed-forward structure is close to 1, a peak value can appear only at a high frequency, only a very small error signal can pass through a whole loop, and therefore the stability of the analog-to-digital converter is greatly improved. Therefore, the gain of the amplifier in the first-stage integrator can be made relatively large, and noise and nonlinearity generated by the rear-stage integrator are effectively suppressed. Moreover, each stage of integrator does not process a feedback signal with high-frequency noise, so that the bandwidth requirement on the next stage of operational amplifier is reduced, the power consumption required by the CIFF structure is lower, and meanwhile, the output swing has better stability due to no feedback structure.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of integrated circuit, especially, a kind of high-precision integrated temperature sensor circuit and temperature sensor. BACKGROUND

[0002] Temperature measurement plays a vital role in many fields, including industrial control, medical equipment, environmental monitoring and automotive electronics, etc. Traditional temperature measurement methods often rely on discrete components, such as thermocouples, thermal resistors, etc. Although these methods can achieve temperature measurement, they have many limitations. Among them, the temperature sensor of discrete component usually has a large volume, which is not conducive to the development trend of integration and miniaturization, and its precision and stability may be affected by various factors, such as environmental interference, installation error, etc., resulting in inaccurate and unstable measurement results.

[0003] It should be noted that with the rapid development of semiconductor technology and integrated circuit process, high-precision integrated temperature sensor emerges as the times require. This sensor integrates temperature sensing elements and signal processing circuits on a chip, with the advantages of small size, low power consumption, fast response speed, high precision, etc.

[0004] It should be further noted that the design focus of integrated temperature sensor is how to accurately convert the measured environmental temperature into a circuit signal. In circuit design, devices that can sense temperature usually include thermistors, metals, etc. The temperature sensor composed of thermistors has achieved high precision after years of development. However, traditional thermistors have many serious defects: poor compatibility with CMOS integrated process; serious non-linearity of resistance and temperature; poor sensitivity and high power consumption in low temperature measurement; temperature measurement range is limited to measuring temperature above zero, etc. This not only does not meet the requirements of high precision, but also poses a huge challenge to the matching of the back-end temperature readout circuit and the front-end analog temperature sensing circuit designed by CMOS process. UTILITY MODEL CONTENT

[0005] The utility model aims to provide a kind of high-precision integrated temperature sensor circuit and temperature sensor to solve the problems raised in the above background technology.

[0006] To achieve the above purpose, the utility model provides the following technical scheme:

[0007] A kind of high-precision integrated temperature sensor circuit, it includes band gap reference circuit, the buffer circuit connected with the band gap reference circuit, the analog-digital conversion circuit connected with the buffer circuit of the buffer, the two-phase non-overlapping clock generation circuit connected with the analog-digital conversion circuit, the FIR digital filter connected with the analog-digital conversion circuit.

[0008] Furthermore, in a preferred embodiment of the present invention, the bandgap reference circuit includes a startup circuit, a bandgap circuit and a bias circuit, and the startup circuit and the bias circuit are both connected to the bandgap circuit, wherein the startup circuit is connected to the bandgap circuit for starting the bandgap circuit, and the bias circuit is connected to the bandgap circuit for providing a bias for the bandgap circuit.

[0009] Furthermore, in a preferred embodiment of the present invention, the bandgap reference circuit includes a first operational amplifier and two parallel parasitic bipolar PNP transistors, and the two parallel parasitic bipolar PNP transistors are respectively connected to two corresponding input terminals of the first operational amplifier.

[0010] Furthermore, in a preferred embodiment of the present invention, the structure of the first operational amplifier is a folded cascode differential operational amplifier; and the parasitic bipolar PNP transistor is a temperature sensing device.

[0011] Furthermore, in a preferred embodiment of the present invention, the buffer circuit includes a second operational amplifier, C4, M0, R0, and R1, wherein the gate of M0 is connected to the output terminal of the second operational amplifier, C4 is connected across the gate and drain of M0, R0 and R1 are connected in series and then connected to the drain of M0, the positive input terminal of the second operational amplifier is connected between R0 and R1, and a resistance trimming module is connected between R0 and C4;

[0012] The bandgap reference circuit generates a reference voltage V REF Input to the second op amp is V IN An input terminal of the second operational amplifier is connected to the gate of the M0.

[0013] Furthermore, in a preferred embodiment of the present invention, the analog-to-digital conversion circuit is a second-order CIFF Σ-Δ modulator structure, and its effective number of bits is 16 bits;

[0014] The Σ-Δ modulator is composed of an adder, an integrator, a one-bit quantizer, a latch circuit and a clock circuit. The integrator, the adder, the one-bit quantizer and the latch circuit are connected in sequence. The clock circuit is the two-phase non-overlapping clock generation circuit. The adder, the integrator and the one-bit quantizer are all connected to the clock circuit, and the clock circuit provides corresponding clock signals to the adder, the integrator and the one-bit quantizer respectively.

[0015] Further, in the preferred embodiment of the utility model, the adder is a switched capacitor adder, which comprises six first capacitors and a plurality of first analog switches, the six first capacitors are connected in parallel to form six branches of the adder, and each first capacitor is connected with two first analog switches at both ends.

[0016] Further, in the preferred embodiment of the utility model, the integrator is a switched capacitor integrator, which comprises a plurality of second analog switches, four second capacitors and a folded cascode operational amplifier, the four second capacitors are C0, C1, C2 and C3, wherein C0 and C1 are integration capacitors, and C2 and C3 are sampling capacitors.

[0017] C0 and C1 are connected across the input and output terminals of the folded cascode operational amplifier in the integrator, respectively, and C2 and C3 are connected with two second analog switches at both ends, respectively, and then connected to the two input terminals of the folded cascode operational amplifier.

[0018] Further, in the preferred embodiment of the utility model, the clock signals output by the two-phase non-overlapping clock generation circuit include PH1, PH2, PH1d and PH2d, wherein PH1 and PH2 are opposite in phase, and PH1d and PH2d are delay clock signals of PH1 and PH2, respectively.

[0019] The frequency of the four clock signals is 200KHz, and the output end of the two-phase non-overlapping clock generation circuit is connected with the buffer circuit to output the corresponding clock signals.

[0020] The utility model also provides a temperature sensor, the temperature sensor has above-mentioned high accuracy integrated temperature sensor circuit.

[0021] The utility model discloses a high-precision integrated temperature sensor circuit and temperature sensor have the beneficial effects of:

[0022] In the design process of the ADC circuit in the utility model, first, the Matlab Simulink function is used to model the modulator at the system level, and then the design is applied to actual process simulation. This design step can shorten the simulation time. First, determine the order, bit number and the like required by the ADC according to the modeling test, so as to determine the architecture of the modulator. Then, transplant the design into the integrated circuit level simulation of Cadence, thereby increasing the design efficiency.

[0023] Further, the key circuit sigma-delta modulator in the utility model adopts integrator cascade feedforward structure CIFF, compared with CIFB with feedback structure, the signal transfer function (namely STF function) of the ADC of feedforward architecture is close to 1, only a peak value can appear at high frequency, only a little error signal can pass through the whole loop.

[0024] Further, the design of the operational amplifier in the bandgap reference source is very important, and the offset of the operational amplifier is a main error source of the reference source. Due to the asymmetry, the operational amplifier can be affected by the input offset. In the utility model, the first operational amplifier in the bandgap reference circuit is optimized to realize a high common-mode rejection ratio PSRR and a low offset, thereby reducing the sensitivity of the temperature detection result to the process. Specifically, for the problem of operational amplifier offset, high-order curvature compensation is used to realize the optimization of the operational amplifier offset. Since the bandgap reference circuit in the utility model is a current mode structure, the current generated by the voltage difference of the two parasitic bipolar PNP transistors B-E junction can be directly used for high-order compensation. In addition, for the problem of improving the common-mode rejection ratio, the chopping technology is used. The chopping technology compares the common-mode interference in the input signal and the common-mode interference in the output signal, and then uses the characteristics of the internal circuit to reduce the common-mode interference to a very low level, so that the common-mode interference in the output signal is greatly reduced, thereby improving the quality and stability of the signal.

[0025] Further, the output voltage of the feedback resistance sampling bandgap circuit is transmitted to the non-inverting input terminal of the second operational amplifier, so that the output voltage of the second operational amplifier changes, and the gate voltage of the M0 transistor is adjusted. In addition, due to process deviation, some resistors will be mismatched, the resistance will deviate from the preset value, and the accuracy of the buffer output voltage will be affected. In view of the above problems, when the feedback resistors R0 and R1 in the buffer circuit are designed, the trimming circuit composed of multiple resistors and transistors is added, the equivalent resistance of the resistor string is adjusted by controlling the conduction and cutoff of the corresponding MOS switch through the control signal, thereby reducing the error caused by the mismatch of the feedback resistors. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 The high-precision integrated temperature sensor circuit schematic diagram provided by the utility model embodiment;

[0027] Figure 2The band gap reference circuit circuit diagram in the high-precision integrated temperature sensor circuit is provided for the embodiment of the utility model.

[0028] Figure 3 The buffer circuit diagram is provided in the embodiment of the utility model.

[0029] Figure 4 The operational amplifier circuit in the buffer circuit is provided in the embodiment of the utility model.

[0030] Figure 5 The overall structure schematic diagram of the sigma-delta modulator circuit is provided in the embodiment of the utility model.

[0031] Figure 6 The sigma-delta modulator structure schematic diagram of the second-order input feedforward structure is provided in the embodiment of the utility model.

[0032] Figure 7 The circuit diagram of the operational amplifier in the feedforward type sigma-delta modulator is provided in the embodiment of the utility model.

[0033] Figure 8 The integrator circuit diagram in the feedforward type sigma-delta modulator is provided in the embodiment of the utility model.

[0034] Figure 9 The adder circuit diagram in the feedforward type sigma-delta modulator is provided in the embodiment of the utility model.

[0035] Figure 10 The quantizer circuit diagram in the feedforward type sigma-delta modulator is provided in the embodiment of the utility model.

[0036] Figure 11 The latch circuit diagram in the feedforward type sigma-delta modulator is provided in the embodiment of the utility model.

[0037] Figure 12 The two-phase non-overlapping clock circuit diagram is provided in the embodiment of the utility model.

[0038] Figure 13 The overall circuit diagram of the temperature sensor is provided in the embodiment of the utility model. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model.

[0040] Please refer to Figure 1 and Figure 13The utility model embodiment provides a kind of high-precision integrated temperature sensor circuit, it includes band gap reference circuit, the buffer circuit being connected with the band gap reference circuit, the analog-to-digital conversion (Analog-to-Digital Converter, ADC) circuit being connected with the buffer circuit of buffer, the two-phase non-overlapping clock generation circuit being connected with the analog-to-digital conversion circuit, the FIR digital filter being connected with the analog-to-digital conversion circuit.It needs to be explained, FIR digital filter, i.e.

[0041] Further, please refer to Figure 2 In the utility model embodiment, the band gap reference circuit includes a start-up circuit, a band gap circuit, and a bias circuit. The start-up circuit and the bias circuit are both connected to the band gap circuit. The start-up circuit is connected to the band gap circuit to start the band gap circuit, i.e., to enable the band gap circuit to start normally. The bias circuit is connected to the band gap circuit to provide appropriate bias for the band gap circuit.

[0042] In addition, the band gap reference circuit includes a first operational amplifier and two parallel parasitic bipolar PNP transistors. The two parallel parasitic bipolar PNP transistors are respectively connected to two input terminals of the first operational amplifier. The first operational amplifier has a folded common-source common-gate differential operational amplifier structure. The parasitic bipolar PNP transistors are temperature sensing devices.

[0043] Further, please refer to Figure 1 、 Figure 2 、 Figure 3 And Figure 4 In the utility model embodiment, the buffer circuit includes a second operational amplifier, a C4, an M0, an R0, and an R1. The gate of the M0 is connected to the output terminal of the second operational amplifier. The C4 is connected across the gate and the drain of the M0. The R0 and the R1 are connected in series and then connected to the drain of the M0. The positive input terminal of the second operational amplifier is connected between the R0 and the R1. A resistance trimming module is connected between the R0 and the C4. It needs to be explained that the C4 is a capacitor, the M0 is a PMOS transistor, the R0 and the R1 are fixed resistors. In addition, it needs to be explained that the reference voltage VREF V IN input to the second operational amplifier on1 input end, and the second operational amplifier output end is connected with the M0 gate.

[0044] Further, please refer to Figures 5-11 In the embodiment of the utility model, the analog-digital conversion circuit is the sigma-delta modulator structure of two order CIFF structure, and the effective number of bits is 16, specifically, the sigma-delta modulator is composed of adder, integrator, one-bit quantizer, latch circuit and clock circuit, the integrator, the adder, the one-bit quantizer, the latch circuit are connected in proper order, the clock circuit is the two-phase non-overlapping clock generation circuit, the adder, the integrator and the one-bit quantizer are all connected to the clock circuit, and the clock circuit provides corresponding clock signal to the adder, the integrator and the one-bit quantizer respectively, it needs to be explained that the quantizer adopts one-bit quantizer, and the quantizer compares the input analog signal with a fixed reference level, and the reference level determines the threshold of quantization, and the result of comparison will produce a 1bit digital signal;

[0045] In addition, it also needs to be explained that the latch corresponding to the latch circuit adopts the SR latch composed of NAND gate, V on1 , V op1 is the latch input, V op , V on is the latch output, and specifically, the latch is realized by two cross-coupled NAND gates (NAND1 and NAND2): the output end of NAND1 is connected with one input end of NAND2, and the output end of NAND2 is connected with one input end of NAND1, and NAND1 and NAND2 still have respectively remaining 1 input end, and are connected with two output ends V on1 and V op1 of one-bit quantizer respectively.

[0046] Further specifically, in the embodiment of the utility model, the adder is the switched-capacitor adder, which includes six first capacitors and a plurality of first analog switches, six first capacitors are connected in parallel to form six branches of the adder, and two first analog switches are connected to each first capacitor respectively. It needs to be explained that these first capacitors perform charge-discharge operation under the control of first analog switches, thereby performing mathematical operation.

[0047] Further specifically, in the embodiment of the utility model, the integrator is the switched-capacitor integrator, which includes a plurality of second analog switches, four second capacitors and a folded common-source common-gate operational amplifier, four second capacitors are C0, C1, C2 and C3 respectively, wherein C0 and C1 are integration capacitors, and C2 and C3 are sampling capacitors.

[0048] Further, the C0 and the C1 are connected across the input and output of the folded cascode operational amplifier in the integrator, and the C2 and the C3 are connected across two second analog switches respectively, and then connected to two inputs of the folded cascode operational amplifier respectively.

[0049] Further, please refer to Figure 12 In the embodiment of the utility model, the clock signal that two phase non overlapping clock generating circuit outputs includes PH1, PH2, PH1d and PH2d, wherein the PH1 and the PH2 are opposite in phase, the PH1d and the PH2d are the delay clock signal of the PH1 and the PH2 respectively, it is explained that, the frequency of 4 the clock signal is 200KHz signal, the two phase non overlapping clock generating circuit output end connects the buffer circuit, and the corresponding clock signal is outputted.

[0050] The utility model embodiment further provides a temperature sensor, the temperature sensor has the high accuracy integrated temperature sensor circuit of above, its specific general circuit diagram as Figure 13 Shown.

[0051] Further, for the purpose, technical scheme and advantages of the embodiments of the present application, the technical scheme in the embodiments of the present application will be more clearly and completely described below. The specific conditions are not marked in the embodiments, and are carried out according to conventional conditions or manufacturer's recommended conditions. Unless otherwise defined, all technical and scientific terms used in this paper are the same as the meanings understood by the persons skilled in the art. The terms used in the specification are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The term "and / or" used in this paper includes any and all combinations of one or more related listed items.

[0052] Please refer to Figures 1-13 The high-precision integrated temperature sensor circuit includes a bandgap reference circuit, a buffer circuit connected to the bandgap reference circuit, an analog-to-digital conversion (ADC) circuit connected to the buffer circuit, a two-phase non-overlapping clock generation circuit connected to the analog-to-digital conversion (ADC) circuit, and a FIR digital filter connected to the analog-to-digital conversion (ADC) circuit. Wherein, the bandgap reference circuit provides two voltages: a voltage V PTAT that is proportional to temperature and a reference voltage VREF The bandgap reference circuit is divided into three parts, i.e. a bandgap circuit, a start-up circuit and a bias circuit, as shown in FIG. 2. Figure 2 It is to be noted that the parasitic transistors in the bandgap reference circuit convert the temperature signal from the outside into a corresponding voltage signal, and the ratio of the emitting junction areas of the two parasitic transistors Q0 and Q1 in the circuit is 8:1 in consideration of the layout factor. The structure of the operational amplifier in the circuit is a folded common-source common-gate differential operational amplifier, which provides two feedback loops, i.e. positive feedback and negative feedback, for the circuit. The input of the amplifier is virtually shorted, so that the potentials at the two differential input terminals are the same, and the difference between V BE The difference ΔV BE is reflected on the voltage difference between the resistors R1, and a current I PTAT with a positive temperature coefficient is generated.

[0053] The expression of I PTAT is as follows:

[0054]

[0055] According to formula (1), I PTAT is copied to the voltage generation circuit through a current mirror, and V PTAT and V REF are generated.

[0056] The expression of V PTAT is as follows:

[0057] V PTAT = I PTAT R2 (2)

[0058] The expression of V REF is as follows:

[0059]

[0060] In formula (3), N=8, which is determined by the ratio of the emitting junction areas of the transistors Q1 and Q2, i.e. 8:1. Since V BE is a negative temperature coefficient voltage, and ΔV BE is a positive temperature coefficient voltage, the value of V REF can be kept constant by adjusting the values of the resistors R1 and R2, i.e. However, V PTAT has a good positive temperature characteristic, and can be used as the temperature sensing voltage after being enhanced by the buffer circuit to have a good load capacity.

[0061] The V PTAT and V REF generated by the bandgap reference circuit cannot effectively drive the subsequent modulator circuit, and the reference voltage V REFThe band gap reference circuit is easy to be affected by the post-stage circuit, therefore, the utility model uses two buffers to process the output voltage of the band gap reference circuit Figure 3 .

[0062] The resistance trimming module in the buffer is analyzed as follows:

[0063] According to the virtual short and virtual open principle of the second operational amplifier, the voltage at node 3 is:

[0064] V FB = V REF

[0065] The ratio of the feedback resistors R0 and R1 is:

[0066]

[0067] The M0 current Thus the resistance values of R0 and R1 are determined. On the feedback resistor network, a trimming circuit composed of resistors R13-R16 and transistors M32-M35 is added. After the trimming circuit is added, the output voltage expression of the buffer is:

[0068]

[0069] In the formula, A0-A3 are variables affected by control signals TRIM0-TRIM3. When the control signals are high level, M32-M35 are turned on, at this time, A0-A3 are 0; when the control signals are low level, M32-M35 are turned off, at this time, A0-A3 are 1, thus the trimming of the feedback resistors R0 and R1 is realized.

[0070] The Σ-Δ modulator structure of the second-order input feedforward structure is shown in Figure 6 , and the response of each node is listed by the following formula:

[0071]

[0072]

[0073] Y2=-(1+Z -1 )Z -1 E (6)

[0074] Y3=-Z -2 E (7)

[0075] Y4=U+(-2Z -1 +Z -2 )E (8)

[0076] E in the above equations is the quantization noise of the circuit. From equations (4) to (8), it can be seen that the loop only needs to deal with the quantization noise, i.e. the nodes Y1, Y2, Y3 are only functions of the quantization noise, and Y2, Y3 are the outputs of integrator 1 and integrator 2, so the swing of the integrator output is only affected by the quantization noise, not by the input signal, and the swing is reduced. At the same time, the higher the quantizer precision, the smaller the quantization noise, and the smaller the swing of the integrator, and the better the linearity of the modulator. Therefore, the feedforward structure has a good effect on reducing quantization noise, improving signal-to-noise ratio (SNR) and improving linearity. The second-order modulator provides a good noise shaping effect through its loop filter, pushing the quantization noise to a higher frequency, thereby improving the signal-to-noise ratio and dynamic range at low frequencies. In addition, adding a low-pass filter later will greatly reduce the quantization noise, and the reduction of the quantization noise will lead to the reduction of the swing of the integrator, thereby improving the linearity of the entire modulator, so it is necessary to add a feedforward structure to the Σ-Δ modulator.

[0077] The integrator circuit in the feedforward Σ-Δ modulator needs to have an operational amplifier structure, and the circuit diagram is as follows Figure 7 The operational amplifier used here has the same structure as the operational amplifier in the bandgap reference circuit, except that the MOS parameters are different. In addition, the parameters of the amplifiers in the first-stage integrator and the second-stage integrator are also different. Because for the first-stage integrator, the effect of reducing noise needs to be considered, and this is usually achieved by increasing the size of the MOS. In the second-stage integrator, because of the effect of noise shaping, the effect of noise can be ignored.

[0078] Further, the switch capacitor integrator circuit diagram in the feedforward Σ-Δ modulator is as follows Figure 8The basic working principle is to convert the analog signal into digital form through the periodic action of the switch, and then process the signal by integration. In the fully differential configuration, the circuit has two identical branches that process the positive and negative parts of the input signal, effectively suppressing even-order harmonics and common-mode noise. In the fully differential switched-capacitor integrator, it usually contains a sampling capacitor, an integration capacitor and an operational amplifier. The operational amplifier is used to maintain the voltage stability of the integrator and provide the required gain. The switched-capacitor integrator periodically changes the connection mode of the capacitor through the control of the switch, realizing the sampling and integration of the input signal. Specifically, the operation of the fully differential switched-capacitor integrator can be summarized as follows: in the sampling stage, the switch is closed, and the input signal is sampled through the sampling capacitor, converting the analog signal into a discrete-time signal; in the charge transfer stage, the switch is opened, and the charge on the sampling capacitor is transferred to the integration capacitor, realizing the integration of the signal; in the feedback stage, the operational amplifier provides feedback to ensure that the output voltage of the integrator remains stable while providing the required gain. In the fully differential configuration, since there are two branches, errors caused by device mismatch, temperature changes and other factors can be effectively offset, thereby improving the overall performance and accuracy of the circuit.

[0079] Further, the switched-capacitor adder circuit diagram in the feedforward Σ-Δ modulator is as follows Figure 9 The adder uses a combination of capacitors and switches to perform mathematical operations such as addition and subtraction without using resistors. Because resistors are not needed, the switched-capacitor adder can avoid the temperature drift and noise problems caused by resistors, while also reducing chip area and improving integration. The specific working process is as follows: it is composed of a series of capacitors and switches that perform charging and discharging operations under the control of the switch. At the beginning of each sampling period, the input signal is sampled and stored in the capacitor. The switches of the switched-capacitor adder operate according to a specific timing sequence. The opening and closing of the switch causes the charge to transfer between the capacitors. If the input signal is higher than the reference voltage, the switch will transfer the charge from the input capacitor to the output capacitor; if the input signal is lower than the reference voltage, the charge will be transferred from the output capacitor to the input capacitor.

[0080] Further, the quantizer circuit diagram in the feedforward Σ-Δ modulator is as follows Figure 10The quantizer is one of the core parts of the whole modulator, and it is responsible for converting analog signals into digital signals. The utility model adopts a one-bit quantizer to design the sigma-delta modulator. The working process is as follows: the analog signal is first sent to the quantizer. The quantizer compares the input analog signal with a fixed reference level. The reference level determines the threshold of quantization. The result of comparison will produce a 1bit digital signal. If the analog signal is higher than the reference level, the quantizer outputs a logic '1'; if the analog signal is lower than the reference level, the quantizer outputs a logic '0'.

[0081] Further, the working process of the latch in the feedforward sigma-delta modulator is as follows: at the beginning of each sampling period, the latch is activated by a switch (usually controlled by a clock signal) to allow the signal output from the quantizer to pass through and be stored on the capacitor of the latch. Once the signal is sampled and stored, the switch is closed, and the latch output remains unchanged even if the input signal changes. In this way, the signal output by the latch represents the input value at the sampling time. The latch circuit diagram adopted by the utility model is as follows: Figure 11 That is, the SR latch composed of NAND gates. The function of the latch circuit is mainly to keep the output value of the sigma-delta modulator, and in the figure, V OP and V ON are the output ports of the latch, which are also the output ports of the sigma-delta modulator designed in this design, and output the quantized digital square wave.

[0082] In addition, the two-phase non-overlapping clock circuit designed by the utility model is as follows: Figure 12 Wherein, PH1 and PH2 are opposite in phase, PH1d and PH2d are delay clock signals of PH1 and PH2 respectively, and PH is a signal with a frequency of 200KHz. In addition, a buffer circuit is added at the output end of the clock circuit, which can provide stronger driving capability and drive more loads, so as to ensure that the clock signal can be stably transmitted to each part of the circuit, and the buffer circuit can also isolate the clock signal source and the load, reduce the influence of load change on the quality of the clock signal, and maintain the stability and integrity of the clock signal.

[0083] Finally, it should be pointed out that the FIR digital filter designed by the utility model is designed and realized by Matlab, and a binary number is obtained by passing the quantized output of the sigma-delta modulator through the FIR digital filter. Through induction, the corresponding relationship expression between temperature and the digital code output by the FIR digital filter can be obtained, so as to obtain the specific output temperature.

[0084] To sum up, in the design process of the ADC circuit, firstly, the Matlab Simulink function is used to model the modulator at the system level, and then the design is applied to actual process simulation, so that the simulation time can be shortened, the order and the number of bits required by the ADC are determined according to the modeling test, so as to determine the architecture of the modulator, and then the design is transplanted to the integrated circuit level simulation of Cadence, so that the design efficiency is increased. In addition, the key circuit sigma-delta modulator in the application adopts the integrator cascade feedforward structure CIFF, compared with the CIFB with feedback structure, the STF function of the ADC with the feedforward architecture is close to 1, only a peak value appears at high frequency, only a small error signal can pass through the entire loop, so the amplifier gain in the first stage integrator can be relatively large, which can effectively suppress the noise and nonlinearity generated by the subsequent integrator. At the same time, each integrator does not process the feedback signal with high frequency noise, so the bandwidth requirement of the subsequent operational amplifier is reduced, and the power consumption required by the CIFF structure is low, and the output swing has better stability due to the absence of feedback structure.

[0085] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A high-precision integrated temperature sensor circuit, characterized by comprising: It includes a bandgap reference circuit, a buffer circuit connected with the bandgap reference circuit, an analog-digital conversion circuit connected with the buffer circuit of the buffer, a two-phase non-overlapping clock generation circuit connected with the analog-digital conversion circuit, and a FIR digital filter connected with the analog-digital conversion circuit.

2. The high precision integrated temperature sensor circuit of claim 1, wherein: The bandgap reference circuit includes a starting circuit, a bandgap circuit and a bias circuit, and the starting circuit and the bias circuit are connected to the bandgap circuit, wherein the starting circuit is connected with the bandgap circuit for starting the bandgap circuit, and the bias circuit is connected with the bandgap circuit for providing bias for the bandgap circuit.

3. The high precision integrated temperature sensor circuit of claim 2, wherein: The bandgap reference circuit includes a first operational amplifier and two parallel parasitic bipolar PNP transistors, and the two parallel parasitic bipolar PNP transistors are respectively connected to two input terminals of the first operational amplifier.

4. The high precision integrated temperature sensor circuit of claim 3, wherein: The structure of the first operational amplifier is a folded common-source common-gate differential operational amplifier, and the parasitic bipolar PNP transistor is a temperature sensing device.

5. The high precision integrated temperature sensor circuit of claim 1, wherein: The buffer circuit includes a second operational amplifier, C4, M0, R0 and R1, wherein the gate of M0 is connected to the output terminal of the second operational amplifier, C4 is connected across the gate and the drain of M0, R0 and R1 are connected in series and connected to the drain of M0, the positive input terminal of the second operational amplifier is connected between R0 and R1, and there is a resistance trimming module between R0 and C4. The bandgap reference circuit generates a reference voltage V REF Input to the second op amp is V IN An input terminal of the second operational amplifier is connected to the gate of the M0.

6. The high precision integrated temperature sensor circuit of claim 1, wherein: The analog-digital conversion circuit is a Σ-Δ modulator structure with a second-order CIFF structure, and the effective bit number is 16. The Σ-Δ modulator is composed of an adder, an integrator, a one-bit quantizer, a latch circuit and a clock circuit, the integrator, the adder, the one-bit quantizer and the latch circuit are connected in sequence, the clock circuit is the two-phase non-overlapping clock generation circuit, the adder, the integrator and the one-bit quantizer are connected to the clock circuit, and the clock circuit provides corresponding clock signals to the adder, the integrator and the one-bit quantizer.

7. The high precision integrated temperature sensor circuit of claim 6, wherein: The adder is a switched capacitor adder, which includes six first capacitors and a plurality of first analog switches, and the six first capacitors are connected in parallel to form six branches of the adder, and two first analog switches are connected to each first capacitor.

8. The high precision integrated temperature sensor circuit of claim 7, wherein: The integrator is a switched capacitor integrator, which includes a plurality of second analog switches, four second capacitors and a folded common-source common-gate operational amplifier, and the four second capacitors are C0, C1, C2 and C3, wherein C0 and C1 are integration capacitors, and C2 and C3 are sampling capacitors. C0 and C1 are connected across the input and output terminals of the folded common-source common-gate operational amplifier in the integrator, and C2 and C3 are connected to two second analog switches respectively, and then connected to two input terminals of the folded common-source common-gate operational amplifier.

9. The high precision integrated temperature sensor circuit of claim 1, wherein: The clock signals outputted by the two-phase non-overlapping clock generation circuit include PH1, PH2, PH1d and PH2d, wherein the PH1 and the PH2 are opposite in phase, and the PH1d and the PH2d are delay clock signals of the PH1 and the PH2 respectively; Four clock signals with a frequency of 200KHz are outputted by the two-phase non-overlapping clock generation circuit, and the output ends of the two-phase non-overlapping clock generation circuit are connected to the buffer circuit to output corresponding clock signals.

10. A temperature sensor characterized by: The temperature sensor has the high-precision integrated temperature sensor circuit in any one of claims 1-9.

Images