10-gigabit optical receiving circuit
By introducing photodiodes, transimpedance amplifiers, differential amplifiers, and limiting amplifiers into the optical communication system, combined with active post-stage equalization and matching circuits, the problems of low signal-to-noise ratio and level mismatch at the receiver end are solved, thereby improving the signal quality and data transmission efficiency of the 10 Gigabit optical communication system.
Patent Information
- Application Number
- CN202423171333.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-23
AI Technical Summary
In existing optical communication systems, the voltage signal output by the transimpedance amplifier at the receiving end has a poor signal-to-noise ratio, with a small signal and high noise. This is especially true in 10-gigabit speed systems where a high signal-to-noise ratio is required. The mismatch between the level standards of analog and digital circuits also affects communication quality.
A 10-gigabit optical receiver circuit is adopted, including a photodiode, a transimpedance amplifier, a differential amplifier, and a limiting amplifier. Combined with an active post-stage equalization circuit and a matching circuit, it enhances the high-frequency response capability, reduces the impact of noise, and removes low-frequency noise through high-pass filtering to achieve hard decision and level standard matching of the signal.
It improves the signal-to-noise ratio of the receiving circuit, enhances the response capability of high-frequency signals, reduces the impact of noise, and improves the signal quality and data transmission efficiency of the communication system.
Smart Images
Figure CN223729748U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of visible light communication, specifically, relates to a kind of gigabit optical receiving circuit. BACKGROUND
[0002] Visible light communication technology (Visible Light Communication, VLC) is a kind of wireless optical communication technology using visible light wave as signal carrier for wireless high-speed communication.VLC uses visible light spectrum, which is a kind of unregulated, free to use spectrum.The most important thing is that VLC and existing radio frequency (Radio Frequency, RF) communication do not interfere with each other.In a narrow sense, VLC uses existing semiconductor lighting devices (Light Emitting Diodes, LED) as the transmitter of communication, and uses the high-speed bright and dark flashing signal emitted by LED light source to transmit information.VLC technology, which integrates visible light illumination and digital communication, will promote the progress of next-generation lighting and access network technology.
[0003] Visible light communication system is an intensity modulation / direct detection (Intensity Modulation / Direct Detection, IM / DD) system, and the light source and receiving end of the system are respectively composed of LED and PD (photodiode).After the information is modulated on the electrical signal, the LED is excited, and the LED can only obtain the amplitude information of the electrical signal with a voltage value greater than the working threshold value of the LED, and the current generated at the receiving end is also proportional to the received power.PD at the receiving end only detects the intensity of light, and does not detect the frequency and phase information of the signal.
[0004] In the design of optical communication system, the photoelectric detection device at the receiving end needs a transimpedance amplifier, which converts the current signal output by the current-type detector into a voltage signal.However, the voltage signal output by the transimpedance amplifier has poor signal-to-noise ratio, small signal and large noise.But the receiving end has certain requirements for the signal-to-noise ratio, especially in the receiving system of gigabit rate, which has higher requirements for signal-to-noise ratio.
[0005] In the design of optical communication system, it is usually divided into analog circuit design and digital circuit design, and there is a mismatch problem between the level standards of analog circuit and digital circuit.For example, the input signal level standard of digital board can be LVCOMS (Low Voltage Complementary Metal Oxide Semiconductor), and the output level standard of analog circuit can be LVDS (Low-Voltage Differential Signaling).
[0006] In order to solve the above problems, people have been seeking an ideal technical solution. SUMMARY
[0007] The utility model discloses to the deficiency of prior art, to provide a kind of gigabit optical receiving circuit, to enhance the high frequency response capability of receiving circuit, reduce the influence of noise, match the level standard of analog circuit and digital circuit.
[0008] In order to achieve the above object, the utility model provides a kind of gigabit optical receiving circuit, including photodiode PD, transimpedance amplifier TIA, differential amplifier Amp and limiting amplifier LA;
[0009] Photodiode PD is connected in series between the two input terminals of transimpedance amplifier TIA;
[0010] Resistance R1 is connected in series between the first input terminal of differential amplifier Amp and the first output terminal of transimpedance amplifier TIA, and capacitor C3 is connected in parallel with resistance R1;
[0011] Resistance R2 is connected in series between the second input terminal of differential amplifier Amp and the second output terminal of transimpedance amplifier TIA, and capacitor C4 is connected in parallel with resistance R2;
[0012] Resistance R3 is connected in series between the first input terminal of differential amplifier Amp and the first output terminal of differential amplifier Amp, and resistance R4 is connected in series between the second input terminal of differential amplifier Amp and the second output terminal of differential amplifier Amp;
[0013] The output terminal of differential amplifier Amp is connected to the input terminal of limiting amplifier LA and signal processing module in sequence.
[0014] Based on the above, the signal processing module is a digital signal processing module;It further includes a matching circuit, which is connected in series between the limiting amplifier LA and the digital signal processing module.
[0015] Based on the above, the matching circuit is a first matching circuit, and the first matching circuit includes resistance R6, resistance R7, resistance R8, resistance R9, capacitor C7 and capacitor C8;
[0016] The first output terminal of limiting amplifier LA is connected to capacitor C7 and resistance R6 in sequence, and then connected to the first input terminal of digital signal processing module, and the first output terminal of limiting amplifier LA is connected to resistance R8, and then connected to first power supply;
[0017] The second output terminal of limiting amplifier LA is connected to capacitor C8 and resistance R7 in sequence, and then connected to the second input terminal of digital signal processing module, and the second output terminal of limiting amplifier LA is connected to resistance R9, and then connected to second power supply.
[0018] Based on the above, the matching circuit is a second matching circuit, the second matching circuit comprises a resistor R10 and a resistor R11; further comprising a first clock data recovery circuit, the first clock data recovery circuit is connected in series between the limiting amplifier LA and the second matching circuit;
[0019] The resistor R10 is connected in series between the first output end of the first clock data recovery circuit and the first input end of the digital signal processing module;
[0020] The resistor R11 is connected in series between the second output end of the first clock data recovery circuit and the second input end of the digital signal processing module.
[0021] The utility model discloses relative prior art has substantial feature and progress, specifically speaking, the utility model has set up active post-stage equalizing circuit in second stage, and active post-stage equalizing circuit has higher gain bandwidth product (GBW), this means that still can provide sufficient gain under higher frequency, to enhance the response ability of high frequency signal, and active post-stage equalizing circuit removes low frequency noise through high pass filter, improves signal to noise ratio (SNR), reduces the influence of noise.
[0022] Considering that the noise detected by the receiving end is large, the utility model adopts a first circuit to realize hard decision of the received signal, and reduces the influence of noise, wherein the first circuit is a transimpedance amplifier circuit TIA. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 It is the circuit schematic diagram of the utility model embodiment 1;
[0024] Figure 2 It is the circuit schematic diagram of the utility model embodiment 2;
[0025] Figure 3 It is the circuit schematic diagram of the utility model embodiment 3;
[0026] Figure 4 It is the circuit schematic diagram of the utility model embodiment 4;
[0027] Figure 5 It is the circuit schematic diagram of the utility model embodiment 5;
[0028] Figure 6 It is the schematic diagram of active post-stage equalizing circuit of the utility model. DETAILED DESCRIPTION
[0029] The technical scheme of the utility model will be described in further detail below through specific implementation.
[0030] The terms "first", "second", "third", "fourth", and the like in the description and in the claims of the present application and above-described drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely employed for descriptive purposes.
[0031] Embodiment 1
[0032] As Figure 1 shown, the present embodiment provides a gigabit optical receiving circuit, comprising a photodiode PD, a transimpedance amplifier TIA, a differential amplifier Amp and a limiting amplifier LA;
[0033] The photodiode PD is connected in series between two input terminals of the transimpedance amplifier TIA;
[0034] The resistor R1 is connected in series between the first input terminal of the differential amplifier Amp and the first output terminal of the transimpedance amplifier TIA, and the capacitor C3 is connected in parallel with the resistor R1;
[0035] The resistor R2 is connected in series between the second input terminal of the differential amplifier Amp and the second output terminal of the transimpedance amplifier TIA, and the capacitor C4 is connected in parallel with the resistor R2;
[0036] The resistor R3 is connected in series between the first input terminal of the differential amplifier Amp and the first output terminal of the differential amplifier Amp, and the resistor R4 is connected in series between the second input terminal of the differential amplifier Amp and the second output terminal of the differential amplifier Amp;
[0037] The output terminal of the differential amplifier Amp is connected in sequence with the input terminal of the limiting amplifier LA and the input terminal of the signal processing module, specifically, the output terminal of the differential amplifier Amp is connected with the input terminal of the limiting amplifier LA, and the output terminal of the limiting amplifier LA is connected with the input terminal of the signal processing module.
[0038] It should be noted that: the utility model can be used for the receiving end of gigabit optical transmission link, and the combination circuit of the transimpedance amplifier TIA, the differential amplifier Amp and the limiting amplifier LA can realize the recovery of the input optical signal, the reception and amplification of the optical signal. Among them, the transimpedance amplifier (TIA): converts the photoelectric current into a voltage signal and performs preliminary amplification. The differential amplifier (Amp): further amplifies the signal, extracts the differential signal and improves the anti-interference ability. The limiting amplifier (LA): limits the amplitude of the signal, prevents distortion, and provides a stable output signal.
[0039] Compared with using only an amplification circuit at the second stage, the present embodiment uses an active post-stage equalization circuit at the second stage (such as Figure 6As shown, the active power equalizer circuit enhances the high-frequency response of the circuit, improves the signal-to-noise ratio, and reduces the impact of noise. The reasons include: the active power equalizer circuit has a high gain-bandwidth product (GBW), which means that it can still provide sufficient gain at higher frequencies, avoid excessive signal attenuation, and enhance the response of high-frequency signals; in optoelectronic communication systems, the signal contains noise, especially in the low-frequency range. The active circuit removes low-frequency noise through high-pass filtering while maintaining the transmission of high-frequency signals. This high-frequency enhancement effect helps to improve the signal-to-noise ratio (SNR) and data transmission quality of the system.
[0040] The amplitude-frequency response expression of the active post-equalization circuit is approximately shown in the following equation:
[0041] .
[0042] Therefore, ideally, the higher the signal frequency, the better the signal amplification effect at the receiver.
[0043] Secondly, since the signal-to-noise ratio of the optical signal detected by the receiver is limited, that is, the noise intensity is relatively large, for example, when the transmitter uses OOK modulation (On-Off Keying), the receiver can achieve hard decision on the received signal by using a single-stage circuit, namely the transimpedance amplifier circuit (TIA), so as to reduce the influence of noise.
[0044] Example 2
[0045] like Figure 2 As shown, the difference between this embodiment and Embodiment 1 lies in the specific implementation of the signal processing module. This signal processing module is a digital signal processing module, and a matching circuit is added. The matching circuit's function is to match the output level of the limiting amplifier LA with the input level of the digital signal processing module. In this embodiment, the matching circuit is a first matching circuit.
[0046] Specifically, the first matching circuit is connected in series between the limiting amplifier LA and the digital signal processing module. The first matching circuit includes resistors R6, R7, R8, and R9, and capacitors C7 and C8.
[0047] The first output terminal of the limiting amplifier LA is connected to capacitor C7 and resistor R6 in sequence, and then connected to the first input terminal of the digital signal processing module. The first output terminal of the limiting amplifier LA is connected to resistor R8 and then connected to the first power supply.
[0048] The second output terminal of the limiting amplifier LA is connected to capacitor C8 and resistor R7 in sequence, and then connected to the second input terminal of the digital signal processing module. The second output terminal of the limiting amplifier LA is connected to resistor R9 and then connected to the second power supply.
[0049] The first power supply can be a 1.2-volt power supply, and the second power supply can be a 1.2-volt power supply.
[0050] It should be noted that the levels of the analog circuit and the digital circuit are not matched. In the design of an optical communication system, the design is divided into an analog circuit and a digital circuit. For example, the level standard of the input signal of a digital board is LVCOMS, and the output level standard of the analog circuit is LVDS. Based on this, the level conversion can be realized by the first matching circuit in Embodiment 2, and the problem of the level mismatch between the analog circuit and the digital circuit in the optical communication system is solved, that is, the output signal of the limiting amplifier LA of the first matching circuit can be adapted to the digital signal processing module.
[0051] Embodiment 3
[0052] As shown in Figure 3 , the difference between this embodiment and Embodiment 1 is that the specific implementation of the signal processing module is given. The signal processing module is a digital signal processing module, and a matching circuit and a first clock and data recovery circuit are added. The matching circuit in this embodiment is a second matching circuit.
[0053] Specifically, the output end of the limiting amplifier LA is connected to the input end of the first clock and data recovery circuit, and the output end of the first clock and data recovery circuit is connected to the input end of the digital signal processing module in turn through the second matching circuit; wherein the second matching circuit comprises a resistor R10 and a resistor R11.
[0054] The resistor R10 is connected in series between the first output end of the first clock and data recovery circuit and the first input end of the digital signal processing module.
[0055] The resistor R11 is connected in series between the second output end of the first clock and data recovery circuit and the second input end of the digital signal processing module.
[0056] It should be noted that in order to facilitate the processing of the subsequent digital circuit, a first clock and data recovery circuit is further connected to the output end of the limiting amplifier, and the purpose is to realize bit synchronization of the received signal through the first clock and data recovery circuit. Then, the output end of the first clock and data recovery circuit is connected to the second matching circuit to realize the level conversion and adapt to the digital signal processing module.
[0057] It should be further noted that when the signal processing module is a digital signal processing module, whether to use a first clock and data recovery circuit can be determined according to the actual use of the receiving circuit, that is, whether to use the mode of Embodiment 2 or Embodiment 3. The present application designs two kinds of level matching circuits to realize the level conversion and adapt to the digital signal processing module.
[0058] Embodiment 4
[0059] As Figure 4 shown, the embodiment is different from embodiment 3 in that capacitors C5, C6 and resistor R5 are added.
[0060] Specifically, capacitor C5 is connected in series between the first output end of differential amplifier Amp and the first input end of limiting amplifier LA;
[0061] Capacitor C6 is connected in series between the second output end of differential amplifier Amp and the second input end of limiting amplifier LA;
[0062] Resistor R5 is connected in series between the first output end of differential amplifier Amp and the second output end of differential amplifier Amp.
[0063] It should be noted that the combined circuit of capacitor C5, capacitor C6 and resistor R5 functions to remove low-frequency noise.
[0064] Embodiment 5
[0065] As Figure 5 shown, the embodiment is different from embodiment 4 in that capacitors C1, C2 and resistor R12 are added.
[0066] Specifically, capacitor C1 is connected in series between the first output end of transimpedance amplifier TIA and resistor R1;
[0067] Capacitor C2 is connected in series between the second output end of transimpedance amplifier TIA and resistor R2;
[0068] Resistor R12 is connected in series between the first connection point and the second connection point, wherein the first connection point is the connection point of capacitor C1 and resistor R1, and the second connection point is the connection point of capacitor C2 and resistor R2.
[0069] It should be noted that the combined circuit of capacitor C1, capacitor C2 and resistor R12 functions to remove low-frequency noise.
[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit them; although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or some technical features can be replaced by equivalent ones; without departing from the spirit of the technical solutions of the present application, they should be covered in the technical solution range of the present application claimed.
Claims
1. A 10-gigabit optical receiver circuit, characterized in that: The photodiode PD, the transimpedance amplifier TIA, the differential amplifier Amp and the limiting amplifier LA are connected in series. The photodiode PD is connected in series between two input terminals of the transimpedance amplifier TIA. The resistor R1 is connected in series between the first input terminal of the differential amplifier Amp and the first output terminal of the transimpedance amplifier TIA, and the capacitor C3 is connected in parallel with the resistor R1. The resistor R2 is connected in series between the second input terminal of the differential amplifier Amp and the second output terminal of the transimpedance amplifier TIA, and the capacitor C4 is connected in parallel with the resistor R2. The resistor R3 is connected in series between the first input terminal of the differential amplifier Amp and the first output terminal of the differential amplifier Amp, and the resistor R4 is connected in series between the second input terminal of the differential amplifier Amp and the second output terminal of the differential amplifier Amp. The output terminal of the differential amplifier Amp is connected to the input terminal of the signal processing module and the limiting amplifier LA in sequence.
2. The gigabit optical receiving circuit according to claim 1, wherein: The signal processing module is a digital signal processing module; and the matching circuit is connected in series between the limiting amplifier LA and the digital signal processing module.
3. The gigabit optical receiving circuit according to claim 2, wherein: The matching circuit is a first matching circuit, and the first matching circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a capacitor C7 and a capacitor C8. The first output terminal of the limiting amplifier LA is connected to the first input terminal of the digital signal processing module in sequence after the capacitor C7 and the resistor R6 connected with the capacitor C7, and the first output terminal of the limiting amplifier LA is connected to the first power supply after the resistor R8 connected with the first output terminal. The second output terminal of the limiting amplifier LA is connected to the second input terminal of the digital signal processing module in sequence after the capacitor C8 and the resistor R7 connected with the capacitor C8, and the second output terminal of the limiting amplifier LA is connected to the second power supply after the resistor R9 connected with the second output terminal.
4. The gigabit optical receiving circuit according to claim 2, wherein The matching circuit is a second matching circuit, and the second matching circuit comprises a resistor R10 and a resistor R11; and the first clock data recovery circuit is connected in series between the limiting amplifier LA and the second matching circuit. The resistor R10 is connected in series between the first output terminal of the first clock data recovery circuit and the first input terminal of the digital signal processing module. The resistor R11 is connected in series between the second output terminal of the first clock data recovery circuit and the second input terminal of the digital signal processing module.
5. The gigabit optical receiving circuit according to claim 3 or 4, wherein: The capacitor C5, the capacitor C6 and the resistor R5 are further included. The capacitor C5 is connected in series between the first output terminal of the differential amplifier Amp and the first input terminal of the limiting amplifier LA. The capacitor C6 is connected in series between the second output terminal of the differential amplifier Amp and the second input terminal of the limiting amplifier LA. The resistor R5 is connected in series between the first output terminal of the differential amplifier Amp and the second output terminal of the differential amplifier Amp.
6. The gigabit optical receiving circuit according to claim 3 or 4, wherein The capacitor C1, the capacitor C2 and the resistor R12 are further included. The capacitor C1 is connected in series between the first output terminal of the transimpedance amplifier TIA and the resistor R1. The capacitor C2 is connected in series between the second output terminal of the transimpedance amplifier TIA and the resistor R2. The resistor R12 is connected in series between the first connection point and the second connection point, wherein the first connection point is the connection point of the capacitor C1 and the resistor R1, and the second connection point is the connection point of the capacitor C2 and the resistor R2.