Seven-level inverter topology

Abstract

The utility model discloses a seven-level inverter topology, which relates to the technical field of multi-level structures and comprises an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm are mutually symmetrical except for the direction of a diode, and a plurality of switch tubes, direct current bus capacitors and flying capacitors in the upper bridge arm and the lower bridge arm are connected according to a specific rule. Working modes with seven different output voltages are realized by controlling the conduction state of the switch tube; the topology realizes voltage division through the DC bus capacitor, realizes intermediate level transition through the flying capacitor, combines an optimized circuit structure and a control strategy, has the advantages of simple circuit design, high efficiency, stable output voltage and the like, and is widely applicable to high-voltage and high-power inverter systems.

Description

Technical Field

[0001] This utility model relates to the technical field of multi-level structures, and more specifically, to a seven-level inverter topology. Background Technology

[0002] Three-level and multi-level converters have become one of the hot topics in research and application at home and abroad in recent years due to their outstanding advantages in high voltage, high quality and high efficiency. Among them, the diode clamped (NPC) type three-level structure has been the most widely studied and applied due to its simple structure and high reliability.

[0003] Besides MMC, typical medium-voltage inverters include diode-clamped (NPC) and cascaded H-bridge (CHB) multilevel inverters. Companies such as Ansalda, ABB, Siemens, and GE all offer high-power medium-voltage converters for marine applications based on NPC and CHB. Generally, in systems below 6kV, the primary topology used is the diode-clamped three-level inverter topology, such as ABB's PCS6000 series (32MW) and ACS6000 series (27MW). To improve the conversion performance of multilevel inverter circuits, ABB has also launched 5L-NPC products (ACS5000 series, etc.). Systems above 6kV can use CHB or a hybrid topology of NPC+CHB.

[0004] In 4kV DC integrated power systems for ships, NPC three-level inverters can utilize 3300VIGBT devices to achieve high-voltage, high-power output while avoiding series connection of devices. However, as ship power demands gradually increase and ship power systems evolve towards 10kV, existing NPC topologies and power device levels are no longer sufficient to meet the requirements. Utility Model Content

[0005] The purpose of this invention is to provide a seven-level inverter topology to achieve high voltage and high power output while improving circuit efficiency and output voltage stability.

[0006] The technical solution of this utility model is: a seven-level inverter topology is provided, which includes: an upper bridge arm and a lower bridge arm; one end of the upper bridge arm and the lower bridge arm are connected to the bus, and the other end is connected to the inverter;

[0007] The upper bridge arm includes the DC bus capacitor C. d1 Flying capacitor C f1 Diodes D1 and D3; switching transistors S1, S2, S5, S6, and S7; the lower bridge arm includes the DC bus capacitor C. d2 Flying capacitor Cf2 Diodes D2 and D4, switching transistors S3, S4, S8, S9, S 10 ;

[0008] For the upper bridge arm: DC bus capacitance C d1 The negative terminal is grounded, and the positive terminal is connected to the inverter in sequence through switching transistors S5, S6, and S7. The DC bus capacitor C d1 The negative terminal is also connected to the flying capacitor C in sequence through switching transistors S2 and S1. f1 Positive terminal, flying capacitor C f1 The positive terminal is simultaneously connected between switching transistors S5 and S6; the flying capacitor C f1 The negative terminal of diode D1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switching transistors S1 and S2; the flying capacitor C f1 The negative terminal is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switching transistors S6 and S7;

[0009] For the lower bridge arm: DC bus capacitance C d2 The positive terminal is grounded, and the negative terminal passes through the switching transistor S in sequence. 10 S9 and S8 are connected to the inverter, and the DC bus capacitor C d2 The positive terminal is also connected to the flying capacitor C in sequence through switching transistors S3 and S4. f2 Negative terminal, flying capacitor C f2 The negative terminal is simultaneously connected to the switching transistor S. 10 Between S9; flying capacitor C f2 The positive terminal of diode D2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switching transistors S3 and S4; the flying capacitor C f2 The positive terminal is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switching transistors S8 and S9.

[0010] In any of the above technical solutions, the connection relationship between the upper bridge arm and the lower bridge arm further includes: DC bus capacitor C d1 The negative terminal is connected to the DC bus capacitor C. d2 The positive terminal, the flying capacitor C f1 The negative terminal is connected to the flying capacitor C. f2 The positive terminal of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch S2 is connected to switch S3, and switch S7 is connected to switch S8.

[0011] In any of the above technical solutions, further, the DC bus capacitor C d1 and C d2 Located at the positive and negative ends of the DC bus, C d1 and C d2 The voltages are all half of the bus voltage, i.e., Udc / 2.

[0012] In any of the above technical solutions, further, the flying capacitor C f1 and C f2 Located between the bus capacitors, in U dc An intermediate voltage is generated between / 2 and 0, C f1 and C f2 The voltage is 1 / 3 of the DC bus voltage, i.e., U dc / 3.

[0013] In any of the above technical solutions, further, each switching transistor only needs to withstand the voltage of a flying capacitor or the voltage difference between adjacent levels, and the maximum voltage stress of each switching transistor and diode is U. dc / 3.

[0014] The beneficial effects of this utility model are:

[0015] The technical solution in this invention constructs a seven-level inverter topology and utilizes DC bus capacitor voltage division and flying capacitor intermediate level transition to achieve precise output voltage grading. It has the advantages of simple circuit structure, high efficiency, good voltage stability, and high power device utilization, and is suitable for high voltage and high power application scenarios. Attached Figure Description

[0016] The advantages of the above and additional aspects of this utility model will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0017] Figure 1 This is a schematic diagram of a seven-level inverter topology according to an embodiment of the present invention;

[0018] Figure 2 It is a 1 / 2U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0019] Figure 3 This is the first 1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0020] Figure 4 This is a second 1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0021] Figure 5 This is the third 1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0022] Figure 6 This is the fourth 1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0023] Figure 7 This is the first 1 / 6U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0024] Figure 8 This is a second 1 / 6U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0025] Figure 9 This is the third 1 / 6U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0026] Figure 10 This is a schematic diagram of the first zero-output voltage equivalent circuit of a seven-level inverter topology according to an embodiment of the present invention;

[0027] Figure 11 This is a schematic diagram of the second zero-output voltage equivalent circuit of a seven-level inverter topology according to an embodiment of the present invention;

[0028] Figure 12 This is the first type -1 / 6U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0029] Figure 13 This is the second type -1 / 6U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0030] Figure 14 This is the third -1 / 6U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0031] Figure 15 This is the first -1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0032] Figure 16 This is the second type -1 / 3U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0033] Figure 17 This is the third -1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0034] Figure 18 This is the fourth -1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0035] Figure 19 It is a -1 / 2U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram. Detailed Implementation

[0036] To better understand the above-mentioned objectives, features, and advantages of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of this utility model and the features thereof can be combined with each other.

[0037] In the following description, many specific details are set forth in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0038] like Figure 1 As shown, this embodiment provides a seven-level inverter topology, which includes:

[0039] Two DC bus capacitors C d1 C d2 Two flying capacitors C f1 C f2 10 switching transistors S1 to S2 10 And four diodes D1 to D4.

[0040] Two DC bus capacitors C d1 and C d2 Located at the positive and negative terminals of the DC bus, they act as a voltage divider, causing the bus voltage U to... dc It remains stable under different voltage levels. d1 and C d2 The voltages are all half of the bus voltage (i.e., U). dc / 2), thereby providing graded support for the circuit's output voltage.

[0041] Two flying capacitors C f1 and C f2 The intermediate level transition is achieved by charging and discharging the capacitors, with two flying capacitors C. f1and C f2 Located between the bus capacitors, in U dc An intermediate voltage is generated between / 2 and 0. In this voltage divider topology, C f1 and C f2 The voltage is 1 / 3 of the DC bus voltage (i.e., U). dc / 3), to achieve voltage grading between different levels.

[0042] Furthermore, the voltage stress on the switching transistor and diode is determined by the maximum voltage difference across their terminals. Each switching transistor only needs to withstand the voltage of a flying capacitor or the voltage difference between adjacent voltage levels. Since the voltage across the flying capacitor is U... dc / 3, therefore the maximum voltage stress of each switch and diode is U dc / 3. Effectively improves the maximum voltage withstand range of this topology.

[0043] Each switch in the circuit is controlled by a gate signal to control its on or off state, thereby changing the current flow and output level. These switches form multiple different paths according to their connection positions, resulting in a total of seven voltage output levels.

[0044] The circuit connects diodes D1 to D4 in different branches to control the direction of current and prevent the generation of reverse current.

[0045] The circuit is divided into an upper bridge arm and a lower bridge arm, which are symmetrical to each other except for the direction of the diodes. The upper bridge arm includes the DC bus capacitor C. d1 Flying capacitor C f1 Diodes D1 and D3; switching transistors S1, S2, S5, S6, and S7; the lower bridge arm includes the DC bus capacitor C. d2 Flying capacitor C f2 Diodes D2 and D4, switching transistors S3, S4, S8, S9, S 10 .

[0046] Specifically, for the upper bridge arm: DC bus capacitor C d1 The negative terminal is grounded, and the positive terminal is connected to the inverter in sequence through switching transistors S5, S6, and S7. The DC bus capacitor C d1 The negative terminal is also connected to the flying capacitor C in sequence through switching transistors S2 and S1. f1 Positive terminal, flying capacitor C f1 The positive terminal is simultaneously connected between switching transistors S5 and S6; the flying capacitor C f1 The negative terminal of diode D1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switching transistors S1 and S2; the flying capacitor C f1 The negative terminal is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switching transistors S6 and S7.

[0047] For the lower bridge arm: DC bus capacitance C d2 The positive terminal is grounded, and the negative terminal passes through the switching transistor S in sequence. 10 S9 and S8 are connected to the inverter, and the DC bus capacitor C d2 The positive terminal is also connected to the flying capacitor C in sequence through switching transistors S3 and S4. f2 Negative terminal, flying capacitor C f2 The negative terminal is simultaneously connected to the switching transistor S. 10 Between S9; flying capacitor C f2 The positive terminal of diode D2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switching transistors S3 and S4; the flying capacitor C f2 The positive terminal is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switching transistors S8 and S9.

[0048] For the connection of the upper and lower bridge arms: DC bus capacitor C d1 The negative terminal is connected to the DC bus capacitor C. d2 The positive terminal, the flying capacitor C f1 The negative terminal is connected to the flying capacitor C. f2 The positive terminal of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch S2 is connected to switch S3, and switch S7 is connected to switch S8.

[0049] By controlling the switching states of each transistor, 18 voltage output schemes are generated, as shown in Table 1 below:

[0050] Table 1 18 Voltage Output Schemes

[0051]

[0052] like Figures 2 to 19 As shown in the attached diagram, the equivalent circuit of each of the above schemes is illustrated. There are a total of 7 different output levels across the 18 schemes: 1 / 2U dc 1 / 3U dc 1 / 6U dc 0, -1 / 6U dc -1 / 3U dc -1 / 2U dc .

[0053] like Figure 2 As shown, switching transistors S5, S6, and S7 are turned on, while all other switching transistors are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 2U. dc .

[0054] like Figure 3As shown, switches S3, S6, and S7 are turned on, all other switches are turned off, diode D2 is turned on, and flying capacitor C... f1 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc .

[0055] like Figure 4 As shown, switches S2, S6, and S7 are turned on, all other switches are turned off, diode D1 is turned on, and flying capacitor C... f1 During charging, current flows into the inverter, and the output level is 1 / 3U. dc .

[0056] like Figure 5 As shown, switches S3, S4, and S7 are turned on, all other switches are turned off, diode D3 is turned on, and flying capacitor C is turned on. f2 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc .

[0057] like Figure 6 As shown, switches S3, S4, and S8 are turned on, all other switches are turned off, diode D4 is turned on, and flying capacitor C... f2 During charging, current flows into the inverter, and the output level is 1 / 3U. dc .

[0058] like Figure 7 As shown, switching transistors S5 and S7 are turned on, all other switching transistors are turned off, diode D3 is turned on, and flying capacitor C... f1 During charging, current flows out to the inverter, and the output level is 1 / 6U. dc .

[0059] like Figure 8 As shown, switching transistors S5 and S8 are turned on, all other switching transistors are turned off, diode D4 is turned on, and flying capacitor C is turned on. f1 Discharge occurs when current flows into the inverter, resulting in an output level of 1 / 6U. dc .

[0060] like Figure 9 As shown, the switching transistors S6, S7, and S... 10 With the circuit turned on, all other switching transistors are turned off, and the flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 6U. dc .

[0061] like Figure 10 As shown, switching transistors S3 and S7 are turned on, all other switching transistors are turned off, diodes D2 and D3 are turned on, and the flying capacitor C... f1 C f2 When both are discharged, current flows out to the inverter, and the output level is 0.

[0062] like Figure 11 As shown, switching transistors S2 and S8 are turned on, all other switching transistors are turned off, diodes D1 and D4 are turned on, and the flying capacitor C... f1 C f2 When both are charging, current flows into the inverter, and the output level is 0.

[0063] like Figure 12 As shown, switching transistors S7 and S... 10 With the circuit turned on, all other switching transistors are turned off, diode D3 is turned on, and the flying capacitor C... f2 Discharge occurs, current flows out to the inverter, and the output level is -1 / 6U. dc .

[0064] like Figure 13 As shown, switching transistors S8 and S... 10 With the circuit turned on, all other switching transistors are turned off, diode D4 is turned on, and the flying capacitor C... f2 During charging, current flows into the inverter, and the output level is -1 / 6U. dc .

[0065] like Figure 14 As shown, switching transistors S5, S8, and S9 are turned on, while all other switching transistors are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed; the output level is -1 / 6U. dc .

[0066] like Figure 15 As shown, switching transistors S1, S2, and S7 are turned on, all other switching transistors are turned off, diode D3 is turned on, and flying capacitor C... f1 During charging, current flows out to the inverter, and the output level is -1 / 3U. dc .

[0067] like Figure 16 As shown, switching transistors S1, S2, and S8 are turned on, all other switching transistors are turned off, and diode D4 is turned on. Flying capacitor C... f1 Discharge occurs when current flows into the inverter, resulting in an output level of -1 / 3U. dc .

[0068] like Figure 17 As shown, switching transistors S3, S8, and S9 are turned on, all other switching transistors are turned off, diode D2 is turned on, and flying capacitor C... f2 During charging, current flows out to the inverter, and the output level is -1 / 3U. dc .

[0069] like Figure 18 As shown, switches S2, S8, and S9 are turned on, all other switches are turned off, diode D1 is turned on, and flying capacitor C... f2Discharge occurs when current flows into the inverter, resulting in an output level of -1 / 3U. dc .

[0070] like Figure 19 As shown, the switching transistors S8, S9, and S... 10 With the circuit turned on, all other switching transistors are turned off, and the flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is -1 / 2U. dc .

[0071] In summary, this utility model proposes a seven-level inverter topology, including:

[0072] Upper and lower bridge arms; both the upper and lower bridge arms are connected to the bus at one end and to the inverter at the other end, with the bus voltage being U. dc .

[0073] The upper bridge arm includes the DC bus capacitor C. d1 Flying capacitor C f1 Diodes D1 and D3; switching transistors S1, S2, S5, S6, and S7; the lower bridge arm includes the DC bus capacitor C. d2 Flying capacitor C f2 Diodes D2 and D4, switching transistors S3, S4, S8, S9, S 10 .

[0074] For the upper bridge arm: DC bus capacitance C d1 The negative terminal is grounded, and the positive terminal is connected to the inverter in sequence through switching transistors S5, S6, and S7. The DC bus capacitor C d1 The negative terminal is also connected to the flying capacitor C in sequence through switching transistors S2 and S1. f1 Positive terminal, flying capacitor C f1 The positive terminal is simultaneously connected between switching transistors S5 and S6. Flying capacitor C f1 The negative terminal of diode D1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switching transistors S1 and S2; the flying capacitor C f1 The negative terminal is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switching transistors S6 and S7.

[0075] For the lower bridge arm: DC bus capacitance C d2 The positive terminal is grounded, and the negative terminal passes through the switching transistor S in sequence. 10 S9 and S8 are connected to the inverter, and the DC bus capacitor C d2 The positive terminal is also connected to the flying capacitor C in sequence through switching transistors S3 and S4. f2 Negative terminal, flying capacitor C f2 The negative terminal is simultaneously connected to the switching transistor S. 10 Between S9; flying capacitor C f2The positive terminal of diode D2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switching transistors S3 and S4; the flying capacitor C f2 The positive terminal is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switching transistors S8 and S9.

[0076] For the connection of the upper and lower bridge arms: DC bus capacitor C d1 The negative terminal is connected to the DC bus capacitor C. d2 The positive terminal, the flying capacitor C f1 The negative terminal is connected to the flying capacitor C. f2 The positive terminal of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch S2 is connected to switch S3, and switch S7 is connected to switch S8.

[0077] By controlling the switching states of each switching transistor, several operating schemes with a total of 7 different output voltages are formed, which output different voltages to the subsequent inverters.

[0078] In this utility model, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this utility model according to the specific circumstances.

[0079] The shapes of the components in the accompanying drawings are schematic and may differ from their actual shapes. The drawings are only used to illustrate the principle of this utility model and are not intended to limit this utility model.

[0080] Although the present invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the present invention. The scope of protection of the present invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the present invention.

Claims

1. A seven-level inverter topology, characterized by, The topology comprises: an upper bridge arm and a lower bridge arm; the upper bridge arm and the lower bridge arm are connected with a busbar at one end and connected with an inverter at the other end; wherein the upper bridge arm comprises a DC bus capacitor C d1 , a flying capacitor C f1 , diodes D1, D3, switch tubes S1, S2, S5, S6, S7; the lower bridge arm comprises a DC bus capacitor C d2 , a flying capacitor C f2 , diodes D2, D4, switch tubes S3, S4, S8, S9, S 10 ; For the upper bridge arm: the negative pole of the DC bus capacitor C d1 is grounded, and the positive pole is connected to the inverter in turn through the switch tubes S5, S6 and S7, and the negative pole of the DC bus capacitor C d1 is also connected to the flying capacitor C f1 in turn through the switch tubes S2 and S1, and the positive pole of the flying capacitor C f1 is connected to the switch tubes S5 and S6 at the same time; the negative pole of the flying capacitor C f1 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the switch tubes S1 and S2; the negative pole of the flying capacitor C f1 is also connected to the anode of the diode D3, and the cathode of the diode D3 is connected to the switch tubes S6 and S7; For the lower bridge arm: the positive pole of the DC bus capacitor C d2 is grounded, and the negative pole is connected to the inverter in turn through the switch tubes S 10 , S9, S8, the positive pole of the DC bus capacitor C d2 is also connected to the flying capacitor C f2 in turn through the switch tubes S3, S4, the negative pole of the flying capacitor C f2 is connected to the switch tubes S 10 , S9 at the same time; the positive pole of the flying capacitor C f2 is connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the switch tubes S3, S4; the positive pole of the flying capacitor C f2 is also connected to the cathode of the diode D4, and the anode of the diode D4 is connected to the switch tubes S8, S9.

2. The seven-level inverter topology of claim 1, wherein, The connection relationship of the upper bridge arm and the lower bridge arm includes: the negative electrode of the DC bus capacitor C d1 connects the positive electrode of the DC bus capacitor C d2 , the negative electrode of the flying capacitor C f1 connects the positive electrode of the flying capacitor C f2 , the anode of the diode D1 connects the cathode of the diode D2, the anode of the diode D3 connects the cathode of the diode D4, the switch tube S2 connects the switch tube S3, and the switch tube S7 connects the switch tube S8.

3. The seven-level inverter topology of any of claims 1, 2, wherein, The DC bus capacitor C d1 and C d2 are respectively located at the positive and negative ends of the DC bus, C d1 and C d2 have a voltage of half of the bus voltage, i.e. U dc / 2.

4. The seven-level inverter topology of claim 3, wherein, The flying capacitor C f1 and C f2 between the bus capacitors, between U dc / 2 and 0, the voltage of C f1 and C f2 is 1 / 3 of the DC bus voltage, i.e. U dc / 3.

5. The seven-level inverter topology of claim 4, wherein, Each of the switch tubes only needs to bear a voltage of a flying capacitor or a voltage difference of adjacent levels, and the maximum voltage stress of each switch tube and diode is U dc / 3.

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