A chip testing device

Abstract

This application provides a chip testing apparatus, including a test board for assembling a chip under test (DUT), and at least one loopback panel for performing insertion loss testing on the DUT. The test board is provided with at least one chip connector, and the loopback panel includes several loopback boards with different trace lengths. Each loopback board is provided with a board connector that forms a closed-loop test path with the chip connector. When the number of loopback panels is configured to be one, the insertion loss value between the loopback boards on the panel is less than 1 dB, and the trace lengths between the loopback boards increase sequentially in 600 mil increments. By splicing loopback boards with different trace lengths onto the loopback panel, the insertion loss testing requirements of different chips can be accommodated.

Description

Technical Field

[0001] This application belongs to the field of chip technology, specifically relating to a chip testing device. Background Technology

[0002] In the field of integrated circuits, SERDES (Serializer / Deserializer) is widely used in FPGA (Field Programmable Gate Array) chip design. Different models of FPGA chips with SERDES channels have different requirements for the insertion loss value during signal transmission at their specified frequencies.

[0003] To meet diverse testing requirements, related technologies typically design dedicated chip test boards and loopback boards for each PFGA chip, connecting them via high-speed male-female connectors. These customized loopback boards usually have only a few fixed insertion loss values ​​and are only applicable to that specific chip. If a different chip is used, the insertion loss values ​​of the existing loopback board may not meet the testing requirements, necessitating the repeated design of loopback boards with different insertion loss values ​​for different chips, impacting testing efficiency and resulting in cost waste. Utility Model Content

[0004] This application provides a chip testing device that can splice loopback boards of different trace lengths on a loopback panel to meet the insertion loss testing requirements of different chips.

[0005] To address the aforementioned technical problems, this application provides a chip testing apparatus, including a test board for assembling a chip under test, and at least one loopback panel for performing insertion loss testing on the chip under test.

[0006] The test board is equipped with at least one chip connector, and the loopback panel includes several loopback panels with different trace lengths.

[0007] Each of the loopback boards is provided with a board connector that forms a closed-loop test path with the chip connector.

[0008] As a further improvement of this application, when the number of loopback panels is configured to be one, the insertion loss value between the loopback panels disposed on the loopback panel is less than 1 dB.

[0009] As a further improvement to this application, the trace length between several loopback boards is increased sequentially in increments of 600 mil.

[0010] As a further improvement of this application, when the number of loopback panels is configured to be three, the trace length of the first loopback panel increases from 280 mil, the trace length of the second loopback panel increases from 880 mil, and the trace length of the third loopback panel increases from 1480 mil.

[0011] As a further improvement to this application, the trace length of the first loopback panel is increased to 30880mil, the trace length of the second loopback panel is increased to 31480mil, and the trace length of the third loopback panel is increased to 32080mil.

[0012] As a further improvement of this application, in the same loop panel, the trace length between several loop panels is increased sequentially in increments of 1800 mil.

[0013] As a further improvement of this application, each loopback panel is provided with 18 loopback plates, and several loopback plates are arranged sequentially on the loopback panel according to the routing length.

[0014] As a further improvement to this application, each of the board connectors is configured to connect to five serial transceiver unit groups of the chip under test;

[0015] Each of the serial transceiver unit groups includes four receive channels and four transmit channels.

[0016] As a further improvement to this application, several of the said loop plates are all the same size.

[0017] As a further improvement to this application, the material of the loop plate is M6 sheet metal.

[0018] Compared with existing technologies, the chip testing apparatus provided in this application integrates loopback boards of different trace lengths on at least one loopback panel, thereby covering different insertion loss value testing requirements. When different chips need to be tested, it is not necessary to customize a dedicated loopback board for each chip. Instead, a loopback board with the corresponding trace length is directly selected from the loopback panel according to the insertion loss value testing requirements of the chip. The chip connector on the test board is connected to the board connector on the corresponding loopback board for testing. This avoids the problem of loopback board idleness and cost waste caused by customizing loopback boards separately, and improves the insertion loss value coverage of the testing apparatus while reducing testing costs. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the chip testing device provided in the embodiments of this application;

[0021] Figure 2 This is a diagram of one embodiment of the loopback panel in the chip testing apparatus provided in this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0023] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the figures). If the specific posture changes, the directional indication will also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0024] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this application are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and step sequences.

[0025] Please refer to Figures 1-2 This application provides a chip testing device that can splice loopback boards of different trace lengths on a loopback splice board to meet the insertion loss testing requirements of different chips.

[0026] Please refer to Figure 1The diagram below shows the structure of a chip testing device provided in this application. The chip testing device includes a test board for assembling the chip under test and at least one loopback panel for performing insertion loss testing on the chip under test. It can be observed that the test board is provided with at least one chip connector, and the loopback panel includes several loopback panels with different trace lengths. Each loopback panel is provided with a board connector that can form a closed-loop test path with the chip connector.

[0027] Since longer trace lengths correspond to higher insertion loss values ​​and shorter trace lengths correspond to lower insertion loss values ​​during signal transmission, this application embodiment provides several loopback boards with different trace lengths on at least one loopback panel. By using different trace lengths to cover different insertion loss values, it adapts to the insertion loss testing requirements of different chips at a specified frequency.

[0028] Furthermore, in practical applications, based on the number of SERDES channels and insertion loss requirements of the chip under test, a loopback board with the corresponding trace length can be selected on the loopback panel for testing. The chip under test is then assembled on the test board, and the chip connector on the test board is connected to the board connector on the corresponding loopback board.

[0029] In this way, the SERDES channel signal of the chip under test is output from the chip connector, transmitted through the PCB (Printed Circuit Board) traces on the loopback board, and then returned to the chip connector through the board connector, forming a closed-loop test path to achieve insertion loss testing of the current chip under test.

[0030] It is understood that the chip under test here can be a PFGA chip with different numbers of SERDES channels, or other types of chips. As long as the chip needs to be tested for insertion loss, it is feasible. This application does not impose too many restrictions on the type of chip under test or its specific number of SERDES channels.

[0031] In this embodiment, loopback boards with different trace lengths are integrated on at least one loopback panel to cover different insertion loss test requirements. When different chips need to be tested, it is not necessary to customize a dedicated loopback board for each chip. Instead, a loopback board with the corresponding trace length can be selected directly from the loopback panel according to the insertion loss requirement of the chip. The chip connector on the test board is connected to the board connector on the corresponding loopback board for testing. This avoids the problem of idle loopback boards and cost waste caused by customizing loopback boards separately. It reduces testing costs while improving the insertion loss coverage of the testing device.

[0032] As an optional implementation, since the slight differences in insertion loss values ​​between chips in high-speed signal transmission scenarios such as (16GHz) may directly affect the accuracy of test results, when only one loopback panel is set, this application needs to limit the insertion loss values ​​of several loopback panels set on the loopback panel. Preferably, the insertion loss value between loopback panels with adjacent trace lengths is controlled within 1dB to avoid the test results deviating from the actual test requirements of the chip due to excessively large differences in insertion loss values.

[0033] Furthermore, calculations show that the insertion loss of a 600mil trace at 16GHz is approximately 0.8dB, less than 1dB. Therefore, when only one loopback panel is used, it is preferable to set the trace length between several loopback panels in the loopback panel to increase sequentially in steps of 600mil. This step value can control the insertion loss between loopback panels with adjacent trace lengths to within 1dB and also avoid test errors caused by excessive insertion loss deviation.

[0034] It should be noted that if the step value is set too small, such as 100mil, although the insertion loss between loopback boards with adjacent trace lengths can be further reduced, it will increase the number of loopback boards and the design complexity of the loopback panel. If the step value is set too large, such as 1000mil, the insertion loss between loopback boards with adjacent trace lengths may exceed 1dB. Therefore, this application preferably sets the trace length between several loopback boards to increase sequentially in steps of 600mil.

[0035] In an optional embodiment, if only one loopback panel is set, too many loopback panels with different routing lengths need to be integrated on the loopback panel, resulting in an excessively large overall size of the loopback panel, which increases manufacturing costs and process complexity to a certain extent. Therefore, this application preferably sets the number of loopback panels to three, reducing the number of loopback panels set on a single loopback panel and the size of the loopback panel, thereby improving the feasibility of portable use of the loopback panel.

[0036] Furthermore, the trace length of the first loopback panel is set to increase from 280 mil, the trace length of the second loopback panel is set to increase from 880 mil, and the trace length of the third loopback panel is set to increase from 1480 mil, ensuring that the trace lengths of the three loopback panels differ by 600 mil at the beginning, covering the insertion loss test range starting from 280 mil (approximately 0.3 dB).

[0037] It is understandable that directly setting the starting trace length of the second loop panel based on the final trace length of the first loop panel, and setting the starting trace length of the third loop panel based on the final trace length of the second loop panel, would increase the design complexity and manufacturing cost of the traces for the second and third loop panels. However, this application sets the trace lengths of the three loop panels to increase incrementally from 280mil, 880mil, and 1480mil respectively, which avoids the layout complexity and process risks associated with excessively long starting traces while ensuring insertion loss coverage.

[0038] Based on this, this application sets the trace length of the first loopback panel to 30880mil, the trace length of the second loopback panel to 31480mil, and the trace length of the third loopback panel to 32080mil, thereby covering the insertion loss range from 0.3dB to 44dB, adapting to the insertion loss testing requirements of different chips at various frequency points, and improving the versatility of the testing device.

[0039] Furthermore, when three loopback panels are set, it is preferable that the trace lengths between several loopback panels in the same loopback panel are increased sequentially in increments of 1800 mil. Taking the first loopback panel as an example, the trace length of the initial loopback panel in this loopback panel is 280 mil, the trace length of the second loopback panel is 2080 mil, the trace length of the third loopback panel is 3880 mil, and so on, increasing sequentially in increments of 1800 mil until it increases to 30880 mil.

[0040] In the second loop panel, the trace length of the initial loop panel is 880mil, the trace length of the second loop panel is 2680mil, the trace length of the third loop panel is 4880mil, and so on, increasing in increments of 1800mil until it reaches 31480mil.

[0041] In the third loop panel, the trace length of the starting loop panel is 1480mil, the trace length of the second loop panel is 3280mil, the trace length of the third loop panel is 5080mil, and so on, increasing in increments of 1800mil until it reaches 32080mil.

[0042] In this way, all loopback boards in the three loopback panels cover a trace length starting from 280mil and increasing in steps of 600mil to 32080mil, thereby controlling the insertion loss of adjacent trace lengths to within 1dB and covering the insertion loss range of 0.3dB to 44dB.

[0043] It should be noted that the test board will also incur some losses due to the signal transmission characteristics. Combining the losses of the test board and the loopback board, the entire test device can achieve an insertion loss coverage range of more than 50dB at a frequency of 16GHz. Based on testing experience, an insertion loss coverage range of 50dB can basically meet the testing requirements of all FPGA chips with SERDES channels.

[0044] As an optional implementation method, please refer to Figure 2 This is an embodiment of the loopback panel in the chip testing device provided in this application. This application provides 18 loopback panels on each loopback panel. Several loopback panels are arranged on the loopback panel in order of trace length, such as from left to right or from top to bottom, so that the trace layout on the same loopback panel is more regular and the layout difficulty caused by the cross arrangement of different trace lengths is reduced.

[0045] Of course, the number of loopback panels and the number of loopback panels in each loopback panel can be adjusted to meet actual testing needs, and this application does not impose any further restrictions on this.

[0046] Preferably, this application sets several loopback boards of the same size, which makes it easy to evenly distribute several loopback boards on the loopback panel according to the trace length, so that the tester can directly locate the loopback board with the appropriate trace length according to the test requirements.

[0047] For example, the material of the loopback board can be set to M6 board material, which is a PCB substrate material designed for high-frequency and high-speed signal transmission. This substrate material has a very low loss factor and its dielectric constant fluctuates very little over a wide frequency range, thus effectively improving the detection accuracy of the test device.

[0048] As an optional implementation, the above-mentioned board connectors and chip connectors can be configured as high-speed connector male and high-speed connector female, such as setting the high-speed connector female on the test board and setting the high-speed connector male on each loopback board, forming the required closed-loop test path through the high-speed connector male and high-speed connector female.

[0049] Specifically, each loopback board can be connected to five SERDES QUADs (serial transceiver units) of the chip under test via a board connector. Each SERDES QUAD includes four SERDES channels, and each SERDES channel includes one receive channel and one transmit channel. In other words, each SERDES QUAD actually includes four receive channels and four transmit channels.

[0050] In an optional embodiment, if the number of SERDES QUADs of a chip under test does not exceed 5, the SERDES QUADs of the chip under test can be directly connected to a corresponding loopback board through the chip connector to form a complete closed-loop test path.

[0051] If the number of SERDES QUADs of a chip under test exceeds 5, multiple loopback boards need to be used for testing to adapt to the number of SERDES channels of the chip under test.

[0052] For example, if a chip under test has a total of 7 SERDES QUADs from Q1 to Q7, then two chip connectors need to be set on the test board. During testing, the first loopback board is connected to the chip under test's 5 SERDES QUADs from Q1 to Q5 through the board connector and the first chip connector. The second loopback board is connected to the remaining 2 SERDES QUADs from Q6 to Q7 of the chip under test through the board connector and the second chip connector.

[0053] Of course, in practical applications, the corresponding loopback board with the appropriate trace length and the corresponding number of loopback boards need to be selected according to the specific number of ERDES QUADs of the chip under test and the insertion loss test requirements. This application will not go into too much detail here.

[0054] The chip testing apparatus provided in this application integrates loopback boards of different trace lengths onto at least one loopback panel, thereby covering different insertion loss value testing requirements. When different chips need to be tested, it is not necessary to customize a dedicated loopback board for each chip. Instead, a loopback board with the corresponding trace length is directly selected from the loopback panel according to the insertion loss value testing requirements of the chip. The chip connector on the test board is then connected to the board connector on the corresponding loopback board for testing. This avoids the problem of idle loopback boards and cost waste caused by customizing loopback boards separately, thereby reducing testing costs and improving the insertion loss value coverage of the testing apparatus.

[0055] Meanwhile, the multiple loopback boards on the loopback panel provide a wider range of insertion loss values, making it easier to test the chip's performance under different insertion loss conditions, thereby testing the chip's extreme performance.

[0056] It is understood that, in specific implementations, the modules / units included in the various devices and products described in the above embodiments may be software modules / units, hardware modules / units, or may be partly software modules / units and partly hardware modules / units.

[0057] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0058] It is understood that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above embodiments are merely exemplary implementations used to illustrate the principles of this application; however, this application is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this application, and these modifications and improvements are also considered to be within the scope of protection of this application.

Claims

1. A chip testing device, characterized in that, It includes a test board for assembling the chip under test, and at least one loopback panel for performing insertion loss testing on the chip under test; The test board is equipped with at least one chip connector, and the loopback panel includes several loopback panels with different trace lengths. Each of the loopback boards is provided with a board connector that forms a closed-loop test path with the chip connector.

2. The chip testing apparatus as described in claim 1, characterized in that, When the number of loopback panels is configured to be one, the insertion loss between the loopback panels disposed on the loopback panel is less than 1 dB.

3. The chip testing apparatus as described in claim 2, characterized in that, The trace lengths between several loopback boards are increased sequentially in increments of 600 mil.

4. The chip testing apparatus as described in claim 1, characterized in that, When the number of loopback panels is configured to be three, the trace length of the first loopback panel increases from 280 mil, the trace length of the second loopback panel increases from 880 mil, and the trace length of the third loopback panel increases from 1480 mil.

5. The chip testing apparatus as described in claim 4, characterized in that, The trace length of the first loopback panel increases to 30880mil, the trace length of the second loopback panel increases to 31480mil, and the trace length of the third loopback panel increases to 32080mil.

6. The chip testing apparatus as described in claim 4, characterized in that, In the same loop panel, the trace length between several loop panels increases sequentially in increments of 1800 mil.

7. The chip testing apparatus according to any one of claims 4-6, characterized in that, Each loopback panel is provided with 18 loopback plates, and several loopback plates are arranged sequentially on the loopback panel according to the routing length.

8. The chip testing apparatus as described in claim 1, characterized in that, Each of the board connectors is configured to connect to five serial transceiver unit groups of the chip under test; Each of the serial transceiver unit groups includes four receive channels and four transmit channels.

9. The chip testing apparatus as described in claim 1, characterized in that, The dimensions of all of the aforementioned loop plates are identical.

10. The chip testing apparatus as described in claim 1, characterized in that, The material of the loop plate is M6 sheet.

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