An overvoltage reverse connection short circuit protection circuit

Abstract

This utility model relates to the field of chip port protection circuit technology, and provides an overvoltage reverse connection short circuit protection circuit, including: a low-side reverse connection protection circuit, a protection circuit A, a protected circuit, a protection circuit C, and a protection circuit B. The low-side reverse connection protection circuit includes a second high-voltage NMOS transistor, a fourth Zener diode, and a fifth resistor; the VDDE port of the protection circuit A is connected to the external power supply VDDE port, and the VSSE port of the protection circuit A is connected to the source of the second high-voltage NMOS transistor Q4 of the low-side reverse connection protection circuit; the VDD and VSS ports of the protection circuit A are respectively connected to the protected circuit; the protected circuit includes a core circuit and an output stage circuit; the protection circuit C includes a third high-voltage NMOS transistor, a fifth Zener diode, and a sixth resistor. This utility model can protect the chip when overvoltage, reverse connection, or short circuit occurs between the OUT, VDDE, and VSSE ports.

Description

Technical Field

[0001] This utility model relates to the field of chip port protection circuit technology, and in particular to an overvoltage reverse connection short circuit protection circuit. Background Technology

[0002] Overvoltage, reverse connection, and short-circuit protection circuits between chip ports are common protection designs in high-reliability chips. These circuits prevent damage to the chip from abnormal power supply conditions (such as overvoltage or reversed polarity) and load short circuits. For example, in automotive sensor systems, the normal operating supply voltage is typically 5V. However, during engine startup, the battery voltage fluctuates due to the operation of high-current devices such as the starter motor, potentially spikeing to 12V or even 40V. Therefore, it is generally required that the chip's output (OUT) and the power supply (VDDE) and ground (VSSE) ports have overvoltage, reverse connection, and short-circuit protection functions.

[0003] Overvoltage and reverse connection protection between the VDDE and VSSE ports is now relatively mature. Overvoltage protection for the OUT port is usually achieved by using a series resistor, which bears most of the overvoltage, thus protecting the internal circuitry. However, for applications requiring a large dynamic range, such as pressure sensor chips where the analog output level range needs to reach 90% (VDDE-VSSE), the voltage drop across the series resistor, especially under high current conditions, makes it difficult to achieve these application goals.

[0004] The utility model patent (CN 110311668A) discloses a circuit and method for protecting the forward overvoltage and reverse voltage of a chip output pin. It can solve the overvoltage and reverse connection protection problems between the VDDE and VSSE ports, as well as the overvoltage protection problem of the OUT port relative to the VDDE and VSSE ports. However, it cannot solve the problem of simultaneous short circuit overvoltage between the OUT port and the VDDE port or the VSSE port. Utility Model Content

[0005] This utility model mainly solves the technical problem of overvoltage, reverse connection and short circuit protection between the three ports OUT, VDDE and VSSE, which cannot be solved by the existing technology. It proposes an overvoltage, reverse connection and short circuit protection circuit to protect the chip when overvoltage, reverse connection and short circuit occur between the three ports OUT, VDDE and VSSE.

[0006] This utility model provides an overvoltage reverse connection short circuit protection circuit, including: a low-side reverse connection protection circuit, a protection circuit A, a protected circuit, a protection circuit C, and a protection circuit B;

[0007] The low-side reverse connection protection circuit includes: a second high-voltage NMOS transistor Q4, a fourth Zener diode D4, and a fifth resistor R5; the gate of the second high-voltage NMOS transistor Q4 is connected to the cathode of the fourth Zener diode D4, the source of the second high-voltage NMOS transistor Q4 is connected to the anode of the fourth Zener diode D4, and the drain of the second high-voltage NMOS transistor Q4 is connected to the external power supply VSSE port; one end of the fifth resistor R5 is connected to the gate of the second high-voltage NMOS transistor Q4, and the other end is connected to the external power supply VDDE port;

[0008] The VDDE port of the protection circuit A is connected to the external power supply VDDE port, and the VSSE port of the protection circuit A is connected to the source of the second high-voltage NMOS transistor Q4 of the low-side reverse connection protection circuit; the VDD port and VSS port of the protection circuit A are respectively connected to the protected circuit, providing power and ground signals to the protected circuit respectively.

[0009] The protected circuit includes: a core circuit and an output stage circuit;

[0010] The output stage circuit includes: a general-purpose PMOS transistor Q5 and a general-purpose NMOS transistor Q6;

[0011] The source of the ordinary PMOS transistor Q5 and the VDD port of the core circuit are connected to the VDD port of the protection circuit A; the gate of the ordinary PMOS transistor Q5 is connected to the core circuit; and the drain of the ordinary PMOS transistor Q5 is connected to the protection circuit C.

[0012] The source of the ordinary NMOS transistor Q6, the VSS port of the core circuit, and the VSS port of the protection circuit A are connected; the gate of the ordinary NMOS transistor Q6 is connected to the core circuit; and the drain of the ordinary NMOS transistor Q6 is connected to the protection circuit C.

[0013] The protection circuit C includes: a third high-voltage NMOS transistor Q7, a fifth Zener diode D5, and a sixth resistor R6;

[0014] One end of the sixth resistor R6 is connected to the VDD port of the core circuit, and the other end is connected to the cathode of the fifth Zener diode D5; the anode of the fifth Zener diode D5 is connected to the VSS port of the core circuit.

[0015] The gate of the third high-voltage NMOS transistor Q7 is connected to the cathode of the fifth Zener diode D5, and the drain of the third high-voltage NMOS transistor Q7 is connected to the OUT port.

[0016] The protection circuit B has the same structure as the protection circuit A; the VDDE port of the protection circuit B is connected to the OUT port; the VSS port of the protection circuit B is shorted to the VSSE port of the protection circuit B, and is connected to the VSS port of the core circuit.

[0017] Preferably, the protection circuit A and the protection circuit B each include: a high-side reverse connection protection circuit and an overvoltage protection circuit.

[0018] Preferably, the high-side reverse connection protection circuit includes: a high-voltage PMOS transistor Q1, a first Zener diode D1, and a first resistor R1;

[0019] The gate of the high-voltage PMOS transistor Q1 is connected to the anode of the first Zener diode D1 and the first resistor R1; the source of the high-voltage PMOS transistor Q1 is connected to the cathode of the first Zener diode D1; the drain of the high-voltage PMOS transistor Q1 is connected to the VDDE port of the protection circuit; and the first resistor R1 is connected to the VSSE port of the protection circuit.

[0020] Preferably, the overvoltage protection circuit includes: a high-voltage PNP transistor Q2, a first high-voltage NMOS transistor Q3, a second Zener diode D2, a third Zener diode D3, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0021] The second resistor R2, the emitter of the high-voltage PNP transistor Q2, the cathode of the third Zener diode D3, and the source of the first high-voltage NMOS transistor Q3 are connected together.

[0022] The cathodes of the second resistor R2, the third resistor R3, and the second Zener diode D2 are connected together;

[0023] The drain of the first high-voltage NMOS transistor Q3 is connected to the VDD port of the protection circuit.

[0024] The gate of the first high-voltage NMOS transistor Q3, the anode of the third Zener diode D3, the collector of the high-voltage PNP transistor Q2, and the fourth resistor R4 are connected together.

[0025] The base of the high-voltage PNP transistor Q2 is connected to the third resistor R3;

[0026] The anode of the second Zener diode D2 and the fourth resistor R4 are connected to the VSS port of the protection circuit.

[0027] This utility model provides an overvoltage, reverse connection, and short circuit protection circuit, which for the first time publicly solves the overvoltage, reverse connection, and short circuit protection problem between the output (OUT terminal), the power supply (external power supply VDDE port), and ground (external power supply VSSE port) of a high-reliability chip. Specifically, it addresses the overvoltage, reverse connection, and short circuit protection problem between the OUT, VDDE, and VSSE ports under six common operating conditions (but not limited to) in the target application. It can protect the chip when overvoltage, reverse connection, or short circuit occurs between the OUT, VDDE, and VSSE ports, with a maximum protection voltage of ±40V or higher. It features high reliability, basically covers all operating conditions, and can well meet the target application requirements. This utility model has four advantages: simple circuit, comprehensive functions, high reliability, and high withstand voltage. Its comprehensive functions are applicable not only to conventional high voltage and reverse connection protection for the VDDE and VSSE ports, but also to high voltage, reverse connection, and short circuit protection for the VDDE, VSSE, and OUT ports. This invention, combining conventional BCD technology, provides overvoltage, reverse connection, and short-circuit protection with a maximum protection voltage of ±40V or higher, exhibiting high voltage withstand capability. This invention expands the application scenarios of ordinary chips, particularly effectively solving target application problems; it not only significantly improves integration but also substantially reduces costs, thus driving the development of related industries. Attached Figure Description

[0028] Figure 1 This is a circuit diagram of an overvoltage reverse connection short circuit protection circuit provided by this utility model;

[0029] Figure 2 This is a circuit diagram of protection circuit A and protection circuit B provided by this utility model. Detailed Implementation

[0030] To make the technical problems solved by this utility model, the technical solutions adopted, and the technical effects achieved clearer, this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for explaining this utility model and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this utility model are shown in the accompanying drawings, not all of them.

[0031] like Figure 1 As shown in the figure, an overvoltage reverse connection short circuit protection circuit provided by this utility model embodiment includes: a low-side reverse connection protection circuit, a protection circuit A, a protected circuit, a protection circuit C, and a protection circuit B.

[0032] The external power supply VDDE port is the chip's external power supply port, connected to an external input power signal; the external power supply VSSE port is the chip's external power ground port, connected to an external input ground signal; the OUT port is the chip's output port, used to output analog or digital signals. The VDD port is the internal power supply port; the VSS port is the internal power ground port. The external power supply VDDE port and external power supply VSSE port are the input ports of this invention's overvoltage reverse connection short circuit protection circuit, and the OUT port is the output port of this invention's overvoltage reverse connection short circuit protection circuit.

[0033] VDDE signal is the external power supply signal; VSSE signal is the external power supply ground signal; VDD signal is the internal power supply signal; VSS signal is the internal power supply ground signal; VDDE signal is input from the external power supply VDDE port, and VSSE signal is input from the external power supply VSSE port; VDD and VSS signals are generated by protection circuit A and used by the protected circuit, protection circuit C, and protection circuit B.

[0034] The low-side reverse connection protection circuit includes: a second high-voltage NMOS transistor Q4, a fourth Zener diode D4, and a fifth resistor R5; the gate of the second high-voltage NMOS transistor Q4 is connected to the cathode of the fourth Zener diode D4, the source of the second high-voltage NMOS transistor Q4 is connected to the anode of the fourth Zener diode D4, and the drain of the second high-voltage NMOS transistor Q4 is connected to the external power supply VSSE port, which receives the external power supply VSSE signal; one end of the fifth resistor R5 is connected to the gate of the second high-voltage NMOS transistor Q4, and the other end is connected to the external power supply VDDE port. The external power supply VSSE port receives the external power supply VSSE signal, and the external power supply VDDE port receives the external power supply VDDE signal.

[0035] The low-side reverse connection protection circuit turns off the second high-voltage NMOS transistor Q4 when the VSSE signal is higher than the VDDE signal. Together with other protection circuits, the low-side reverse connection protection circuit provides reverse connection protection. During normal operation, the second high-voltage NMOS transistor Q4 is turned on.

[0036] The VDDE port of protection circuit A is connected to the external power supply VDDE port, and the VSSE port of protection circuit A is connected to the source of the second high-voltage NMOS transistor Q4 of the low-side reverse connection protection circuit. The VDD and VSS ports of protection circuit A are respectively connected to the protected circuit; that is, the VDD port of protection circuit A is connected to the internal power supply VDD signal, and the VSS port of protection circuit A is connected to the internal power supply VSS signal. The VDD and VSS ports of protection circuit A provide power and ground signals to the protected circuit, respectively. Protection circuit A converts the external power supply VDDE and VSSE signals into internal power supply VDD and VSS signals, supplying power to protection circuits C and B.

[0037] like Figure 2 As shown, the protection circuit A includes: a high-side reverse connection protection circuit and an overvoltage protection circuit.

[0038] The high-side reverse connection protection circuit includes: a high-voltage PMOS transistor Q1, a first Zener diode D1, and a first resistor R1. The gate of the high-voltage PMOS transistor Q1 is connected to the anode of the first Zener diode D1 and the first resistor R1; the source of the high-voltage PMOS transistor Q1 is connected to the cathode of the first Zener diode D1; and the drain of the high-voltage PMOS transistor Q1 is connected to the VDDE port of protection circuit A. The first resistor R1 is connected to the VSSE port of protection circuit A.

[0039] The overvoltage protection circuit includes: a high-voltage PNP transistor Q2, a first high-voltage NMOS transistor Q3, a second Zener diode D2, a third Zener diode D3, a second resistor R2, a third resistor R3, and a fourth resistor R4; the second resistor R2, the emitter of the high-voltage PNP transistor Q2, the cathode of the third Zener diode D3, and the source of the first high-voltage NMOS transistor Q3 are connected together. The second resistor R2, the third resistor R3, and the cathode of the second Zener diode D2 are connected together; the drain of the first high-voltage NMOS transistor Q3 is connected to the VDD port of protection circuit A; the gate of the first high-voltage NMOS transistor Q3, the anode of the third Zener diode D3, the collector of the high-voltage PNP transistor Q2, and the fourth resistor R4 are connected together; the base of the high-voltage PNP transistor Q2 is connected to the third resistor R3; the anode of the second Zener diode D2 and the fourth resistor R4 are connected to the VSS port of protection circuit A.

[0040] Protection circuit A provides overvoltage and reverse connection protection for the external power supply VDDE and VSSE ports. When the VSSE signal is higher than the VDDE signal, the high-voltage PMOS transistor Q1 is turned off. During normal operation, the high-voltage PMOS transistor Q1 in the high-side reverse connection protection circuit is turned on. When the VDDE signal is overvoltage, the second Zener diode D2 in the overvoltage protection circuit is turned on and in a voltage-regulating state, and the high-voltage PNP transistor Q2 is turned on, resulting in a sufficient voltage drop across the fourth resistor R4, which in turn turns off the first high-voltage NMOS transistor Q3, thus providing overvoltage protection. During normal operation, the second Zener diode D2 is turned off, the high-voltage PNP transistor Q2 is turned off, and the first high-voltage NMOS transistor Q3 is turned on.

[0041] The protected circuit includes a core circuit and an output stage circuit. The core circuit is the object for which this invention provides overvoltage, reverse connection, and short-circuit protection.

[0042] The output stage circuit includes a common PMOS transistor Q5 and a common NMOS transistor Q6; in most applications, the common PMOS transistor Q5 and the common NMOS transistor Q6 constitute the output stage of an operational amplifier. Internal power supply signals VDD and VSS power supply power the protected circuit.

[0043] The source of the ordinary PMOS transistor Q5 and the VDD port of the core circuit are connected to the VDD port of the protection circuit A, that is, the source of the ordinary PMOS transistor Q5 is connected to the internal power supply VDD signal; the gate of the ordinary PMOS transistor Q5 is connected to the core circuit; the drain of the ordinary PMOS transistor Q5 is connected to the protection circuit C, specifically the drain of the ordinary PMOS transistor Q5 is connected to the VDD port of the protection circuit B.

[0044] The source of the ordinary NMOS transistor Q6 and the VSS port of the core circuit are connected to the VSS port of the protection circuit A, that is, the source of the ordinary NMOS transistor Q6 is connected to the internal power supply VSS signal; the gate of the ordinary NMOS transistor Q6 is connected to the core circuit; the drain of the ordinary NMOS transistor Q6 is connected to the protection circuit C, specifically, the drain of the ordinary NMOS transistor Q6 is connected to the drain of the third high-voltage NMOS transistor Q7 in the protection circuit C.

[0045] The protection circuit C includes: a third high-voltage NMOS transistor Q7, a fifth Zener diode D5, and a sixth resistor R6;

[0046] One end of the sixth resistor R6 is connected to the VDD port of the core circuit, that is, one end of the sixth resistor R6 is connected to the internal power supply VDD signal, and the other end of the sixth resistor R6 is connected to the cathode of the fifth Zener diode D5; the anode of the fifth Zener diode D5 is connected to the VSS port of the core circuit, that is, the anode of the fifth Zener diode D5 is connected to the internal power supply VSS signal.

[0047] The gate of the third high-voltage NMOS transistor Q7 is connected to the cathode of the fifth Zener diode D5, and the drain of the third high-voltage NMOS transistor Q7 is connected to the OUT port.

[0048] The protection circuit C is used to isolate the OUT port from the protected circuit. The protection circuit C works together with other protection circuits. During normal operation, the third high-voltage NMOS transistor Q7 is turned on.

[0049] The protection circuit B has the same structure as protection circuit A, and protection circuit B also includes: a high-side reverse connection protection circuit and an overvoltage protection circuit. The specific structure is as follows: Figure 2 As shown, no further details are provided. The VDDE port of the protection circuit B is connected to the OUT port; the VSS port of the protection circuit B is shorted to the VSSE port of the protection circuit B, and is connected to the VSS port of the core circuit, that is, connected to the internal power supply VSS signal.

[0050] The working principle of the overvoltage reverse connection short circuit protection circuit provided by this utility model is as follows:

[0051] Operating Condition 1: Normal operating condition (external power supply VDDE port and external power supply VSSE port are at normal operating voltage, and the OUT port level is between external power supply VDDE port and external power supply VSSE port).

[0052] (1) Low-side reverse connection protection circuit: The second high-voltage NMOS transistor Q4 is turned on, the fourth Zener diode D4 is turned off, and no current flows through the fifth resistor R5. It is in normal working condition.

[0053] (2) Protection circuit A:

[0054] High-side reverse connection protection circuit: High-voltage PMOS transistor Q1 is turned on, first Zener diode D1 is turned off, and no current flows through first resistor R1. It is in normal operating condition.

[0055] Overvoltage protection circuit: The second Zener diode D2 is off, the first high-voltage NMOS transistor Q3 is off, no current flows through the second resistor R2, the third resistor R3, and the fourth resistor R4, the third Zener diode D3 is off, and the high-voltage NMOS transistor Q3 is on. The VDDE and VDD ports of protection circuit A are short-circuited, and the VSSE and VSS ports are short-circuited. It is in normal operating condition.

[0056] (3) Protection circuit B:

[0057] High-side reverse connection protection circuit: High-voltage PMOS transistor Q1 is turned on, first Zener diode D1 is turned off, and no current flows through first resistor R1. It is in normal operating condition.

[0058] Overvoltage protection circuit: The second Zener diode D2 is off, the first high-voltage NMOS transistor Q3 is off, no current flows through the second resistor R2, the third resistor R3, and the fourth resistor R4, the third Zener diode D3 is off, and the first high-voltage NMOS transistor Q3 is on. The VDDE port and VDD port of protection circuit B are short-circuited (i.e., the OUT port is short-circuited to the drain of the fifth PMOS transistor Q5). It is in normal operating condition.

[0059] (4) Protection circuit C: The third high-voltage NMOS transistor Q7 is turned on, the fifth Zener diode D5 is turned off, and no current flows through the seventh resistor R7. It is in normal working condition.

[0060] (5) Protected circuit: The drain of ordinary PMOS transistor Q5 and the drain of ordinary NMOS transistor Q6 are short-circuited through protection circuit B and the third high-voltage NMOS transistor Q7. It is in normal working condition.

[0061] Operating Condition 2: External power supply VDDE port and external power supply VSSE port (the voltage difference between the external power supply VDDE port and the external power supply VSSE port is greater than the normal operating voltage difference, resulting in overvoltage)

[0062] (1) Low-side reverse connection protection circuit: The second high-voltage NMOS transistor Q4 is turned on, the fourth Zener diode D4 is turned on and in a voltage-stabilized state, protecting the second high-voltage NMOS transistor Q4, and a small current flows through the fifth resistor R5. It is in a voltage-stabilized working state.

[0063] (2) Protection circuit A:

[0064] High-side reverse connection protection circuit: High-voltage PMOS transistor Q1 is turned on, first Zener diode D1 is turned on and in a regulated state, and a small current flows through first resistor R1. It is in regulated operating state.

[0065] Overvoltage protection circuit: The second Zener diode D2 is turned on, the first high-voltage NMOS transistor Q3 is turned on, a small current flows through the second resistor R2, the third resistor R3, and the fourth resistor R4, the third Zener diode D3 is turned off, and the first high-voltage NMOS transistor Q3 is turned off. The path between the VDDE and VDD ports of protection circuit A is cut off, and the VSSE and VSS ports are short-circuited. It is in high-voltage protection mode, and there is no overvoltage between the external power supply signals VDDE and VSS.

[0066] (3) Protection circuit B: Each port is not subjected to overvoltage.

[0067] (4) Protection circuit C: Each port is not subjected to overvoltage.

[0068] (4) Protected circuit: The circuit is not subjected to overvoltage.

[0069] Operating Condition 3: External power supply VDDE port and external power supply VSSE port are connected in reverse due to overvoltage (the voltage difference between the external power supply VDDE port and the external power supply VSSE port is greater than the normal operating voltage difference, resulting in overvoltage, and they are connected in reverse, that is, the external power supply VSSE port is higher than the external power supply VDDE port).

[0070] (1) Low-side reverse connection protection circuit: The second high-voltage NMOS transistor Q4 is turned off, the fourth Zener diode D4 is turned off, and no current flows through the fifth resistor R5. The path between the external power supply VSSE port and the external power supply VDDE port is cut off. It is in reverse connection protection mode. At this time, there is no overvoltage between the external power supply signals VDDE and VSSE.

[0071] (2) Protection circuit A: Each port is not subjected to overvoltage.

[0072] (3) Protection circuit B: Each port is not subjected to overvoltage.

[0073] (4) Protection circuit C: Each port is not subjected to overvoltage.

[0074] (5) Protected circuit: The circuit is not subjected to overvoltage.

[0075] Condition 4: Overvoltage between OUT port and external power supply VSSE port (the voltage difference between OUT port and external power supply VSSE port is greater than the normal operating voltage difference, resulting in overvoltage, and at the same time, the external power supply VDDE port is open).

[0076] (1) Low-side reverse connection protection circuit: The second high-voltage NMOS transistor Q4 is turned off, the fourth Zener diode D4 is turned off, and no current flows through the fifth resistor R5. The path between the VSSE port and the VSS port is cut off. It is in reverse connection protection mode. At this time, there is no overvoltage between the external power supply signal VDDE and the external power supply signal VSSE.

[0077] (2) Protection circuit A: Each port is not subjected to overvoltage.

[0078] (3) Protection circuit B:

[0079] High-side reverse connection protection circuit: High-voltage PMOS transistor Q1 is turned on, first Zener diode D1 is turned on and in a voltage-regulating state, and a small current flows through first short-circuit resistor R1. It is in voltage-regulating operation.

[0080] Overvoltage protection circuit: The second Zener diode D2 is turned on, the first high-voltage NMOS transistor Q3 is turned on, a small current flows through the second resistor R2, the third resistor R3, and the fourth resistor R4, the third Zener diode D3 is turned off, and the first high-voltage NMOS transistor Q3 is turned off. The path between the VDDE port and the VDD port of protection circuit B is cut off. In the high-voltage protection working state, the path from the OUT port to the ordinary PMOS transistor Q5 is cut off, and there is no overvoltage between the internal power supply signal VDD and the internal power supply signal VSS.

[0081] (4) Protection circuit C: The third high-voltage NMOS transistor Q7 is turned off, the fifth Zener diode D5 is turned off, and no current flows through the sixth resistor R6. The path from the OUT port to the ordinary NMOS transistor Q6 is cut off.

[0082] (5) Protected circuit: The circuit is not subjected to overvoltage.

[0083] Condition 5: Overvoltage at the external power supply VDDE port and the external power supply VSSE port, and short circuit between the OUT port and the external power supply VDDE port (the voltage difference between the OUT port and the external power supply VSSE port is greater than the normal operating voltage difference, resulting in overvoltage, and at the same time, the OUT port and the external power supply VDDE port are short-circuited).

[0084] (1) Low-side reverse connection protection circuit: The second high-voltage NMOS transistor Q4 is turned on, the fourth Zener diode D4 is turned on and in a voltage-stabilized state, protecting the second high-voltage NMOS transistor Q4, and a small current flows through the fifth resistor R5. It is in a voltage-stabilized working state.

[0085] (2) Protection circuit A:

[0086] High-side reverse connection protection circuit: High-voltage PMOS transistor Q1 is turned on, first Zener diode D1 is turned on and in a regulated state, and a small current flows through first resistor R1. It is in regulated operating state.

[0087] Overvoltage protection circuit: The second Zener diode D2 is turned on, the first high-voltage NMOS transistor Q3 is turned on, a small current flows through the second resistor R2, the third resistor R3, and the fourth resistor R4, the third Zener diode D3 is turned off, and the first high-voltage NMOS transistor Q3 is turned off. The path between the VDDE and VDD ports of protection circuit A is cut off, and the external power supply signal VSSE and the internal power supply signal VSS are short-circuited. It is in high-voltage protection mode, and there is no overvoltage between the internal power supply signals VDD and VSS at this time.

[0088] (3) Protection circuit B: The working state is similar to that of protection circuit A, but the path from the OUT port to the ordinary PMOS transistor Q5 is cut off.

[0089] (4) Protection circuit C: The third high-voltage NMOS transistor Q7 is turned off, the fifth Zener diode D5 is turned off, and no current flows through R6. The path from the OUT port to the ordinary NMOS transistor Q6 is cut off.

[0090] (5) Protected circuit: The circuit is not subjected to overvoltage.

[0091] Condition 6: External power supply VSSE port is reverse-connected with overvoltage, and OUT port is short-circuited with external power supply VSSE port (the voltage difference between external power supply VDDE port and external power supply VSSE port is greater than the normal operating voltage difference, resulting in overvoltage, and the reverse connection means that external power supply VSSE port is higher than external power supply VDDE port. At the same time, OUT port is short-circuited with external power supply VSSE port).

[0092] (1) Low-side reverse connection protection circuit: The second high-voltage NMOS transistor Q4 is turned off, the fourth Zener diode D4 is turned off, and no current flows through the fifth resistor R5. The path between the external power supply signal VSSE and the internal power supply signal VSS is cut off. It is in reverse connection protection mode. At this time, there is no overvoltage between the internal power supply signal VDD and the internal power supply signal VSS.

[0093] (2) Protection circuit A: Each port is not subjected to overvoltage.

[0094] (3) Protection circuit B:

[0095] High-side reverse connection protection circuit: High-voltage PMOS transistor Q1 is turned on, first Zener diode D1 is turned on and in a regulated state, and a small current flows through first resistor R1. It is in regulated operating state.

[0096] Overvoltage protection circuit: The second Zener diode D2 is turned on, the first high-voltage NMOS transistor Q3 is turned on, a small current flows through the second resistor R2, the third resistor R3, and the fourth resistor R4, the third Zener diode D3 is turned off, and the first high-voltage NMOS transistor Q3 is turned off. The path between the VDDE port and the VDD port of protection circuit B is cut off. It is in high-voltage protection mode. At this time, the path from the OUT port to Q5 is cut off.

[0097] (4) Protection circuit C: The third high-voltage NMOS transistor Q7 is turned off, the fifth Zener diode D5 is turned off, and no current flows through the sixth resistor R6. The path from the OUT port to the ordinary NMOS transistor Q6 is cut off.

[0098] (5) Protected circuit: The circuit is not subjected to overvoltage.

[0099] Other operating conditions: Except for condition 1, which is the normal operating condition, the other five of the above six operating conditions basically cover the main high-voltage reverse connection and short circuit conditions of the external power supply VDDE port, external power supply VSSE port, and OUT port. In addition, the circuit can also operate in various other high-voltage reverse connection and short circuit conditions, providing excellent protection. These will not be elaborated upon here.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications to the technical solutions described in the foregoing embodiments, or equivalent substitutions for some or all of the technical features, do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An overvoltage reverse connection short circuit protection circuit, characterized by comprising: include: Low-side reverse connection protection circuit, protection circuit A, protected circuit, protection circuit C and protection circuit B; The low-side reverse connection protection circuit includes: a second high-voltage NMOS transistor Q4, a fourth Zener diode D4, and a fifth resistor R5; the gate of the second high-voltage NMOS transistor Q4 is connected to the cathode of the fourth Zener diode D4, the source of the second high-voltage NMOS transistor Q4 is connected to the anode of the fourth Zener diode D4, and the drain of the second high-voltage NMOS transistor Q4 is connected to the external power supply VSSE port; one end of the fifth resistor R5 is connected to the gate of the second high-voltage NMOS transistor Q4, and the other end is connected to the external power supply VDDE port; The VDDE port of the protection circuit A is connected to the external power supply VDDE port, and the VSSE port of the protection circuit A is connected to the source of the second high-voltage NMOS transistor Q4 of the low-side reverse connection protection circuit; the VDD port and VSS port of the protection circuit A are respectively connected to the protected circuit, providing power and ground signals to the protected circuit respectively. The protected circuit includes: a core circuit and an output stage circuit; The output stage circuit includes: a general-purpose PMOS transistor Q5 and a general-purpose NMOS transistor Q6; The source of the ordinary PMOS transistor Q5 and the VDD port of the core circuit are connected to the VDD port of the protection circuit A; the gate of the ordinary PMOS transistor Q5 is connected to the core circuit; and the drain of the ordinary PMOS transistor Q5 is connected to the protection circuit C. The source of the ordinary NMOS transistor Q6, the VSS port of the core circuit, and the VSS port of the protection circuit A are connected; the gate of the ordinary NMOS transistor Q6 is connected to the core circuit; and the drain of the ordinary NMOS transistor Q6 is connected to the protection circuit C. The protection circuit C includes: a third high-voltage NMOS transistor Q7, a fifth Zener diode D5, and a sixth resistor R6; One end of the sixth resistor R6 is connected to the VDD port of the core circuit, and the other end is connected to the cathode of the fifth Zener diode D5; the anode of the fifth Zener diode D5 is connected to the VSS port of the core circuit. The gate of the third high-voltage NMOS transistor Q7 is connected to the cathode of the fifth Zener diode D5, and the drain of the third high-voltage NMOS transistor Q7 is connected to the OUT port. The protection circuit B has the same structure as the protection circuit A; the VDDE port of the protection circuit B is connected to the OUT port; the VSS port of the protection circuit B is shorted to the VSSE port of the protection circuit B, and is connected to the VSS port of the core circuit.

2. The overvoltage reverse connection short circuit protection circuit according to claim 1, characterized by The protection circuit A and protection circuit B respectively include: a high-side reverse connection protection circuit and an overvoltage protection circuit.

3. The overvoltage reverse connection short circuit protection circuit according to claim 2, characterized in that, The high-side reverse connection protection circuit includes: a high-voltage PMOS transistor Q1, a first Zener diode D1, and a first resistor R1; The gate of the high-voltage PMOS transistor Q1 is connected to the anode of the first Zener diode D1 and the first resistor R1; the source of the high-voltage PMOS transistor Q1 is connected to the cathode of the first Zener diode D1; the drain of the high-voltage PMOS transistor Q1 is connected to the VDDE port of the protection circuit; and the first resistor R1 is connected to the VSSE port of the protection circuit.

4. The overvoltage reverse connection short circuit protection circuit according to claim 3, characterized by The overvoltage protection circuit includes: a high-voltage PNP transistor Q2, a first high-voltage NMOS transistor Q3, a second Zener diode D2, a third Zener diode D3, a second resistor R2, a third resistor R3, and a fourth resistor R4. The second resistor R2, the emitter of the high-voltage PNP transistor Q2, the cathode of the third Zener diode D3, and the source of the first high-voltage NMOS transistor Q3 are connected together. The cathodes of the second resistor R2, the third resistor R3, and the second Zener diode D2 are connected together; The drain of the first high-voltage NMOS transistor Q3 is connected to the VDD port of the protection circuit. The gate of the first high-voltage NMOS transistor Q3, the anode of the third Zener diode D3, the collector of the high-voltage PNP transistor Q2, and the fourth resistor R4 are connected together. The base of the high-voltage PNP transistor Q2 is connected to the third resistor R3; The anode of the second Zener diode D2 and the fourth resistor R4 are connected to the VSS port of the protection circuit.

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