Quartz resonant micro-force sensing signal processing circuit

Abstract

The utility model relates to a quartz resonant type micro force sensing signal processing circuit, include: input port processing circuit is used for receiving the resonant signal of micro force sensor output, frequency signal processing circuit is used for converting the resonant signal to intermediate frequency signal and carries out analog shaping, and output processing signal, frequency solution circuit is used for extracting the base frequency signal in processing signal, first memory is used for storing frequency division coefficient and frequency multiplication coefficient, reconfigurable frequency divider is used for generating the frequency division signal of base frequency signal based on frequency division coefficient, digital frequency multiplier is used for generating the frequency multiplication signal of base frequency signal according to frequency multiplication coefficient, the utility model can convert the tiny frequency offset of quartz resonator accurately into real -time digital frequency signal output, is applicable to static high accuracy or dynamic multi -parameter synchronous micro force precision measurement scene.

Description

Technical Field

[0001] This utility model relates to the field of high-precision mechanical sensing technology, and in particular to a quartz resonant micro-force sensing signal processing circuit. Background Technology

[0002] Quartz resonant mechanical sensors, as core components for high-precision measurement, are based on the resonant frequency shift characteristics of quartz crystals under external forces. This principle gives them irreplaceable advantages in fields such as industrial weighing, aero-engine torque monitoring, and precision mechanical pressure detection. However, with the increasing demands of modern measurement systems for multi-parameter fusion, real-time performance, and intelligence, the limitations of traditional processing circuits are becoming increasingly apparent. Existing solutions generally employ analog frequency divider / multiplier circuits, whose inherent temperature drift and nonlinearity, as well as the effects of line noise and phase distortion, restrict the measurement accuracy of the system over a wide temperature range or under dynamic loads.

[0003] More importantly, traditional technologies have limitations in utilizing frequency information. The harmonic components generated by the excitation of a quartz resonator contain rich mechanical response characteristics, which can effectively compensate for nonlinear errors or environmental disturbances in fundamental frequency measurements. However, existing systems, limited by hardware resources and processing logic, typically only extract the fundamental frequency signal for counting output, forcing higher-order harmonic information to be passively filtered out, resulting in a lack of data dimensions.

[0004] Traditional circuits are built using hard-wired logic, and their frequency division and multiplication coefficients cannot be changed once determined, making them difficult to adapt to sensors of different ranges or types. More importantly, their temperature compensation mechanisms are usually external, independent units separate from the core frequency processing circuit, resulting in delays in the transmission of compensation signals and making it difficult to achieve real-time and accurate compensation for temperature drift in the core circuit. In addition, while pure analog frequency division schemes are cost-effective, their response delays make them difficult to meet the requirements for multi-channel synchronous output. Summary of the Invention

[0005] The technical problem to be solved by this utility model is to provide a quartz resonant micro-force sensing signal processing circuit that can accurately convert the tiny frequency deviation of the quartz resonator into a real-time digital frequency signal output.

[0006] The technical solution adopted by this utility model to solve its technical problem is: to provide a quartz resonant micro-force sensing signal processing circuit, including:

[0007] The input port processing circuit is electrically connected to the quartz resonant micro-force sensor and is used to receive the resonant signal output by the micro-force sensor.

[0008] A frequency signal processing circuit, electrically connected to the input port processing circuit, is used to convert the resonant signal into an intermediate frequency signal, perform analog shaping, and output a processed signal.

[0009] A frequency calculation circuit, electrically connected to the frequency signal processing circuit, is used to extract the digital baseband signal from the processed signal;

[0010] The first memory is used to store the frequency division coefficient and the frequency multiplication coefficient;

[0011] A reconfigurable frequency divider, electrically connected to the frequency calculation circuit and the first memory, is used to generate a frequency-divided signal of the digital baseband signal based on the frequency division coefficient;

[0012] A digital frequency multiplier, electrically connected to the frequency calculation circuit and the first memory, is used to generate a multiplied signal of the digital base frequency signal based on the multiplication factor.

[0013] Furthermore, it also includes a temperature compensation circuit, which includes a temperature sensor, a first analog-to-digital converter, a second memory, and a digital-to-analog converter connected in sequence. The temperature sensor is used to detect the temperature in real time and output an analog voltage signal. The first analog-to-digital converter is used to convert the analog voltage signal into a digital signal. The second memory obtains the temperature compensation value based on the digital signal addressing. The digital-to-analog converter generates the bias voltage of the reconfigurable frequency divider and the digital frequency multiplier according to the temperature compensation value.

[0014] Furthermore, the reconfigurable frequency divider includes multiple programmable frequency divider units connected in parallel. Each programmable frequency divider unit is electrically connected to the frequency calculation circuit and the first memory, respectively, and is used to obtain its respective frequency division coefficient from the first memory, synchronously generate multiple frequency division signals, and output them in parallel.

[0015] Furthermore, the digital frequency multiplier includes multiple digital frequency multiplier units connected in parallel. Each digital frequency multiplier unit is electrically connected to the frequency calculation circuit and the first memory, respectively, and is used to obtain its respective frequency multiplication coefficient from the first memory, synchronously generate multiple frequency multiplication signals, and output them in parallel.

[0016] Furthermore, the frequency calculation circuit includes a second analog-to-digital converter and a phase-locked loop connected to each other. The second analog-to-digital converter is used to convert the processed signal into a digital processed signal, and the phase-locked loop is used to lock the base frequency signal of the digital processed signal and output the digital base frequency signal.

[0017] Furthermore, the input port processing circuit includes an anti-static resistor array and a crystal oscillator. The anti-static resistor array is electrically connected to a quartz resonant micro-force sensor to receive the resonant signal output by the micro-force sensor. The crystal oscillator is electrically connected to the frequency signal processing circuit, the reconfigurable frequency divider, and the digital frequency multiplier to generate a clock signal.

[0018] Furthermore, the antistatic resistor array includes multiple sets of thin-film resistors connected in series.

[0019] Furthermore, the frequency signal processing circuit includes a mixer circuit, an amplifier circuit, a filter circuit, and a shaping circuit connected in sequence.

[0020] Furthermore, the shaping circuit is a Schmitt trigger.

[0021] Furthermore, it also includes an output port processing circuit, which is electrically connected to the frequency calculation circuit, the reconfigurable frequency divider, and the digital frequency multiplier, respectively, and is used to package the digital baseband signal, the frequency divider signal, and the frequency multiplier signal into a standardized data transmission frame.

[0022] Furthermore, it also includes a human-computer interaction unit, which is electrically connected to the frequency calculation circuit, the reconfigurable frequency divider, and the digital frequency multiplier, respectively, and is used to respond to user commands to cause the output port processing circuit to output the digital baseband signal, or to output the digital baseband signal, the frequency divider signal, and the frequency multiplier signal.

[0023] Beneficial effects

[0024] Due to the adoption of the above technical solutions, this utility model has the following advantages and positive effects compared with the prior art: This utility model converts the resonant signal output by the micro-force sensor to an intermediate frequency through a mixer circuit, amplifies, filters, and shapes it, and then extracts the digital fundamental frequency signal through a frequency calculation circuit. Then, based on the stored division coefficient and harmonic coefficient, it generates division and harmonic signals, which can simultaneously capture and output the fundamental frequency, division, and harmonic signals. This allows the system to explore the value of harmonics and obtain more accurate signal data, thereby improving the measurement accuracy of the quartz resonant mechanical sensor. This utility model designs a temperature compensation circuit, which uses hardware logic to quickly look up the compensation value based on the real-time detected temperature, thereby adjusting the bias voltage of the division and harmonic multipliers. This enables fast and accurate temperature compensation and suppresses the temperature drift problem of the division and harmonic multipliers. This utility model builds a human-computer interaction platform to support dynamic switching of measurement modes and data visualization. Attached Figure Description

[0025] Figure 1 This is a structural schematic diagram of an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the temperature compensation circuit introduced in this embodiment of the utility model;

[0027] Figure 3 This is a schematic diagram of the structure of a preferred embodiment of the present invention. Detailed Implementation

[0028] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0029] The embodiments of this utility model relate to a quartz resonant micro-force sensing signal processing circuit, such as... Figure 1 As shown, it includes:

[0030] The input port processing circuit is electrically connected to the quartz resonant micro-force sensor and is used to receive the high-frequency resonant signal output by the sensor.

[0031] The frequency signal processing circuit, which is electrically connected to the input port processing circuit, is used to convert the high-frequency resonant signal into an intermediate frequency signal by frequency mixing and down-conversion, and then perform analog shaping to output the processed signal.

[0032] The data processing and core control circuit is used to build a flexible and configurable multi-channel frequency synthesis architecture, processing the baseband signal (f0) to obtain the baseband signal (f0) and the frequency divider signal (f0 / 2). n The three frequency signals include: ) and the harmonic signal (k·f0), specifically:

[0033] The frequency calculation circuit is electrically connected to the frequency signal processing circuit and is used to extract the fundamental frequency signal from the processed signal.

[0034] The first memory is used to store the frequency division coefficient and the frequency multiplication coefficient;

[0035] A reconfigurable frequency divider is electrically connected to a frequency calculation circuit and a first memory, respectively, and is used to generate a frequency-divided signal based on the frequency division coefficient;

[0036] The digital frequency multiplier is electrically connected to the frequency calculation circuit and the first memory, respectively, and is used to generate a frequency multiplier signal based on the frequency multiplication coefficient.

[0037] In some preferred embodiments, a temperature compensation circuit can also be designed to compensate for disturbances caused by ambient temperature factors. For example... Figure 2As shown, the temperature compensation circuit can be implemented using a temperature sensor, a first analog-to-digital converter (ADC), a second memory, and a digital-to-analog converter (DAC) connected in sequence. The temperature sensor detects the ambient temperature of the circuit in real time and outputs a corresponding analog voltage signal. The first ADC converts this analog voltage signal into a digitized temperature value. The second memory (essentially a lookup table) uses this digitized temperature value as an address to retrieve a pre-calibrated digital compensation code used to correct performance drift at that temperature. Finally, the DAC receives this digital compensation code and converts it into a precise analog DC voltage. This analog DC voltage is directly used as the bias voltage for the reconfigurable frequency divider and digital frequency multiplier, adjusting the operating point of their internal circuits in real time to achieve precise compensation for temperature drift.

[0038] More specifically, the input port processing circuit can be implemented using an anti-static resistor array and a crystal oscillator. The anti-static resistor array can consist of multiple sets of thin-film resistors connected in series in the sensor input path, electrically connected to the quartz resonant micro-force sensor, and used to receive the high-frequency resonant signal output by the micro-force sensor. The crystal oscillator generates a stable local oscillation frequency, which serves as the system clock for timing circuits such as the mixer, reconfigurable frequency divider, and digital frequency multiplier. When the first and second memories use synchronous registers based on timing logic, this circuit also provides the clock signal.

[0039] The frequency signal processing circuit can be implemented by sequentially connecting a mixer circuit, an amplifier circuit, a filter circuit, and a shaping circuit. The mixer circuit can be a differential mixer circuit, which down-converts the MHz-level resonant signal to the hundreds of kHz level after mixing with the local oscillation signal; the amplifier circuit has a gain of 2 to 10 times; and the filter circuit includes a set of second-order Butterworth low-pass filters with a cutoff frequency of 300 kHz to 500 kHz.

[0040] The frequency calculation circuit can be implemented using a second analog-to-digital converter (ADC), a synchronous counter, and a phase-locked loop (PLL). The second ADC converts the processed signal into a discrete digital signal. The PLL, connected to the second ADC, locks the center frequency of this discrete digital signal and outputs a cleaned-up clock signal (i.e., the digital baseband signal) with the same frequency but significantly reduced jitter and phase noise. The synchronous counter, electrically connected to the PLL, counts the pulses of the cleaned-up clock signal within a precise time reference provided by the system; the final count result is the frequency value of the digital baseband signal (i.e., the digital baseband).

[0041] The reconfigurable frequency divider can employ a programmable frequency divider circuit based on a JK flip-flop chain, with the division ratio (i.e., the division factor) configured via a first memory. The digital frequency multiplier can employ a frequency multiplier circuit comprising a delay-locked loop and logic gates, with the multiplication ratio (i.e., the multiplication factor) configured via a first memory. The frequency divider and multiplier generate the divided signal f0 / 2 using dynamically set division factor n and multiplication factor k, respectively. n And the frequency multiplication signal k·f0, where n and k are configurable integers.

[0042] Specifically, a reconfigurable frequency divider may include multiple programmable frequency divider units connected in parallel, each of which (e.g., a circuit based on a JK flip-flop chain) is electrically connected to a first memory. During operation, these frequency divider units can load their own independent division coefficients (n1, n2, ...) from the first memory in parallel. All frequency divider units receive a digital baseband signal as input, thereby synchronously and in parallel generating multiple different divided signals (e.g., n1 divided signal, n2 divided signal, etc. of the baseband signal).

[0043] Similarly, a digital frequency multiplier can include multiple digital frequency multiplier units connected in parallel (e.g., a circuit combining a delay phase-locked loop and logic gates), each of which can be configured with its own independent frequency multiplication coefficient (k1, k2, ...). They also uniformly receive the digital baseband signal, thereby synchronously and in parallel generating multiple different frequency multiplied signals (e.g., k1 multiplied signal, k2 multiplied signal, etc. of the baseband signal).

[0044] Through this parallel array structure, this circuit can expand the fundamental frequency signal into a signal group containing multiple harmonic components in real time, providing a multi-dimensional data foundation for subsequent signal packaging and high-precision analysis, which is something that a single frequency divider and multiplier cannot achieve.

[0045] In some preferred embodiments, an output port processing circuit is also included. The output port processing circuit is electrically connected to the frequency calculation circuit, the reconfigurable frequency divider, and the digital frequency multiplier, respectively, and is used to package the base frequency signal, the frequency division signal, and the frequency multiplier signal into a standardized data transmission frame.

[0046] In addition, it can be connected to a digital display screen with human-computer interaction, and the output mode can be selected by buttons: including static high-precision mode (output only f0) or dynamic analysis mode (synchronously output base frequency signal f0 and frequency divider signal f0 / 2). n The digital display shows the current output mode and the real-time frequency change value. The digital base frequency is obtained by counting with a synchronous counter. Its division and multiplication can be obtained by counting the corresponding division and multiplication signals with a synchronous counter, or they can be directly calculated using the division and multiplication coefficients.

[0047] like Figure 3 The image shown is a preferred embodiment 1 of this implementation.

[0048] It includes input port processing circuit, frequency signal processing circuit, data processing and core control circuit, output port processing circuit, human-machine interaction unit and power supply management unit.

[0049] This embodiment describes the core circuit for back-end signal processing of a quartz resonant mechanical sensor. The input port processing circuit receives and converts the original high-frequency resonant signal output by the sensor using electronic signal processing. This signal is then converted to an intermediate frequency (IF) signal via frequency down-conversion after mixing. This IF signal subsequently enters the frequency signal processing circuit, where it is amplified, filtered, and Schmitt trigger shaped into a regular square wave signal. This regularized signal is then input to the data processing and core control circuit. The circuit employs a programmable frequency divider and a digital frequency multiplier constructed using hard-wired digital logic circuitry. The division factor (n) and multiplication factor (k) are dynamically set via physical configuration registers, simultaneously generating the divided frequency signal (f0 / 2). n The generated signals consist of three frequency signals: a frequency multiplier (k·f0) and a frequency harmonic (k·f0). These signals drive the output port processing circuit via SPI / I... 2 The S-interface synchronously outputs real-time digital frequency values ​​and encapsulates them into standardized transmission frames. The human-machine interface unit supports selection via buttons for either a static high-precision mode (outputting only f0) or a dynamic analysis mode (synchronously outputting three signals), and displays the frequency information visually on the LCD screen. The power management structure provides multi-stage voltage regulation (1.2V to 5V) to power various circuit units and sensors, and utilizes a multi-stage π-type filter network to achieve a ripple rejection ratio >80dB, ensuring stable system operation.

[0050] Through this embodiment, the minute frequency shift corresponding to the minute mechanical quantity change of the quartz resonator can be accurately extracted, calculated and output, and its signal processing accuracy can meet the requirements of high-sensitivity mechanical sensing.

[0051] This embodiment specifically includes: an input port processing circuit 101, a frequency signal processing circuit 102, a data processing and core control circuit 103, an output port processing circuit 104, a human-machine interaction unit 105, and a power management unit 106. The input port processing circuit 101 receives the high-frequency resonant signal output from the sensor and converts it into an intermediate frequency signal through mixing and down-conversion. The frequency signal processing circuit 102 includes an amplification circuit, a filtering circuit, and a shaping circuit. After filtering and amplifying the intermediate frequency signal, it is shaped and output via a Schmitt trigger. The data processing and core control circuit 103 processes the fundamental frequency signal (f0) using a flexible and configurable multi-channel frequency synthesis architecture to obtain the fundamental frequency signal (f0) and the frequency division signal (f0 / 2). nThe system outputs three frequency signals: k, f0, and k-frequency multiplier (k / f0), which drive the output port processing circuit 104 to synchronously output the real-time digital frequency of each signal. The human-machine interface unit 105 supports LCD digital display output of visualized frequency information, and the power supply management unit 106 provides multi-stage voltage regulation and multi-stage power supply decoupling.

[0052] In this embodiment, the input port processing circuit 101 includes:

[0053] An anti-static resistor array consists of multiple sets of thin-film resistors connected in series in the sensor input path;

[0054] A crystal oscillator generates a stable local oscillation frequency, which serves as the system clock for use by the mixer circuit and other timing circuits.

[0055] The frequency signal processing circuit 102 includes:

[0056] Differential mixer circuits mix and down-convert MHz-level resonant signals with local oscillation signals to the hundreds of kHz level;

[0057] The amplifier circuit can achieve a gain of 2 to 10 times.

[0058] The filtering circuit includes a set of second-order Butterworth low-pass filters with a cutoff frequency of 300kHz to 500kHz.

[0059] Data processing and core control circuit 103 The data processing and core control circuit includes:

[0060] The hard-wired frequency calculation circuit consists of a multi-channel PLL circuit and a 32-bit synchronous counter.

[0061] A reconfigurable frequency divider, a programmable frequency divider circuit based on a JK flip-flop chain, with the division ratio configured via a physical register;

[0062] A digital frequency multiplier, comprising a frequency multiplier circuit synthesized from a delay phase-locked loop and logic gates;

[0063] The temperature compensation circuit uses the analog voltage output from the temperature sensor, which is converted by an ADC and used as an address signal to access a lookup table in an erasable programmable read-only memory. The compensation value output from the lookup table directly adjusts the bias voltage of the frequency divider / multiplier circuit to achieve temperature compensation.

[0064] The frequency divider and frequency multiplier generate the divided signal f0 / 2 by dynamically setting the division factor n and multiplication factor k, respectively. n and the frequency multiplication signal k / f0, where n and k are configurable integers.

[0065] The output port processing circuit 104 includes:

[0066] SPI / I 2S-interface, synchronously outputs three digital frequency values;

[0067] The data encapsulation protocol stack packages the baseband signal, frequency divider signal, and frequency multiplier signal into standardized transmission frames, supporting transparent transmission of RS485 / CAN bus.

[0068] The human-machine interface unit 105 allows selection of the output mode via buttons: static high-precision mode (outputs only f0) or dynamic analysis mode (synchronously outputs the base frequency signal f0 and the frequency divider signal f0 / 2). n The digital display shows the current output mode and the real-time frequency change value, along with the frequency multiplier signal k·f0.

[0069] The power management unit 106 is used to perform multi-stage voltage regulation, providing the core operating voltage (1.2V to 5V) for each unit of the circuit, and at the same time providing voltage output to power the sensor; a multi-stage π-type filter network achieves a ripple rejection ratio of >80dB.

[0070] The entire processing flow includes:

[0071] The frequency signal of the sensor is transmitted from the input terminal of the anti-static resistor array in the input port processing circuit 101 to the processing circuit.

[0072] First, the high-frequency signal is processed into an intermediate-frequency signal by the mixing circuit in the frequency signal processing circuit 102. Then, it passes through the amplification and filtering circuit in this circuit, where the signal amplitude is amplified by 2-10 times and high-frequency noise is filtered out. Finally, it passes through the rectifier circuit, where the signal is processed into a square wave signal with a duty cycle of 50%-60%.

[0073] The square wave signal then enters from the input terminal of the 103 data processing and core control circuit. After passing through the ADC circuit, the analog signal is converted into a digital signal and passed to the counter. The base frequency is then locked by the phase-locked loop (PLL) circuit. The base frequency is then passed to the programmable divider and digital multiplier. The division factor (n) and multiplication factor (k) are dynamically set through the physical configuration register, resulting in the divided signal (f0 / 2). n ) and the frequency multiplier signal (k·f0), where n and k are configurable integers;

[0074] The analog voltage output by the temperature detection unit is converted by the ADC and used as an address signal to access the lookup table in the erasable programmable read-only memory. The compensation value output by the lookup table directly adjusts the bias voltage of the frequency divider / multiplier circuit to achieve temperature compensation.

[0075] Based on the user's switch button signals fed back by the 105 human-computer interaction circuit, the signal output results in different modes are displayed on the digital screen via the 104 communication and data output circuit: static mode (output only f0) or dynamic analysis mode (synchronously outputting the base frequency signal (f0) and the frequency division signal (f0 / 2)).n The circuit includes a multi-stage voltage output (1.2V to 5V) and a frequency multiplier signal (k·f0). The 106 power management circuit provides multi-stage voltage outputs (1.2V to 5V) to provide operating voltage for the components in the circuit, while the crystal oscillator in the 101 input port processing circuit provides the synchronous system clock signal for the entire circuit.

Claims

1. A quartz resonant micro-force sensing signal processing circuit, characterized in that, include: The input port processing circuit is electrically connected to the quartz resonant micro-force sensor and is used to receive the resonant signal output by the micro-force sensor. A frequency signal processing circuit, electrically connected to the input port processing circuit, is used to convert the resonant signal into an intermediate frequency signal, perform analog shaping, and output a processed signal. A frequency calculation circuit, electrically connected to the frequency signal processing circuit, is used to extract the digital baseband signal from the processed signal; The first memory is used to store the frequency division coefficient and the frequency multiplication coefficient; A reconfigurable frequency divider, electrically connected to the frequency calculation circuit and the first memory, is used to generate a frequency-divided signal of the digital baseband signal based on the frequency division coefficient; A digital frequency multiplier, electrically connected to the frequency calculation circuit and the first memory, is used to generate a multiplied signal of the digital base frequency signal based on the multiplication factor.

2. The circuit according to claim 1, characterized in that, It also includes a temperature compensation circuit, which comprises a temperature sensor, a first analog-to-digital converter, a second memory, and a digital-to-analog converter connected in sequence. The temperature sensor is used to detect the temperature in real time and output an analog voltage signal. The first analog-to-digital converter is used to convert the analog voltage signal into a digital signal. The second memory obtains the temperature compensation value based on the digital signal. The digital-to-analog converter generates the bias voltage of the reconfigurable frequency divider and the digital frequency multiplier according to the temperature compensation value.

3. The circuit according to claim 1, characterized in that, The reconfigurable frequency divider includes multiple programmable frequency divider units connected in parallel. Each programmable frequency divider unit is electrically connected to the frequency calculation circuit and the first memory, respectively, and is used to obtain its respective frequency division coefficient from the first memory, synchronously generate multiple frequency division signals, and output them in parallel.

4. The circuit according to claim 1, characterized in that, The digital frequency multiplier includes multiple digital frequency multiplier units connected in parallel. Each digital frequency multiplier unit is electrically connected to the frequency calculation circuit and the first memory, respectively, and is used to obtain its respective frequency multiplication coefficient from the first memory, synchronously generate multiple frequency multiplication signals, and output them in parallel.

5. The circuit according to claim 1, characterized in that, The frequency calculation circuit includes a second analog-to-digital converter and a phase-locked loop connected to each other. The second analog-to-digital converter is used to convert the processed signal into a digital processed signal, and the phase-locked loop is used to lock the base frequency signal of the digital processed signal and output the digital base frequency signal.

6. The circuit according to claim 1, characterized in that, The input port processing circuit includes an anti-static resistor array and a crystal oscillator. The anti-static resistor array is electrically connected to a quartz resonant micro-force sensor and is used to receive the resonant signal output by the micro-force sensor. The crystal oscillator is electrically connected to the frequency signal processing circuit, the reconfigurable frequency divider, and the digital frequency multiplier, respectively, and is used to generate a clock signal.

7. The circuit according to claim 6, characterized in that, The antistatic resistor array comprises multiple sets of thin-film resistors connected in series.

8. The circuit according to claim 1, characterized in that, The frequency signal processing circuit includes a mixer circuit, an amplifier circuit, a filter circuit, and a shaping circuit connected in sequence.

9. The circuit according to claim 1, characterized in that, It also includes an output port processing circuit, which is electrically connected to the frequency calculation circuit, the reconfigurable frequency divider and the digital frequency multiplier, respectively, and is used to package the digital baseband signal, the frequency division signal and the frequency multiplier signal into a standardized data transmission frame.

10. The circuit according to claim 9, characterized in that, It also includes a human-computer interaction unit, which is electrically connected to the frequency calculation circuit, the reconfigurable frequency divider and the digital frequency multiplier, respectively, and is used to respond to user commands to make the output port processing circuit output the digital baseband signal, or output the digital baseband signal, the frequency divider signal and the frequency multiplier signal.

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