A gigabit industrial ethernet interface circuit

Abstract

The utility model relates to the field of ethernet interface, concretely relates to a kind of gigabit industrial ethernet interface circuit.2-way 10 / 100 / 1000Mbps adaptive MAC chip is integrated, two gigabit ethernet interfaces are realized by external expansion gigabit PHY device, data transmission speed is greatly improved.The utility model provides a kind of gigabit industrial ethernet interface circuit, including gigabit ethernet controller, the gigabit ethernet controller connects two-way gigabit ethernet interface, each gigabit ethernet interface includes gigabit ethernet transceiver chip, gigabit network transformer, bidirectional transient voltage suppression diode array, gigabit ethernet controller is connected with gigabit ethernet transceiver chip YT8511, ethernet transceiver chip YT8511 is connected with gigabit network transformer, and gigabit network transformer integrates RJ45 interface.The utility model is suitable for gigabit industrial ethernet interface.

Description

Technical Field

[0001] This utility model relates to the field of Ethernet interfaces, specifically to a gigabit industrial Ethernet interface circuit. Background Technology

[0002] Gigabit Ethernet is a high-speed wired network technology defined by the IEEE 802.3 standard. Since its standardization in 1999, it has become the mainstream choice for enterprise, data center, and consumer networks. Its interface design incorporates several key technologies to achieve high-speed transmission of 1Gbps while maintaining compatibility with traditional Ethernet.

[0003] With the development of related technologies, transmission rates and transmission techniques have been greatly improved. Existing technologies, such as the Gigabit Ethernet interface circuit disclosed in CN203104528U, include: a microcontroller connected to a MAC chip, and a PHY chip connected to a PHY chip; the microcontroller receives first data transmitted from an external device and transmits it to the PHY chip via the MAC chip; the PHY chip sends the first data through a Gigabit Ethernet port; the PHY chip receives second data through the Gigabit Ethernet port and transmits it to the microcontroller via the MAC chip; the microcontroller transmits the second data to the external device through the external device's interface. This solution achieves the interception and processing of Gigabit Ethernet data, realizes the sending and receiving of data packets, increases the transmission speed to 300Mb / s, and provides an external data processing interface.

[0004] However, the above solutions have low integration and require many peripheral circuits; they do not integrate an RJ45 interface, resulting in low compatibility; the improvement in transmission speed is limited, and they lack ESD protection. Utility Model Content

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a gigabit industrial Ethernet interface circuit that integrates two 10 / 100 / 1000Mbps adaptive MAC chips and realizes two gigabit Ethernet interfaces by expanding gigabit PHY devices, which greatly improves the data transmission speed.

[0006] This utility model achieves the above objectives by adopting the following technical solution: This utility model provides a gigabit industrial Ethernet interface circuit, including a gigabit Ethernet controller. The gigabit Ethernet controller connects two gigabit Ethernet interfaces. Each gigabit Ethernet interface includes a gigabit Ethernet transceiver chip U1, a gigabit network transformer U2, a first bidirectional transient voltage suppression diode array U3, and a second bidirectional transient voltage suppression diode array U4. Pins 25, 26, 28, and 29 of the gigabit Ethernet transceiver chip U1 are respectively connected to the data receiving pins of the gigabit Ethernet controller. Pin 30 of the gigabit Ethernet transceiver chip U1 is connected to the receive data valid signal pin of the gigabit Ethernet controller. Pins 31, 32, 33, 34, 35, 36, 28, and 29 of the gigabit Ethernet transceiver chip U1 are connected to the data receiving pins of the gigabit Ethernet controller. Pin 13 is connected to the receive and transmit clock signal pins of the Gigabit Ethernet controller, pin 32 is connected to the transmit control signal pin of the Gigabit Ethernet controller, pins 34 to 37 are connected to the data transmit pins of the Gigabit Ethernet controller, pin 39 is connected to the management data input or output pin of the Gigabit Ethernet controller, pin 40 is connected to the management data clock pin of the Gigabit Ethernet controller, pin 20 is connected to the status signal pin of the Gigabit Ethernet controller, and pin 23 is connected to the receive clock signal pin of the Gigabit Ethernet controller.

[0007] Pins 9, 10, 12, and 13 of the Gigabit Ethernet transceiver chip U1 are connected to the input terminals of the first bidirectional transient voltage suppressor diode array U3, respectively. Pins 15, 16, 18, and 19 of the Gigabit Ethernet transceiver chip U1 are connected to the input terminals of the second bidirectional transient voltage suppressor diode array U4, respectively. The output terminals of the first bidirectional transient voltage suppressor diode array U3 and the second bidirectional transient voltage suppressor diode array U4 are connected to pins 1, 2, 3, 4, 7, 8, 9, and 10 of the Gigabit network transformer U2, respectively. The Gigabit network transformer U2 integrates an RJ45 interface.

[0008] Furthermore, each Gigabit Ethernet interface also includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The second pin of the Gigabit Ethernet transceiver chip U1 is connected to a 1.1V voltage terminal through the first inductor L1 and is grounded through the first capacitor C1 and the second capacitor C2 respectively. The thirty-ninth, fortieth, and twentieth pins of the Gigabit Ethernet transceiver chip U1 are connected to a 3.3V DC voltage terminal through the first resistor R1, the second resistor R2, and the third resistor R3 respectively. The seventh pin of the Gigabit Ethernet transceiver chip U1 is grounded through the fourth resistor R4, the twenty-fourth pin of the Gigabit Ethernet transceiver chip U1 is grounded through the fifth resistor R5, and the eighth and twenty-seventh pins of the Gigabit Ethernet transceiver chip U1 are also grounded through the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5.

[0009] Furthermore, each gigabit Ethernet interface also includes a sixth capacitor C6, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The sixth and seventh pins of the gigabit network transformer U2 are grounded through the sixth capacitor C6. The eleventh pin of the gigabit network transformer U2 is connected to the 3.3V DC voltage terminal. The twelfth pin is connected to the network data activity status pin through the sixth resistor R6. The thirteenth pin of the gigabit network transformer U2 is connected to the LED control pin indicating the 10M / 100M connection speed through the seventh resistor R7. The fourteenth pin of the gigabit network transformer U2 is connected to the LED control pin indicating the gigabit connection status through the eighth resistor R8.

[0010] The beneficial effects of this utility model are:

[0011] This utility model's gigabit Ethernet controller uses an RK3568 processor, which integrates two 10 / 100 / 1000Mbps adaptive MACs. By expanding the gigabit PHY device, gigabit network transformer, and RJ45 interface, it realizes the required two gigabit Ethernet interfaces, greatly improving data transmission efficiency.

[0012] Gigabit network transformers provide physical layer signal conversion for Gigabit Ethernet, support high-speed data transmission, and have filtering functions to reduce signal interference and improve network communication stability.

[0013] Deploying TVS diodes (such as ESD0524P) between the gigabit network transformer and the gigabit Ethernet transceiver chip protects against electrostatic discharge and surge impacts, improving circuit safety. Attached Figure Description

[0014] Figure 1 This utility model provides a block diagram of a gigabit industrial Ethernet interface circuit structure;

[0015] Figure 2 This is a circuit diagram of a gigabit Ethernet transceiver chip provided by this utility model;

[0016] Figure 3 This is a circuit diagram of a gigabit network transformer provided by this utility model;

[0017] Figure 4 This is a circuit structure diagram of a first bidirectional transient voltage suppression diode array and a second bidirectional transient voltage suppression diode array provided by this utility model. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0019] This utility model provides a gigabit industrial Ethernet interface circuit, such as Figures 1 to 4 As shown, the system includes a Gigabit Ethernet controller connected to two Gigabit Ethernet interfaces. Each Gigabit Ethernet interface includes a Gigabit Ethernet transceiver chip U1, a Gigabit network transformer U2, a first bidirectional transient voltage suppressor diode array U3, and a second bidirectional transient voltage suppressor diode array U4. Pins 25, 26, 28, and 29 of the Gigabit Ethernet transceiver chip U1 are connected to the data receive pins of the Gigabit Ethernet controller, pin 30 of the Gigabit Ethernet transceiver chip U1 is connected to the receive data valid signal pin of the Gigabit Ethernet controller, and pins 31 and 33 of the Gigabit Ethernet transceiver chip U1 are connected to the receive and transmit pins of the Gigabit Ethernet controller, respectively. The clock signal pin is connected; pin 32 of the Gigabit Ethernet transceiver chip U1 is connected to the transmit control signal pin of the Gigabit Ethernet controller; pins 34 to 37 of the Gigabit Ethernet transceiver chip U1 are connected to the data transmit pin of the Gigabit Ethernet controller respectively; pin 39 of the Gigabit Ethernet transceiver chip U1 is connected to the management data input or output pin of the Gigabit Ethernet controller; pin 40 of the Gigabit Ethernet transceiver chip U1 is connected to the management data clock pin of the Gigabit Ethernet controller; pin 20 of the Gigabit Ethernet transceiver chip U1 is connected to the status signal pin of the Gigabit Ethernet controller; and pin 23 of the Gigabit Ethernet transceiver chip U1 is connected to the receive clock signal pin of the Gigabit Ethernet controller.

[0020] Pins 9, 10, 12, and 13 of the Gigabit Ethernet transceiver chip U1 are connected to the input terminals of the first bidirectional transient voltage suppressor diode array U3, respectively. Pins 15, 16, 18, and 19 of the Gigabit Ethernet transceiver chip U1 are connected to the input terminals of the second bidirectional transient voltage suppressor diode array U4, respectively. The output terminals of the first bidirectional transient voltage suppressor diode array U3 and the second bidirectional transient voltage suppressor diode array U4 are connected to pins 1, 2, 3, 4, 7, 8, 9, and 10 of the Gigabit network transformer U2, respectively. The Gigabit network transformer U2 integrates an RJ45 interface.

[0021] Specifically, each Gigabit Ethernet interface also includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The second pin of the Gigabit Ethernet transceiver chip U1 is connected to a 1.1V voltage terminal through the first inductor L1 and is grounded through the first capacitor C1 and the second capacitor C2 respectively. The thirty-ninth, fortieth, and twentieth pins of the Gigabit Ethernet transceiver chip U1 are connected to a 3.3V DC voltage terminal through the first resistor R1, the second resistor R2, and the third resistor R3 respectively. The seventh pin of the Gigabit Ethernet transceiver chip U1 is grounded through the fourth resistor R4, the twenty-fourth pin of the Gigabit Ethernet transceiver chip U1 is grounded through the fifth resistor R5, and the eighth and twenty-seventh pins of the Gigabit Ethernet transceiver chip U1 are also grounded through the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5.

[0022] Specifically, each gigabit Ethernet interface also includes a sixth capacitor C6, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The sixth and seventh pins of the gigabit network transformer U2 are grounded through the sixth capacitor C6. The eleventh pin of the gigabit network transformer U2 is connected to the 3.3V DC voltage terminal. The twelfth pin is connected to the network data activity status pin through the sixth resistor R6. The thirteenth pin of the gigabit network transformer U2 is connected to the LED control pin indicating the 10M / 100M connection speed through the seventh resistor R7. The fourteenth pin of the gigabit network transformer U2 is connected to the LED control pin indicating the gigabit connection status through the eighth resistor R8.

[0023] The working principle of this utility model is as follows:

[0024] The RK3568 CPU has an embedded Gigabit Ethernet MAC. Through an external Gigabit Ethernet transceiver chip YT8511, it converts Ethernet data packets into level signals that can be transmitted over twisted-pair media. After passing through electrostatic discharge and surge protection devices, the level signals are transmitted to the RJ45 interface with a network transformer.

[0025] When Gigabit Ethernet is used for data transmission, data is sent from the CPU's MAC component as a TTL level signal, and after passing through the Gigabit Ethernet transceiver chip, it is sent to the twisted-pair transmission medium.

[0026] When Gigabit Ethernet is used for data reception, data is transmitted from the twisted-pair transmission medium through the RJ45 interface to the Gigabit Ethernet transceiver chip YT8511, where it is converted to TTL level and then transmitted to the MAC component inside the CPU.

[0027] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. A gigabit industrial Ethernet interface circuit, characterized in that, The system includes a Gigabit Ethernet controller connected to two Gigabit Ethernet interfaces. Each Gigabit Ethernet interface includes a Gigabit Ethernet transceiver chip (U1), a Gigabit network transformer (U2), a first bidirectional transient voltage suppressor diode array (U3), and a second bidirectional transient voltage suppressor diode array (U4). Pins 25, 26, 28, and 29 of the Gigabit Ethernet transceiver chip (U1) are connected to the data receive pins of the Gigabit Ethernet controller, pin 30 of the Gigabit Ethernet transceiver chip (U1) is connected to the receive data valid signal pin of the Gigabit Ethernet controller, and pins 31 and 33 of the Gigabit Ethernet transceiver chip (U1) are connected to the receive and transmit pins of the Gigabit Ethernet controller, respectively. The clock signal pin is connected; pin 32 of the Gigabit Ethernet transceiver chip (U1) is connected to the transmit control signal pin of the Gigabit Ethernet controller; pins 34 to 37 of the Gigabit Ethernet transceiver chip (U1) are connected to the data transmit pins of the Gigabit Ethernet controller; pin 39 of the Gigabit Ethernet transceiver chip (U1) is connected to the management data input or output pin of the Gigabit Ethernet controller; pin 40 of the Gigabit Ethernet transceiver chip (U1) is connected to the management data clock pin of the Gigabit Ethernet controller; pin 20 of the Gigabit Ethernet transceiver chip (U1) is connected to the status signal pin of the Gigabit Ethernet controller; and pin 23 of the Gigabit Ethernet transceiver chip (U1) is connected to the receive clock signal pin of the Gigabit Ethernet controller. Pins 9, 10, 12, and 13 of the Gigabit Ethernet transceiver chip (U1) are connected to the input terminals of the first bidirectional transient voltage suppressor diode array (U3), respectively. Pins 15, 16, 18, and 19 of the Gigabit Ethernet transceiver chip (U1) are connected to the input terminals of the second bidirectional transient voltage suppressor diode array (U4), respectively. The output terminals of the first bidirectional transient voltage suppressor diode array (U3) and the second bidirectional transient voltage suppressor diode array (U4) are connected to pins 1, 2, 3, 4, 7, 8, 9, and 10 of the Gigabit network transformer (U2), respectively. The Gigabit network transformer (U2) integrates an RJ45 interface.

2. The gigabit industrial Ethernet interface circuit according to claim 1, characterized in that, Each Gigabit Ethernet interface also includes a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), a first inductor (L1), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), and a fifth resistor (R5). The second pin of the Gigabit Ethernet transceiver chip (U1) is connected to a 1.1V voltage terminal through the first inductor (L1), and grounded through the first capacitor (C1) and the second capacitor (C2) respectively. The Gigabit Ethernet transceiver... Pins 39, 40, and 20 of chip (U1) are connected to a 3.3V DC voltage terminal through resistors 1 (R1), 2 (R2), and 3 (R3), respectively. Pin 7 of the Gigabit Ethernet transceiver chip (U1) is grounded through resistor 4 (R4), pin 24 of the Gigabit Ethernet transceiver chip (U1) is grounded through resistor 5 (R5), and pins 8 and 27 of the Gigabit Ethernet transceiver chip (U1) are also grounded through capacitors 3 (C3), 4 (C4), and 5 (C5).

3. The gigabit industrial Ethernet interface circuit according to claim 1, characterized in that, Each Gigabit Ethernet interface also includes a sixth capacitor (C6), a sixth resistor (R6), a seventh resistor (R7), and an eighth resistor (R8). The sixth and seventh pins of the Gigabit network transformer (U2) are grounded through the sixth capacitor (C6). The eleventh pin of the Gigabit network transformer (U2) is connected to the 3.3V DC voltage terminal. The twelfth pin is connected to the network data activity status pin through the sixth resistor (R6). The thirteenth pin of the Gigabit network transformer (U2) is connected to the LED control pin indicating the 10M / 100M connection speed through the seventh resistor (R7). The fourteenth pin of the Gigabit network transformer (U2) is connected to the LED control pin indicating the Gigabit connection status through the eighth resistor (R8).

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