A hardware anti-jitter electronic switch circuit

Abstract

The utility model discloses a kind of hardware anti-shaking electronic switch circuit, including signal input filter voltage stabilizing circuit, signal anti-shaking inverting circuit and signal buffer circuit;Wherein, the input end of signal input filter voltage stabilizing circuit is connected after the input signal needing anti-shaking outside, the output end of signal input filter voltage stabilizing circuit is connected with the signal anti-shaking inverting circuit, signal buffer circuit;The output end of signal anti-shaking inverting circuit is connected with the input end of signal buffer circuit, and the output end of signal buffer circuit is connected to the external circuit of receiving anti-shaking signal.The utility model can effectively eliminate mechanical contact shaking, ensure the stability and accuracy of signal, applicable to most circuits needing signal anti-shaking.Meanwhile, circuit structure is easy to realize, and cost is low.

Description

Technical Field

[0001] This utility model relates to the field of electronic switch technology, and in particular to a hardware anti-jitter electronic switch circuit. Background Technology

[0002] Debounce electronic switches, also known as debounce circuits or anti-jitter circuits, are a common design strategy in electronic systems, primarily used in signal processing and control systems. When a mechanical switch is pressed or released, a brief, continuous switching action, known as jitter, occurs due to physical reasons. This jitter can lead to malfunctions or system instability; therefore, the purpose of debounce technology is to ensure the stability and accuracy of the switching signal.

[0003] The basic principle of debounce circuits is to filter out repetitive switching signals within a short period of time using software or hardware. Existing solutions mostly rely on software debounce (such as delay detection), but this increases system response latency and is not suitable for purely hardware circuits without an MCU (microcontroller unit). Therefore, it is essential to research a debounce electronic switch suitable for purely hardware circuits without an MCU. Summary of the Invention

[0004] The purpose of this invention is to provide a hardware anti-jitter electronic switch circuit to solve the problem that existing anti-jitter electronic switches are not suitable for pure hardware circuits without an MCU.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A hardware anti-shake electronic switch circuit includes a signal input filtering and voltage regulation circuit, a signal anti-shake inverting circuit, and a signal buffer circuit. The input terminal of the signal input filtering and voltage regulation circuit is connected in series with the external input signal requiring anti-shake measures. The output terminal of the signal input filtering and voltage regulation circuit is connected to the signal anti-shake inverting circuit and the signal buffer circuit. The output terminal of the signal anti-shake inverting circuit is connected to the input terminal of the signal buffer circuit, and the output terminal of the signal buffer circuit is connected to an external circuit receiving the anti-shake signal.

[0006] Furthermore, the signal input filtering and voltage regulation circuit includes a filter capacitor C1, a filter capacitor C2, and a voltage regulator chip U1; wherein, pin 3 of the voltage regulator chip U1 is connected to one end of the filter capacitor C1, and this connection is connected to the external input signal that needs to be de-jittered; the other end of the filter capacitor C2, pin 1 of the voltage regulator chip U1, and one end of the filter capacitor C1 are all connected to GND; pins 2 and 4 of the voltage regulator chip U1 and the other end of the filter capacitor C1 are all connected, and this connection serves as the output terminal of the signal input filtering and voltage regulation circuit, connecting to the signal de-jitter inverting circuit and the signal buffer circuit.

[0007] Furthermore, the voltage regulator chip U1 adopts an RS3015-5.0XD3 linear regulator.

[0008] Furthermore, the signal anti-jitter inverting circuit includes an RC delay resistor R1, a capacitor C3, a Schmitt trigger inverter chip U2, a chip power supply current limiting resistor R2, and a power supply decoupling capacitor C4. One end of the RC delay resistor R1 serves as the input terminal of the signal anti-jitter inverting circuit, connected to the output terminal of the signal input filtering and voltage regulation circuit. The other end of the RC delay resistor R1, one end of the capacitor C3, and pin 1 of the Schmitt trigger inverter chip U2 are connected together, and the signal KEY is also connected at this connection point. The other end of the capacitor C3... Pin 2 of the Schmitt trigger inverter chip U2 is connected to GND; pin 2 of the Schmitt trigger inverter chip U2 serves as the output of the signal debouncing inverter circuit, and the output signal C is connected to the input of the signal buffer circuit; pin 7 of the Schmitt trigger inverter chip U2 is connected to GND; pin 14 of the Schmitt trigger inverter chip U2, one end of the chip power supply current limiting resistor R2, and one end of the power supply decoupling capacitor C4 are connected together; the other end of the chip power supply current limiting resistor R2 is also connected to the output of the signal input filter and voltage regulator circuit; the other end of the power supply decoupling capacitor C4 is connected to GND.

[0009] Furthermore, the Schmitt trigger inverter chip U2 adopts a six-channel Schmitt trigger inverter 74HC14D.

[0010] Furthermore, the signal buffer circuit includes a chip enable resistor R3, a chip power supply current limiting resistor R4, a chip enable resistor R5, a Schmitt in-phase buffer chip U3, and a power supply decoupling capacitor C5; wherein, one end of the chip enable resistor R3 is connected to pin 1 of the Schmitt in-phase buffer chip U3; the other end of the chip enable resistor R3 is connected to GND; pin 2 of the Schmitt in-phase buffer chip U3 is connected to the output terminal of the signal anti-jitter inverting circuit; pin 10 of the Schmitt in-phase buffer chip U3 is connected to GND; pin 20 of the Schmitt in-phase buffer chip U3, the chip power supply current limiting resistor R4, the chip enable resistor R5, a Schmitt in-phase buffer chip U3, and a power supply decoupling capacitor C5 are connected to the output terminal of the signal anti-jitter inverting circuit; pin 10 of the Schmitt in-phase buffer chip U3 is connected to GND; and pin 20 of the Schmitt in-phase buffer chip U3 is connected to the chip power supply current limiting resistor R4, the chip power supply current limiting resistor R5, ...5, the chip power supply current limiting resistor R4, the chip power supply current limiting resistor R5, the chip power supply current limiting resistor R One end of the current-limiting resistor R4 and one end of the power supply decoupling capacitor C5 are connected together; the other end of the chip power supply current-limiting resistor R4 is connected to the output terminal of the signal input filter and voltage regulator circuit, which is used to power the Schmitt in-phase buffer chip U3; the other end of the power supply decoupling capacitor C5 is connected to GND; pin 19 of the Schmitt in-phase buffer chip U3 is connected to one end of the chip enable resistor R5, and the other end of the chip enable resistor R5 is connected to GND; pin 18 of the Schmitt in-phase buffer chip U3 serves as the output terminal of the signal buffer circuit, and the output signal D is connected in series to the external circuit that receives the anti-shake signal.

[0011] Furthermore, the RC delay resistor R1 is 10K, the capacitor C3 is 10UF, the chip power supply current limiting resistor R2 is 100R, the chip enable resistors R3 and R5 are 10K, the current limiting resistor R4 is 220R, and the power supply decoupling capacitor C5 is 10UF.

[0012] The circuit of this invention consists of discrete components. Its signal input terminal is connected in series with the jitter signal, and the output signal is connected in series with an external circuit that receives the anti-jitter signal. It uses a 74HC14D chip for signal anti-jitter, which has hysteresis characteristics and strong noise immunity; it uses a 74HCT244D chip for output, providing signal isolation to protect sensitive circuits, high-speed CMOS, TTL level compatibility, and tri-state output. It effectively eliminates mechanical contact jitter, ensuring signal stability and accuracy. It is suitable for pure hardware circuits without an MCU and most circuits requiring signal anti-jitter. Furthermore, the circuit structure is easy to implement and low in cost. Attached Figure Description

[0013] Figure 1 This is a structural block diagram of the hardware anti-shake electronic switch circuit of this utility model.

[0014] Figure 2 This is a circuit diagram of a preferred embodiment of the present invention. Detailed Implementation

[0015] To further explain the structure and overall operation of the technical solution of this utility model, the following description is provided in conjunction with the accompanying drawings: like Figure 1 As shown, the hardware anti-shake electronic switch circuit provided by this utility model includes a signal input filtering and voltage regulation circuit, a signal anti-shake inverting circuit, and a signal buffer circuit. The input terminal of the signal input filtering and voltage regulation circuit is connected in series after the external input signal A that needs to be anti-shake. The output terminal of the signal input filtering and voltage regulation circuit is connected to the signal anti-shake inverting circuit and the signal buffer circuit. The output terminal of the signal anti-shake inverting circuit is connected to the input terminal of the signal buffer circuit, and the output terminal of the signal buffer circuit is connected to the external circuit that receives the anti-shake signal.

[0016] Example: like Figure 2 As shown, the specific design of the preferred embodiment of this utility model is as follows: The signal input filtering and voltage regulation circuit includes filter capacitor C1, filter capacitor C2, and voltage regulator chip U1. U1 is a voltage regulator (LDO). Pin 3 (VIN) of voltage regulator chip U1 is connected to one end of filter capacitor C1, and this connection is connected to the external input signal A (Signal_input) requiring anti-jitter. The other end of filter capacitor C2, pin 1 (GND) of voltage regulator chip U1, and one end of filter capacitor C1 are all connected to GND. Pins 2 (VOU+), 4 (TAB) of voltage regulator chip U1, and the other end of filter capacitor C1 are all connected, and this connection serves as the output terminal (+5.1V) of the signal input filtering and voltage regulation circuit (1), connecting to the signal anti-jitter inverting circuit (2) and the signal buffer circuit (3). In the above design, after the input signal is regulated by U1, the output +5.1V not only powers the subsequent circuits but also serves as the signal. For this circuit, it is recommended that the voltage regulator chip U1 be an RS3015-5.0XD3 linear regulator (SOT-223 package) with an input of 3-45V, an output of 5V, and a maximum current of I=300mA; C1 and C2 should be 10uF capacitors with appropriate voltage rating.

[0017] The signal anti-jitter inverter circuit includes an RC delay resistor R1, a capacitor C3, a Schmitt trigger inverter chip U2, a chip power supply current limiting resistor R2, and a power supply decoupling capacitor C4. Among them, the Schmitt trigger inverter chip U2 has hysteresis characteristics, strong noise immunity, and inverted output. One end of the RC delay resistor R1 serves as the input terminal of the signal de-jitter inverter circuit, connected to the output terminal (+5.1V) of the signal input filter and voltage regulator circuit. The other end of the RC delay resistor R1, one end of the capacitor C3, and pin 1 of the Schmitt trigger inverter chip U2 are connected together at this connection point, which is the signal KEY, the processed input signal A (Signal_input). The other end of the capacitor C3 is connected to GND. Pin 2 of the Schmitt trigger inverter chip U2 serves as the output terminal (KEY_0) of the signal de-jitter inverter circuit, and the output signal C is connected to the input terminal of the signal buffer circuit. Pin 7 of the Schmitt trigger inverter chip U2 is connected to GND. Pin 14 of the Schmitt trigger inverter chip U2, one end of the chip power supply current limiting resistor R2, and one end of the power supply decoupling capacitor C4 are connected together. The other end of the chip power supply current limiting resistor R2 is also connected to the output terminal (+5.1V) of the signal input filter and voltage regulator circuit. The other end of the power supply decoupling capacitor C4 is connected to GND. In the above design, the "+5.1V" output from U1 powers U2 and also serves as a signal. The "+5.1V" signal, after passing through an RC delay resistor (R1) and capacitor (C3), becomes the "KEY" signal input to port 1A of chip U2. The six-channel Schmitt trigger inverter 74HC14D has a positive threshold voltage of 1.6V, a negative threshold voltage of 0.8V, and a hysteresis voltage of 0.8V. The +5.1V signal is 5.1V, which is greater than the positive threshold voltage of 1.6V. Therefore, port 2Y of chip U2 outputs the signal KEY_0 at a low level (0V), with an output current of ±25mA. The debouncing principle is that after RC filtering, the Schmitt trigger eliminates residual jitter. The parameters of the delay resistor R1 and capacitor C3 must satisfy the requirement that the RC time constant (Y=R×C) ≥ the jitter duration (typically 1ms-10ms). This circuit recommends using a six-channel Schmitt trigger inverter chip U2, namely a 74HC14D (SOIC-14 package); an RC delay resistor R1 of 10K; capacitors C3 and C4 of 10UF; and a chip power supply current limiting resistor R2 of 100R to prevent damage to the power supply of chip U2.

[0018] The signal buffer circuit includes a chip enable resistor R3, a chip power supply current limiting resistor R4, a chip enable resistor R5, a Schmitt in-phase buffer chip U3, and a power supply decoupling capacitor C5. Among them, the Schmitt in-phase buffer U3 is a Schmitt high-speed tri-state buffer, which has signal isolation and level conversion functions. One end of the chip enable resistor R3 is connected to pin 1 of the Schmitt in-phase buffer chip U3; the other end of the chip enable resistor R3 is connected to GND; pin 2 of the Schmitt in-phase buffer chip U3 is connected to the output terminal (KEY_0) of the signal anti-jitter inverting circuit; pin 10 of the Schmitt in-phase buffer chip U3 is connected to GND; pin 20 of the Schmitt in-phase buffer chip U3, one end of the chip power supply current limiting resistor R4, and one end of the power supply decoupling capacitor C5 are connected together; the other end of the chip power supply current limiting resistor R4 is connected to the output terminal (+5.1V) of the signal input filter and voltage regulator circuit to power the Schmitt in-phase buffer chip U3; the other end of the power supply decoupling capacitor C5 is connected to GND; pin 19 of the Schmitt in-phase buffer chip U3 is connected to one end of the chip enable resistor R5, and the other end of the chip enable resistor R5 is connected to GND; pin 18 of the Schmitt in-phase buffer chip U3 serves as the output terminal of the signal buffer circuit, and the output signal D (CH1) is connected in series to the external circuit that receives the anti-jitter signal. For this circuit, it is recommended that the Schmitt in-phase buffer chip U3 be an eight-channel in-phase buffer 74HCT244D; the chip enable resistors R3 and R5 be 10K; the current limiting resistor R4 be 220R; and the power supply decoupling capacitor C5 be 10UF.

[0019] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be conceived by those skilled in the art within the technical scope disclosed in this utility model without creative effort should be included within the protection scope of this utility model.

Claims

1. A hardware anti-jitter electronic switch circuit comprising a signal input filter and regulator circuit, characterized in that, It also includes a signal anti-shake inverting circuit and a signal buffer circuit; wherein, the input terminal of the signal input filtering and regulating circuit is connected in series after the external input signal that needs to be anti-shake, and the output terminal of the signal input filtering and regulating circuit is connected to the signal anti-shake inverting circuit and the signal buffer circuit; the output terminal of the signal anti-shake inverting circuit is connected to the input terminal of the signal buffer circuit, and the output terminal of the signal buffer circuit is connected to the external circuit that receives the anti-shake signal.

2. The hardware anti-jitter electronic switch circuit of claim 1, wherein, The signal input filtering and voltage regulation circuit includes a filter capacitor C1, a filter capacitor C2, and a voltage regulator chip U1. Pin 3 of the voltage regulator chip U1 is connected to one end of the filter capacitor C1, and this connection is used to connect the external input signal requiring anti-jitter. The other end of the filter capacitor C2, pin 1 of the voltage regulator chip U1, and one end of the filter capacitor C1 are all connected to GND. Pins 2 and 4 of the voltage regulator chip U1 and the other end of the filter capacitor C1 are all connected, and this connection serves as the output terminal of the signal input filtering and voltage regulation circuit, connecting to a signal anti-jitter inverting circuit and a signal buffer circuit.

3. The hardware anti-jitter electronic switch circuit of claim 2, wherein, The voltage regulator chip U1 is an RS3015-5.0XD3 linear regulator.

4. The hardware anti-jitter electronic switch circuit of claim 2, wherein, The signal anti-jitter inverter circuit includes an RC delay resistor R1, a capacitor C3, a Schmitt trigger inverter chip U2, a chip power supply current limiting resistor R2, and a power supply decoupling capacitor C4. One end of the RC delay resistor R1 serves as the input terminal of the signal anti-jitter inverter circuit and is connected to the output terminal of the signal input filter and voltage regulator circuit. The other end of the RC delay resistor R1, one end of the capacitor C3, and pin 1 of the Schmitt trigger inverter chip U2 are connected together, and signal KEY is also connected at this connection point. The other end of the capacitor C3 is connected to GND. Pin 2 of the Schmitt trigger inverter chip U2 serves as the output terminal of the signal anti-jitter inverter circuit, and the output signal C is connected to the input terminal of the signal buffer circuit. Pin 7 of the Schmitt trigger inverter chip U2 is connected to GND. Pin 14 of the Schmitt trigger inverter chip U2, one end of the chip power supply current limiting resistor R2, and one end of the power supply decoupling capacitor C4 are connected together. The other end of the chip power supply current limiting resistor R2 is also connected to the output terminal of the signal input filter and voltage regulator circuit. The other end of the power supply decoupling capacitor C4 is connected to GND.

5. The hardware anti-jitter electronic switch circuit of claim 4, wherein, The Schmitt trigger inverter chip U2 uses a six-channel Schmitt trigger inverter 74HC14D.

6. The hardware anti-jitter electronic switch circuit of claim 4, wherein, The signal buffer circuit includes a chip enable resistor R3, a chip power supply current limiting resistor R4, a chip enable resistor R5, a Schmitt in-phase buffer chip U3, and a power supply decoupling capacitor C5. One end of the chip enable resistor R3 is connected to pin 1 of the Schmitt in-phase buffer chip U3; the other end of the chip enable resistor R3 is connected to GND; pin 2 of the Schmitt in-phase buffer chip U3 is connected to the output of the signal anti-jitter inverting circuit; pin 10 of the Schmitt in-phase buffer chip U3 is connected to GND; and pin 20 of the Schmitt in-phase buffer chip U3 is connected to the chip power supply current limiting resistor. One end of resistor R4 and one end of power supply decoupling capacitor C5 are connected together; the other end of chip power supply current limiting resistor R4 is connected to the output of signal input filtering and voltage regulation circuit, used to power Schmitt in-phase buffer chip U3; the other end of power supply decoupling capacitor C5 is connected to GND; pin 19 of Schmitt in-phase buffer chip U3 is connected to one end of chip enable resistor R5, and the other end of chip enable resistor R5 is connected to GND; pin 18 of Schmitt in-phase buffer chip U3 serves as the output of signal buffer circuit, and the output signal D is connected in series to the external circuit that receives the anti-shake signal.

7. The hardware anti-jitter electronic switch circuit of claim 6, wherein, The RC delay resistor R1 is 10K, capacitors C3 and C4 are 10UF, the chip power supply current limiting resistor R2 is 100R, the chip enable resistors R3 and R5 are 10K, the current limiting resistor R4 is 220R, and the power supply decoupling capacitor C5 is 10UF.

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