Signal pin assembly for a power module for multiple devices

Abstract

Power module (55), comprising: a first insulating substrate (65) with a bonded copper layer on a first side defining conductor tracks (66), a plurality of first signal pins (67) and a plurality of power terminals (68), wherein the first signal pins (67) and the power terminals (68) are coplanar and each project over an edge (69) of the first insulating substrate (65); at least one semiconductor chip (70, 71, 72) containing a power transistor and having one side that is soldered to a corresponding conductor track (66) on the first insulating substrate (65) extending to one of the power terminals (68); a second insulating substrate (75) extending parallel to the first insulating substrate (65) and having a bonded copper layer on an inner side facing the first side and defining conductor tracks (76), and a plurality of second signal pins (77), wherein the second signal pins (77) are coplanar and each project over an edge (78) of the second insulating substrate (75), wherein the semiconductor chip (70, 71, 72) includes a plurality of signal contact points (73), wherein a first group of signal contact points (73) is each connected to a corresponding first signal pin (67), and wherein a second group of signal contact points (73) is each connected to a corresponding second signal pin (77); a large number of spacers, each soldered between the first side and the inside; and an encapsulation body that secures the insulating substrates (65, 75), the semiconductor chip (70, 71, 72) and the spacers, wherein the signal pins (67, 77) and the power terminals (68) extend through the encapsulation body.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to power modules containing high-power transistors for use in inverters for electric vehicles, and in particular to substrate and interconnect pin configurations to improve space utilization and reduce signal interactions.

[0002] Electric vehicles, such as hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and battery electric vehicles (BEVs), use inverter-driven electric machines to provide traction torque. A typical electric drive system may include a DC power source (such as a battery pack or fuel cell) coupled via power contactors to a variable voltage converter (VVC) to regulate a main bus voltage across a main DC link capacitor. An inverter is placed between the main bus and a traction motor to convert the DC bus power into an AC voltage that is coupled to the motor windings to propel the vehicle.

[0003] In publication US 9 041 183 B2, a power module with a first and second insulation substrate, each having a bonded copper layer, and furthermore a power transistor as well as a plurality of coplanar signal pins and power connections coupled to it.

[0004] The inverter comprises transistor switching devices (such as insulated-gate bipolar transistors or IGBTs) connected in a bridge configuration with multiple phase branches. A typical configuration includes a three-phase motor driven by a three-phase inverter. An electronic controller switches the switches on and off to convert a DC voltage from the bus into an AC voltage applied to the motor. The inverter can pulse-width modulate the DC input voltage to provide an approximate sinusoidal current output for driving the motor at a desired speed and torque. Pulse-width modulation (PWM) control signals applied to the gates of the IGBTs switch them on and off as needed, so the resulting current matches the desired current.

[0005] Due to the relatively high power (e.g., 100 kW) handled by the inverter switching transistors, they are typically designed as power modules that connect to a main printed circuit board containing a motor control IC and other auxiliary circuitry. Heat dissipation structures, such as a liquid-cooled cold plate, are typically positioned in contact with the power module(s) to manage large amounts of generated heat. A typical module may consist of a DCB (direct copper bonded) substrate with one or more power transistor chips soldered onto a copper layer, a conductor frame with multiple input / output pins, and an overmolded body encapsulating the module.

[0006] A power module can contain only one switching element (e.g., an IGBT along with a freewheeling diode, a reverse-conducting or RC IGBT, or a SiC MOSFET), which is referred to as a 1-in-1 power board. A power board can be single-sided or double-sided cooled. A power module can also contain a variety of switching transistors, i.e., an N-in-1 power board. A 2-in-1 power board can be used to form a single phase branch of an inverter bridge. Power modules with four or more switching transistors are also available, internally connected in a configuration that provides multiple phase branches and may include partially redundant transistors connected in parallel when forming a phase branch.

[0007] The power module typically takes the form of a flat, thin plate. Connecting pins extending from the module include power terminals for the inputs and output(s) of the phase branch(es), and signal pins for transistor control signals (i.e., gate signals) and various sensor signals. For example, many power modules incorporate on-chip temperature and / or pressure sensors.

[0008] In one conventional configuration, the power connections and signal pins extend from one or more of the narrow sides or edges of the module. The connections / pins can remain straight, so that when connected to a main circuit board, the module is oriented perpendicular to the main board, with both of the longest sides of the module exposed for heat dissipation by a heat sink or cold plate. Alternatively, the connections / pins can be bent, allowing the module to lie flat against the main circuit board. In either case, the relatively high voltage levels that can exist between different connections / pins dictate a minimum spacing between adjacent connections / pins. As the number of devices and associated sensors increases, more connections / pins are required for the module, and the required length of the module sides on which the connections / pins are located also increases.Consequently, the footprint on the main circuit board can increase undesirably. This problem is particularly significant when a DCB substrate is used, since the simplest and cheapest way to form the connections / pins is to have them extend outwards along the plane defined by the DCB substrate, resulting in the connections / pins all occupying a single layer.

[0009] The chip size required for any given power level is shrinking as a result of developments in power semiconductors, which have achieved lower losses, higher current densities (e.g., SiC power devices), and reverse conduction capability (e.g., RCIGBT). However, the placement of signal pins in a single layer could limit the potential use of smaller chips and further reductions in the size of power cards, especially for N-in-1 power cards with N greater than 2.

[0010] Another consequence of arranging the signal pins along a single layer is that the power connections are located on the same layer as the signal pins. Therefore, the signal pins were spaced apart from the power connections so that the magnetic field generated by the power connections does not couple with the signal loops (i.e., so that there is no constructive or destructive interference with the signals carried on the signal pins). Thus, single-layer modules utilize a pin spacing that avoids coupling a power loop with a signal loop, which could otherwise induce a gate current that unintentionally turns on the power devices, slows down the switching speed of the power devices, and / or interferes with on-die sensor signals. However, it would be advantageous to reduce the spacing without causing such coupling. BRIEF SUMMARY OF THE INVENTION

[0011] In one aspect of the invention, a power module comprises a first insulating substrate with a bonded copper layer on a first side, defining conductive traces, and a plurality of first signal pins and a plurality of power terminals. The first signal pins and power terminal are coplanar, and each projects beyond an edge of the first substrate. At least one semiconductor chip containing a power transistor has one side that is soldered to a corresponding conductive trace on the first substrate, extending to one of the power terminals. A second insulating substrate is provided parallel to the first substrate and has a bonded copper layer on an inner side facing the first side, defining conductive traces, and a plurality of second signal pins. The second signal pins are coplanar, and each projects beyond an edge of the second substrate.The chip incorporates a plurality of signal contact points, each of which is connected to a corresponding first signal pin in a first group, and each of which is connected to a corresponding second signal pin in a second group. Each of the plurality of spacers is soldered between the first side and the inner surface. An encapsulation body secures the substrates, the chip, and the spacers, with the signal pins and power connections extending through the encapsulation body. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic diagram showing a typical 2-in-1 power module. Fig. Figure 2 is an exploded view showing sections of a state-of-the-art power module. The Fig. 3, Fig. 4 and Fig. Figure 5 shows an isometric, end or side view of a state-of-the-art power module with a single pin layer having signal pins and power connections on opposite sides. Fig. Figure 6 is a top view of one side of a power module with both signal pins and power connections. Fig. Figure 7 is an end view of the power module. Fig. Figure 6 shows the induced magnetic fields for the signal pins and power connections. The Fig. 8 and Fig. Figure 9 shows an end or side view of a power module of the present invention. Fig. Figure 10 is a schematic diagram showing an arrangement of power devices according to an embodiment of a power module. Fig. Figure 11 is a top view showing an initial DCB substrate with power connectors, signal pins, and conductor tracks that house some of the semiconductor chips for the circuit. Fig. Record 10. Fig. Figure 12 is a top view showing a second DCB substrate with signal pins and conductor tracks, which connect the other semiconductor chips for the circuit. Fig. Record 10. Fig. 13 is a top view showing the first and second substrates from the Fig. 11 and Fig. Figure 12 shows which are joined together to form a power module with signal pins arranged in two layers. Fig. Figure 14 is a cross-section showing a two-layer construction according to the present invention. Fig. Figure 15 is an end view of a power module according to the invention, showing magnetic fields associated with the power terminals and signal pins. DETAILED DESCRIPTION OF PREFERRED EXECUTION FORMS

[0012] The present invention arranges the pins / terminals for the signal inputs / outputs (e.g., gate control, current sensor, and temperature sensor signals) in two parallel layers within the power module. The power connections (e.g., positive and negative bus and / or an output junction of a phase branch) are preferably arranged in only one of the layers. The signal pins are spaced both laterally along a long edge of the power module and transversely to the edge direction, so that minimal spacing (i.e., gaps) can be achieved while shortening the lateral length of the edge(s) of the power module. Preferably, the signal pins belonging to an individual power transistor (e.g., IGBT or MOSFET) are distributed between the two layers, so that corresponding signal loops can be magnetically decoupled from the power connection loop.

[0013] In relation to Fig. Figure 1 shows an exemplary configuration for a power module 10 comprising a first and second power transistor 11 and 12 with a reverse diode 13 and 14, respectively. Transistors 11 and 12 are connected in series between a positive bus terminal P and a negative bus terminal N. A junction between transistors 11 and 12 is connected to an AC power terminal to provide a phase branch output when the power module 10 is used for a phase branch in an inverter bridge. Power transistors 11 and 12 have corresponding gate input terminals G1 and G2, respectively, and corresponding Kelvin emitter terminals KE1 and KE2, with each pair of gate / emitter terminals receiving a corresponding gate drive signal to turn power transistors 11 and 12 on and off according to a switching algorithm implemented in a controller (not shown).

[0014] Transistors 11 and 12 have corresponding current sensor outputs SE1 and SE2 to provide a signal proportional to the main current flowing through transistors 11 and 12. On-die temperature sensors 15 and 16 are located in close proximity to transistors 11 and 12, respectively, to provide associated temperature signals via terminals K1 and A1 and K2 and A2, respectively.

[0015] A typical one, as in Fig. The construction shown in Figure 2 for a power module can include a DCB (Direct Copper Bond) substrate 20, wherein a first side 20a has a bonded copper layer etched to define traces 21 and signal pins 22 and 23. A second bonded copper layer on the opposite side 20b of the substrate 20 can act as a heat spreader to remove heat generated during the switching of the power transistors 11 and 12, as known in the subject matter. The traces 21 also extend from a corresponding edge of the substrate 20 to form the power terminals P, N, and AC. The signal pins 22 and 23 and the power terminals P, N, and AC are coplanar, and each projects beyond a corresponding edge of the substrate 20.The signal pins 22 and 23 and the power connections P, N and AC can be formed by etching a bonded copper layer or they can be formed, for example, using a conductor frame.

[0016] Semiconductor chips 24 and 25 each provide a corresponding power transistor, reverse diodes, and in-chip sensors (e.g., a current sensor and a temperature sensor). Each chip includes a variety of input / output contacts for connection to an external circuit via direct soldering or jumper wires soldered between the contacts and the traces or pins. Typically, one side of the semiconductor chip forms a collector terminal that is soldered directly to the traces 21, thereby connecting the P and N pins directly to the transistor emitters via the traces. The emitter sides of the transistors are connected to corresponding traces or terminals via jumper wires.A heat spreader 26, consisting of a conductive plate, is arranged against the remaining side of the chips 24 and 25 to transfer thermal energy to a heat sink, such as a cold plate. The heat spreader can be a DCB plate or simply an uninsulated copper layer. The power module is typically encapsulated in . Fig. The two components shown are held together within an overmolded body (e.g., thermoplastic).

[0017] The Fig. Figures 3-5 show a power module 30 of a type used for electric vehicle inverters. Any number of power transistors can be incorporated into a power module, typically in multiples of two according to a desired number of phase branches per module. Each IGBT or MOSFET transistor typically has five signal pins, consisting of Kelvin emitter pins (for receiving a gate drive signal) and sensor pins, including a current sensor pin and temperature anode and cathode pins. In the Fig. In the embodiment shown in Figures 3-5, the signal pins 31 extend from one edge of the module 30, and the power terminals 32 extend from an opposite edge, with the pins 31 and the terminals 32 all being coplanar in a single layer. The number of power terminals typically includes positive and negative bus terminals and one junction terminal for each phase branch. As the number of power transistors increases, the required length of the sides along which the signal pins 31 extend also increases proportionally. Pin spacing requirements can be significant to maintain sufficient voltage margin between adjacent pins to allow a voltage difference of approximately 15 to 20 V between pins of the same transistor device and a voltage difference of a few hundred volts between pins belonging to different transistor devices.Consequently, the in the . Fig. The device shown in 3-5 may be too long for some applications.

[0018] Fig. Figure 6 shows another prior art power module 35, which has power terminals 36 and 37 for conducting current in the direction shown. A pair of signal pins 38 and 39 and a pair of signal pins 40 and 41 also conduct current in the directions shown. The terminals 36 and 37 and the pins 38-41 extend from a common edge of the power module 35; however, the magnetic interaction discussed here applies equally to the case in which the terminals and pins occupy a single layer but extend from opposite edges. As in Fig. As shown in Figure 7, the power terminals 36 and 37 induce magnetic fields perpendicular to the plane defined by the flat module 35 (i.e., perpendicular to the line formed by the single layer of pins and terminals). Similarly, the signal pins 38-41 have an orientation that induces perpendicular magnetic fields. Likewise, the magnetic fields in the signal pins 38-41 induce currents perpendicular to the pin layer (e.g., generated by currents in the power terminals 36 and 37). Since the magnetic field directions associated with the pins 38-41 are either parallel or antiparallel with respect to the field directions for the power terminals 36 and 37, magnetic coupling between the power loops and the signal loops can be sufficiently strong to cause interference with the gate and sensor signals.

[0019] The Fig. 8 and Fig. Figure 9 shows a power module 45 of the present invention, wherein the signal pins are arranged in several layers to reduce the module's footprint. Signal pins extending from an edge of the module 45 include pins 46 and pins 47, each group of 5 pins representing a corresponding power transistor. The signal pins are distributed between a first layer 50 and a second layer 51. Layer 51 is preferably coplanar with the power terminals 48. Distributing the signal pins between layers 50 and 51 results in a more compact power module. Additionally, a specific connection of matching pairs of signal pins, such that interlocking pins are distributed between the two layers, is described below, which leads to magnetic decoupling of the signal loops from the power loops.

[0020] A general design for a detailed embodiment of a power module 55 is a Fig. Shown 11-13. Fig. Figure 10 is a schematic representation showing the arrangement of power transistors and a circuit configuration of module 55 for forming a pair of phase branches. Transistor devices 56 and 57 are connected in series to form a first phase branch, which has an output AC1 at an intermediate connection point. A second phase branch has an output AC2 by connecting in parallel the intermediate connections of a pair of series-connected power transistors 58 and 59 and power transistors 60 and 61. The parallel combination of two transistor sets in a phase branch serves to increase the current handling capacity.

[0021] The present embodiment uses a first in Fig. 11 isolation substrate shown and a second one in Fig. 12 insulation substrates shown, which are joined together to form a structure as shown in Fig. To train the module shown in section 13.

[0022] In relation to Fig. Figure 11 shows a first DCB substrate 65 having a first side defined by the conductor tracks 66, a plurality of signal pins 67, and a plurality of power terminals 68. The first signal pins 67 are coplanar with the power terminals 68 and the conductor tracks 66. The pins 67 each project over an edge 69 of the substrate 65. The power terminals 68 each project over an opposite edge of the DCB substrate 65. A plurality of semiconductor chips 70, 71, and 72 (each containing a corresponding power transistor) has a corresponding emitter side that is soldered to corresponding conductor tracks 66, thus defining the collector according to the Fig. The configuration shown in 10 is connected to the power connections 68.

[0023] Each semiconductor chip 70-72 has a plurality of signal contact points, including the contact points 73 shown for chip 70. Certain signal contact points 73 are connected to corresponding signal pins 67 using soldered jumper wires 74, such that a subset (i.e. less than all) of the signal pins associated with chip 70 are assigned to the first layer of signal pins 67.

[0024] A second DCB substrate 75 has a first (inner) side that defines the conductor tracks 76 and a plurality of second signal pins 77. Preferably, no power connections are provided on the second substrate 75; however, distributing the power connections is also within the scope of the invention. The second signal pins 77 are coplanar with the conductor tracks 66, and each projects over an edge 78 of the substrate 75. A plurality of semiconductor chips 80, 81, and 82 (each containing a corresponding power transistor) have a corresponding emitter side that is soldered to corresponding conductor tracks 76. To connect the conductor tracks 76 to the power connections 68 on the first substrate 65, conductive spacers are placed between the conductor tracks 76 and the conductor tracks 68. Fig. 11) soldered after substrates 65 and 75 were joined to form the power module. The solder joints of the conductive spacers are shown at 84, 85 and 86.

[0025] Each semiconductor chip 80-82 has a multitude of signal contact points. On each corresponding chip, some of its signal contact points are connected to corresponding second signal pins 77 using soldered jumper wires (e.g., the wires 83). On chips 70-72 and 80-82, the signal contact points that are not bridged to signal pins on the same substrate are bridged to signal pins on the other substrate. Thus, the signal pins associated with each particular chip are distributed between the first layer of signal pins 67 and the second layer of signal pins 77. Fig. Figure 13 shows the assembled substrates placed side by side, so that the signal pin layers are located in spaced parallel planes. In this position, the switching wires and conductive spacers can be soldered between the two substrates.

[0026] The structure of a power module 90 is shown in more detail in the cross-sectional view. Fig. Figure 14 shows a first DCB substrate comprising an insulating layer 91 with a shaped (e.g., etched) bonded copper layer 92 on one (internal) face and a continuous bonded copper layer 93 on the other (outer) face. The copper layer 92 extends beyond one edge of the insulating layer 91 to form a power terminal 94 and beyond an opposite edge to form a signal pin 95. A semiconductor chip 96 is soldered to the copper layer 92 and has a signal contact point that is connected to the signal pin 95 by a jumper wire 97. A second insulating layer 100 has a shaped bonded copper layer 101 on one side and a continuous copper-bonded copper layer 102 on the other side. A signal pin 103 extends along a common edge with the signal pins 95 as part of a second parallel layer.Conductive spacers 104 and 105 are soldered between the semiconductor chip 96 and the copper layer 101 to provide both the necessary electrical connections and a controlled gap to allow the penetration of an overmolding or encapsulation material 106 to provide a main structural body for the power module 90. The conductive spacers can also be soldered between the inner copper layers of the two substrates. The outer continuous copper layers act as heat spreaders to efficiently dissipate heat from the module 90 during operation.

[0027] The problem of magnetic coupling and interference between a power loop and a signal loop is addressed by the present invention, as described in Fig. Figure 15 shows a power module 110 having power terminals 111 and 112 spaced longitudinally along a long edge of the module 110. A pair of signal pins 113 and 114 and a pair of signal pins 115 and 116 are each oriented with respect to the substrate edges (i.e., each pair of pins is spaced along a line perpendicular to a line defined by the spacing of the power terminals 111 and 112). Each pair of signal pins 113 / 114 and 115 / 116 is selected to match a corresponding signal loop, such as a gate signal loop consisting of the gate pin and Kelvin emitter pin of a power transistor, or a sensor signal loop, such as the cathode and anode pins for a temperature sensor located at a power transistor.The resulting directions of the magnetic fields for the switching current in the power loop and the low-level signals in the signal loops are equally transversely oriented, which means that there is no net coupling and interference is avoided.

[0028] The matching of signal pins according to Fig.15 preferably corresponds to the alignment of the signal contact points for a power transistor that receive a gate drive signal for this power transistor. Thus, the signal contact points of a chip are divided into a first group of signal contact points, which includes one of the pair of gate drive contact points, and a second group of signal contact points, which includes the other of the pair of gate drive contact points. The first group of signal contact points is connected to pins in the first layer of pins, and the second group of signal contact points is connected to pins in the second layer of pins. Preferably, the first and second signal pins connected to the pair of gate drive contact points are oriented transversely with respect to the edge of the module.

[0029] Each semiconductor chip can contain a pair of signal contact points designed to provide a chip temperature signal. The first group of contact points, connected to the first layer of signal pins, can comprise one of the temperature signal contact points, and the second group of contact points, connected to the second layer of signal pins, can comprise the other of the temperature signal contact points. Again, the first and second signal pins connected to the temperature signal contact points are preferably oriented transversely with respect to the edge of the module.

[0030] The foregoing describes a two-layer signal pin design for a power module with significant advantages. In an N-in-1 power module, the two-layer signal pin design can save space while maintaining sufficient voltage headroom, thus reducing the overall size of the power module. On a gate drive board for an integrated circuit controller (ISC), multiple power modules are required, mounted together on the board, to drive a multitude of phase branches. The signal pin design of this invention can reduce the footprint required to accommodate the power modules on the gate drive board. Consequently, the size of the gate drive board can be reduced, and the signal trace design on the gate drive board can be simplified.The two-layer signal pin design can drastically reduce magnetic coupling between power loops and signal loops (e.g., during device switching transitions), especially when the power connections are located near the signal pins. The design of the power connections offers greater flexibility in the design of a power module, as the invention reduces the need to keep power connections as far away from the signal pins as possible.

Claims

[1] Power module (55), comprising: a first insulating substrate (65) with a bonded copper layer on a first side defining conductor tracks (66), a plurality of first signal pins (67) and a plurality of power terminals (68), wherein the first signal pins (67) and the power terminals (68) are coplanar and each project over an edge (69) of the first insulating substrate (65); at least one semiconductor chip (70, 71, 72) containing a power transistor and having one side that is soldered to a corresponding conductor track (66) on the first insulating substrate (65) extending to one of the power terminals (68); a second insulating substrate (75) extending parallel to the first insulating substrate (65) and having a bonded copper layer on an inner side facing the first side and defining conductor tracks (76), and a plurality of second signal pins (77), wherein the second signal pins (77) are coplanar and each project over an edge (78) of the second insulating substrate (75), wherein the semiconductor chip (70, 71, 72) includes a plurality of signal contact points (73), wherein a first group of signal contact points (73) is each connected to a corresponding first signal pin (67), and wherein a second group of signal contact points (73) is each connected to a corresponding second signal pin (77); a large number of spacers, each soldered between the first side and the inside; and an encapsulation body that secures the insulating substrates (65, 75), the semiconductor chip (70, 71, 72) and the spacers, wherein the signal pins (67, 77) and the power terminals (68) extend through the encapsulation body. [2] Power module (55) according to claim 1, comprising a plurality of semiconductor chips which are soldered to the first and second insulation substrate (65, 75) with corresponding conductor tracks, wherein each semiconductor chip contains a corresponding power transistor, and wherein power terminals (68) for all power transistors extend from the first insulation substrate (65). [3] Power module (55) according to claim 1, wherein a pair of signal contact points (73) are designed to receive a gate control signal for the power transistor, the first group comprising one of the pair of gate control signal contact points and the second group comprising the other of the pair of gate control signal contact points. [4] Power module (55) according to claim 3, wherein a corresponding first (67) and second signal pin (77) connected to the pair of gate control signal contact points are oriented transversely with respect to the edge (69) of the first insulation substrate (65), whereby a magnetic field associated with a gate current in the first (67) and second signal pin (77) is oriented transversely to a magnetic field associated with a switching current in the power terminals (68). [5] Power module (55) according to claim 1, wherein a pair of signal contact points (73) are configured to provide a semiconductor chip temperature signal, wherein the first group provides a first of the pair of temperature signal contact points and the second group includes the other of the pair of temperature signal contact points, and wherein a corresponding first and second signal pin (67, 77) connected to the pair of temperature signal contact points are oriented transversely with respect to the edge (69) of the first insulating substrate (65), whereby a magnetic field associated with a temperature signal in the first and second signal pin (67, 77) is oriented transversely to a magnetic field associated with a switching current in the power terminals (68). [6] Power module (55) according to claim 1, wherein the first signal pins (67) and the power terminals (68) extend from opposite edges (69) of the first insulation substrate (65). [7] Power module according to claim 6, wherein the first and second signal pins (67, 77) extend from adjacent edges (69, 78) of the first and second insulation substrate (65, 75), respectively. [8] Power module (55) according to claim 1, wherein each of the first and second insulation substrate (65, 75) has an outer surface consisting of a bonded copper layer designed to transfer heat generated in the power transistor. [9] Phase branch for an inverter in an electric vehicle, comprising: a first insulating substrate (65) with a bonded copper layer on a first side defining conductor tracks (66), a plurality of first signal pins (67) and a plurality of power terminals (68), wherein the first signal pins (67) and the power terminals (68) are coplanar and each project over an edge (69) of the first insulating substrate (65); a plurality of semiconductor chips (70, 71, 72), each containing a corresponding power transistor and having a corresponding side that is soldered to a corresponding conductor track (66) on the first insulating substrate (65) extending to one of the power terminals (68); a second insulating substrate (75) extending parallel to the first insulating substrate (65) and having a bonded copper layer on an inner side facing the first side and defining conductor tracks (76), and a plurality of second signal pins (77), wherein the second signal pins (77) are coplanar and each project over an edge (78) of the second insulating substrate (75), wherein the conductor tracks (76) connect corresponding power transistors in series with an intermediate connection point providing a phase branch output, wherein each semiconductor chip (70, 71, 72) includes a plurality of signal contact points (73), wherein a first group of signal contact points (73) of each power transistor is each connected to a corresponding first signal pin (67), and wherein a second group of signal contact points (73) of each power transistor is each connected to a corresponding second signal pin (77); a large number of spacers, each soldered between the first side and the inside; and an encapsulation body that secures the insulating substrates (65, 75), the semiconductor chips (70, 71, 72) and the spacers, wherein the signal pins (67) and the power terminals (68) extend through the encapsulation body. [10] Phase branch according to claim 9, wherein a pair of signal contact points of each power transistor is designed to receive a corresponding gate drive signal, and wherein each first group includes one of the pair of corresponding gate drive signal contact points and each second group includes the other of the corresponding gate drive signal contact points. [11] Phase branch according to claim 10, wherein corresponding first and second signal pins (67, 77) connected to each pair of gate control signal contact points are oriented transversely with respect to the edge (69) of the first insulation substrate (65), whereby a magnetic field associated with a gate current in the corresponding first and second signal pins (67, 77) is oriented transversely to a magnetic field associated with a switching current in the power terminals (68). [12] Phase branch according to claim 9, wherein a pair of signal contact points (73) of each semiconductor chip (70, 71, 72) are configured to provide a semiconductor chip temperature signal, wherein each first group provides a first of the corresponding pair of temperature signal contact points and each second group includes the other of the corresponding pair of temperature signal contact points, and wherein corresponding first and second signal pins (67, 77) connected to the corresponding pair of temperature signal contact points are oriented transversely with respect to the edge (69) of the first insulating substrate (65), whereby a magnetic field associated with a corresponding temperature signal in the first and second signal pins (67, 77) is oriented transversely to a magnetic field associated with a switching current in the power terminals (68). [13] Phase branch according to claim 9, wherein the first signal pins (67) and the power terminals (68) extend from opposite edges (69) of the first insulation substrate (65). [14] Phase branch according to claim 13, wherein the first and second signal pins (67, 77) extend from adjacent edges (69, 78) of the first and second insulation substrate (65, 75), respectively. [15] Phase branch according to claim 9, wherein each of the first and second insulating substrate (65, 75) has an outer surface consisting of a bonded copper layer designed to transfer heat generated in the power transistors.

Images