Systems and methods for accessing mass storage as working memory

Abstract

Processor device (202, 302, 402, 502) comprising: a microprocessor (212) comprising a microprocessor system agent (214); and a Field Programmable Gate Array (FPGA) (204, 304, 404, 504), wherein the FPGA (204, 304, 404, 504) comprises: an FPGA system agent (206, 306, 406, 506) for processing memory access requests (230) received from the microprocessor system agent (214) via a communication link (216, 218), wherein the FPGA system agent (206, 306, 406, 506) and the communication link (216, 218) are in a coherence region of the microprocessor (212); a memory controller (207, 316, 416, 508) communicatively coupled to the system agent (206, 306, 406, 506); a high-speed serial interface (208) for connecting the system agent (206, 306, 406, 506) to a mass storage system (218); wherein the FPGA system agent (206, 306, 406, 506) processes the memory access requests (230) by translating addresses in the memory access requests (230) into the addresses of the mass storage system (218) and accesses data at the addresses of the mass storage system (218) through a high-speed serial interface (208).

Description

AREA

[0001] This disclosure relates to systems and methods for accessing mass storage as memory. GENERAL STATE OF THE ART

[0002] Mass storage devices are often accessed as devices on a long-latency hardware interface through inefficient software layers. With the introduction of low-latency mass storage devices, access latencies for these devices are becoming very low, approaching DDR memory access latencies.

[0003] US 2015 / 0143003 A1 shows a fast and highly parallel configuration method for field programmable gate arrays (FPGAs).

[0004] The stated object is achieved according to the invention by the features of patent claim 1. Further embodiments of the invention are presented in the subclaims and the independent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates one embodiment of a block diagram for a computing system including a multi-core processor. Fig. 2 is a schematic diagram of an exemplary multi-chip platform including a field programmable gate array and a system agent according to embodiments of the present disclosure. Fig. 3 is a schematic diagram of another example multi-chip platform including a field programmable gate array and a system agent according to embodiments of the present disclosure. Fig. 4 is a schematic diagram of an exemplary multi-chip platform including a field programmable gate array and a system agent illustrating inline accelerator circuits according to embodiments of the present disclosure. Fig. 5A is a schematic diagram of an example multi-chip platform including a field programmable gate array and a system agent for connecting to a fabric-attached mass storage used as memory, according to embodiments of the present disclosure. Fig. 5B is a schematic diagram of an exemplary fabric-connected storage used as memory, according to embodiments of the present disclosure. Fig. 6A is a process flow diagram for processing a memory access request according to embodiments of the present disclosure. Fig. 6B is a process flow diagram for asynchronous memory access execution according to embodiments of the present disclosure. Fig. 6C is a process flow diagram for performing inline data processing according to embodiments of the present disclosure. Fig. 7 is a schematic diagram of one embodiment of a fabric composed of point-to-point connections interconnecting a set of components according to embodiments of the present disclosure. Fig. 8 is a schematic diagram of an embodiment of a layered protocol stack according to embodiments of the present disclosure. Fig. 9 is a schematic diagram of an embodiment of a PCIe transaction descriptor according to embodiments of the present disclosure. Fig. 10 is a schematic diagram of an embodiment of a PCIe point-to-point serial fabric according to embodiments of the present disclosure. Fig. 11 is a schematic block diagram of an example computer system formed with a processor including execution units to execute an instruction, wherein one or more of the interconnections implement one or more features according to an embodiment of the present disclosure. Fig. 12 is a schematic block diagram of a system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0005] In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific dimensions / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details need not be implemented to practice the present disclosure.In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuitry / code for described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, the specific expression of algorithms in code, specific shutdown and gating techniques / logic, and other specific operating details of computer systems, have not been described in detail to avoid unnecessarily obscuring the present disclosure.

[0006] While the following embodiments may be described with reference to power conservation and energy efficiency in specific integrated circuits, such as computing platforms or microprocessors, other embodiments are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from improved power efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. They may also be used in other devices, such as handheld devices, tablets, other thin notebooks, system-on-a-chip (SoC) devices, and embedded applications.Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, network computers (NetPC), set-top boxes, network nodes, wide-area network (WAN) switches, or any other system capable of performing the functions and operations taught below. Furthermore, the apparatus, methods, and systems described herein are not limited to physical computing devices but may also relate to software optimizations for power conservation and efficiency.As will be readily apparent from the following description, the embodiments of methods, devices, and systems described herein (whether related to hardware, firmware, software, or a combination thereof) are essential to a "green technology" future consistent with performance considerations.

[0007] As computing systems evolve, the components within them become more complex. As a result, the complexity of the interconnect architecture used to couple the components and enable communication between them also increases to ensure that bandwidth requirements for optimal component operation are met. Furthermore, different market segments require different aspects of interconnect architectures to meet market needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. However, a primary purpose of most fabrics is to provide the highest possible performance with maximum power savings. A number of interconnects that would potentially benefit from aspects of the disclosure described herein are discussed below.

[0008] Referring to Fig. Figure 1 depicts one embodiment of a block diagram for a computing system including a multi-core processor. Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system-on-a-chip (SOC), or other device for executing code. Processor 100, in one embodiment, includes at least two cores—cores 101 and 102—which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 100 may include any number of processing elements, which may be symmetric or asymmetric.

[0009] In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element capable of maintaining state for a processor, such as execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, an operating system, an application, or other code.A physical processor (or processor socket) typically refers to an integrated circuit that potentially contains any number of other processing elements, such as cores or hardware threads.

[0010] A core often refers to logic residing on an integrated circuit capable of maintaining independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic residing on an integrated circuit capable of maintaining independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, the boundaries of the nomenclature of a hardware thread and a core overlap when certain resources are shared and others are dedicated to an architectural state.However, a core and a hardware thread are often treated as individual logical processors by an operating system, with the operating system being able to schedule operations on each logical processor individually.

[0011] The physical processor 100, as in Fig. 1, includes two cores - core 101 and 102. Here, core 101 and 102 are considered symmetric cores, i.e., cores with the same configurations, functional units, and / or logic. In another embodiment, core 101 includes an out-of-order processor core, while core 102 includes an in-order processor core. However, cores 101 and 102 may be individually selected from any type of core, such as a native core, a software-managed core, a core configured to execute a native instruction set architecture (ISA), a core configured to execute a translated instruction set architecture (ISA), a co-designed core, or any other known core. In a heterogeneous core environment (i.e.,In the case of asymmetric cores, a form of translation, such as binary translation, may be used to schedule or execute code on one or both cores. To continue the discussion, the functional units depicted in core 101 are described in more detail below, as the units in core 102 operate in a similar manner in the depicted embodiment.

[0012] As depicted, core 101 includes two hardware threads 101a and 101b, which may also be referred to as hardware thread slots 101a and 101b. Therefore, in one embodiment, software entities, such as an operating system, potentially view processor 100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As mentioned above, a first thread is associated with architectural state registers 101a, a second thread is associated with architectural state registers 101b, a third thread may be associated with architectural state registers 102a, and a fourth thread may be associated with architectural state registers 102b. Here, each of the architectural state registers (101a, 101b, 102a, and 102b) may be referred to as processing elements, thread slots, or thread units, as described above.As shown, the architectural state registers 101a are replicated in the architectural state registers 101b, allowing individual architectural states / contexts to be stored for the logical processor 101a and the logical processor 101b. In the core 101, other minor resources, such as instruction pointers and renaming logic in the allocator and renamer block 130, may also be replicated for the threads 101a and 101b. Some resources, such as reorder buffers in the reorder / retirement unit 135, ILTB 120, load / store buffers, and queues, may be shared by partitioning. Other resources, such as internal general purpose registers, page table base register(s), low level data cache and data TLB 115, execution unit(s) 140, and portions of out-of-order unit 135 are potentially fully shared.

[0013] The processor 100 often includes additional resources that can be fully shared, shared by partitioning, or dedicated to processing elements. Fig. 1 illustrates one embodiment of a purely exemplary processor with illustrative logical units / resources of a processor. It should be understood that a processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not shown. As illustrated, core 101 includes a simplified, representative out-of-order (OOO) processor core. However, in various embodiments, an in-order processor may be utilized. The OOO core includes a branch target buffer 120 to predict branches to be executed / taken and an instruction translation buffer (I-TLB) 120 to store address translation entries for instructions.

[0014] Core 101 further includes decode module 125, which is coupled to load unit 120 to decode loaded elements. Load logic, in one embodiment, includes individual sequencers associated with thread slots 101a and 101b, respectively. Typically, core 101 is associated with a first ISA that defines / specifies instructions executable on processor 100. Often, machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode) that points to or specifies an instruction or operation to be executed. Decode logic 125 includes circuitry that recognizes these instructions by their opcodes and forwards the decoded instructions down the pipeline for processing as defined by the first ISA.For example, as discussed in more detail below, in one embodiment, decoders 125 include logic designed or configured to recognize specific instructions, such as transaction instructions. Upon recognition by decoders 125, architecture or core 101 takes specific, predefined actions to perform tasks associated with the respective instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note that in one embodiment, decoders 126 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 126 recognize a second ISA (either a subset of the first ISA or a different ISA).

[0015] In one example, allocator and renamer block 130 includes an allocator to reserve resources, such as register memory, to store instruction processing results. However, threads 101a and 101b are potentially capable of out-of-order execution, with allocator and renamer block 130 also reserving other resources, such as reorder buffers, to track instruction results. Unit 130 may also include a register renamer to rename program / instruction reference registers to other registers within processor 100. Reorder / retirement unit 135 includes components, such as the aforementioned reorder buffers, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of out-of-order instructions.

[0016] In one embodiment, the scheduler and execution unit block 140 includes a scheduler unit for scheduling instructions / operations onto execution units. For example, a floating-point instruction is scheduled on a port of an execution unit that has an available floating-point execution unit. Register memories associated with the execution units are also included to store information instruction processing results. Example execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

[0017] The low-level data cache and data translation buffer (D-TLB) 150 are coupled to the execution unit(s) 140. The data cache is used to store recently used / operated items, such as data operands potentially held in memory coherence states. The D-TLB is used to store recently performed virtual / linear-to-physical address translations. As a specific example, a processor may include a page table structure to partition physical memory into a plurality of virtual pages.

[0018] Here, cores 101 and 102 share access to higher-level or more distant cache, such as second-level cache associated with on-chip interface 110. Note that higher-level or more distant refers to cache levels increasing or being farther away from the execution unit(s). In one embodiment, a higher-level cache is a last-level data cache—the last cache in the memory hierarchy on processor 100—such as a second- or third-level data cache. However, higher-level cache is not so limited, as it may be associated with or include an instruction cache. Instead, a trace cache—a type of instruction cache—may be coupled after decoder 125 to store recently decoded traces. Here, an instruction potentially refers to a macroinstruction (i.e.,a general instruction recognized by the decoders) that can be decoded into a number of microinstructions (microoperations).

[0019] In the depicted configuration, processor 100 also includes an on-chip interface module 110. Historically, a memory controller, described in more detail below, was included in a computing system external to processor 100. In this scenario, on-chip interface 110 is intended to communicate with devices external to processor 100, such as system memory 175, a chipset (which often includes a memory control hub to connect to memory 175 and an I / O control hub to connect to peripheral devices), a memory control hub, a northbridge, or another integrated circuit. And in this scenario, a bus 105 may include any known connection, such as a multi-drop bus, a point-to-point connection, a serial connection, a parallel bus, a coherent (e.g.,cache-coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0020] Memory 175 may be dedicated to processor 100 or shared with other devices in a system. Common examples of memory 175 types include DRAM, SRAM, non-volatile memory (NV memory), and other known memory devices. It should be noted that device 180 may include a graphics accelerator, a processor or card coupled to a memory control hub, data storage coupled to an I / O control hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

[0021] Recently, however, as more logic and devices are integrated into a single die, such as an SOC, each of these devices may be incorporated into the processor 100. For example, in one embodiment, a memory control hub is in the same package and / or die as the processor 100. Here, a portion of the core (an on-core portion) 110 includes one or more controllers for interfacing with other devices, such as memory 175 or a graphics device 180. The configuration that includes interconnection and controllers for interfacing with such devices is often referred to as an on-core (or uncore) configuration. For example, the on-chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point interconnect 105 for off-chip communication.However, in the SOC environment, even more devices, such as the network interface, coprocessors, memory 175, graphics processor 180, and any other known computing devices / interfaces, may be integrated into a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0022] In one embodiment, processor 100 is capable of executing compiler, optimization, and / or translation code 177 to compile, translate, and / or optimize application code 176 to support or interface with the apparatus and methods described herein. A compiler often includes a program or set of programs to translate source text / code into target text / code. Typically, compilation of program / application code with a compiler occurs in multiple phases and takes place to convert high-level programming language code into low-level machine / assembly language code. However, single-pass compilers can still be used for simple compilation.A compiler can use any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0023] Larger compilers often include multiple phases, but most commonly these phases are contained within two general phases: (1) a front-end, where syntax processing, semantic processing, and some conversion / optimization can generally take place; and (2) a back-end, where analysis, conversions, optimizations, and code generation generally take place. Some compilers refer to a middle phase, illustrating the blurring of the line between a front-end and a back-end of a compiler. Consequently, a reference to an insertion, allocation, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc.in one or more compilation phases, such as inserting calls / operations in a front-end compilation phase and then converting the calls / operations into lower-level code during a conversion phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations / calls as well as optimize the code for runtime execution. As a concrete illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

[0024] The following detailed description makes reference to the accompanying drawings. The same reference numerals may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth, such as specific structures, architectures, interfaces, techniques, etc., in order to provide a thorough understanding of various aspects of various embodiments. However, it will be apparent to one of ordinary skill in the art having access to the present disclosure that the various aspects of the various embodiments may be implemented in other examples that depart from these specific details.In certain instances, descriptions of well-known devices, circuits, and methods are omitted in order not to obscure the description of the various embodiments with unnecessary detail.

[0025] Current software and hardware interface overhead prevents the effective use of enhanced mass storage device capabilities, such as mass storage used as memory. This disclosure relates to exposing mass storage devices as coherent memory accessible directly from the core using hardware capabilities. The disclosure includes using a field programmable gate array (FPGA) integrated into a processor to leverage the programmable logic in the FPGA to create a system agent in the coherence domain to extend memory semantics to the mass storage device via PCIe.

[0026] Today, storage is a long-latency device that is programmed and accessed by the core using a device model. This translates to long-latency I / O interfaces (doorbells, interrupts) and a software stack with multiple layers of storage. This disclosure exposes storage (particularly low-latency NVM technologies and low-device access latency) as coherent memory. This allows for the release of a massive amount of memory to the system, benefiting many applications such as in-memory databases, and provides low-latency storage for many big data applications.

[0027] Fig. 2 is a schematic diagram 200 of an exemplary multi-chip platform (MCP) 202 including a field programmable gate array (FPGA) 204 and a system agent 206 according to embodiments of the present disclosure. The MCP 202 includes a processor 212. The processor 212 may be a hardware processor, such as a microprocessor. The processor 212 includes a system agent 214 configured to execute memory access instructions from, for example, an application 228. The application 228 may make mass storage access requests 232 and memory access requests 230, each of which may be processed by the processor 212 (or more specifically, the system agent 214). A system agent may access the mass storage 226 through a PCIe interface 224 or through other interfaces, such as a Serial Advanced Technology Attachment (SATA) compliant connection.The memory accesses are routed by the system agent 214 to the DDR interface 234, by the system agent 214 and the memory controller 207 or other home agents in the coherence area.

[0028] The MCP 202 also includes an FPGA 204. The FPGA 204 includes a system agent 206 implemented in hardware, such as by digital design. The system agent 206 is configured to execute memory access instructions. The system agent 206 may detect the physical addresses for its channels to execute memory access requests through a QPI- or UPI-compliant connection 216. The system agent 206 translates the physical address into a channel address and forwards it to a memory controller 207. A system agent is responsible for mapping memory into processor system address space. A system agent 206 may also be responsible for managing coherency between caches in the system. Each memory controller 207 maintains a table to figure out what to do with each set of channel addresses it handles. The system agent 206 may offer an address space to the system agent 214.System Agent 214 can forward memory access requests to the offered address spaces to System Agent 206.

[0029] Aspects of this disclosure relate to the system agent 206 incorporated into the FPGA 204. The system agent 206 is configured to conform to the processor's QuickPath Interconnect (QPI) or UltraPath Interconnect (UPI) coherency domain and to participate in memory transactions on behalf of the mass storage device 210 connected by the HSSI (High-Speed ​​Serial Interface) 208. The system agent 206 releases and manages the mass storage device 210 used as memory, to which it is connected by the HSSI 208. The system agent 206 participates in memory transactions through the QPI / UPI protocols 216 and responds to messages related to the memory behind it.

[0030] The System Agent 206 also manages the directory structure stored either in its own memory or in the DRAM connected to the processor, and optionally caches it in the FPGA Block RAM 234.

[0031] The System Agent 206 is designed to operate as a hardware design that couples a mass storage used as memory to a processor through a hardware-based coherence protocol.

[0032] When a memory request arrives at system agent 214, system agent 214 may identify system agent 206 as an entity responsible for processing the memory access request. For example, system agent 214 may identify system agent 206, which is part of FPGA 204, to process the memory access request. System agent 206 may process the memory access request by accessing the appropriate address from the mass storage element(s) 210 used as memory through HSSI 208.

[0033] Although shown as an MCP, a single-chip platform, such as an application-specific integrated circuit, may also be used. Embodiments may extend beyond an FPGA implementation to include any accelerator that can interface with a processor and storage, and may include a hardware system agent. Other examples of such accelerators may include special-purpose accelerator chips or general-purpose computation on graphics processing units (GPGPUs).

[0034] Fig. 3 is a schematic diagram 300 of another example multi-chip platform 302 including a field programmable gate array 304 and a system agent 306 according to embodiments of the present disclosure. In some embodiments, the FPGA 304 supports direct mapping 314 of memory RD / WR transactions 328 by the system agent 306 into the memory controller 316, providing additional flow control. The FPGA 304 also includes one or more accelerator circuits 308 for performing inline processing of data (either reading or writing data).

[0035] The FPGA 304 may include a 4 KB line cache 312. The 4 KB line cache 312 may cache blocks of data from the mass storage 210. In some embodiments, memory read and write operations may declare long latency by using asynchronous read / write commands. The system agent 214 may send a read acknowledgment to the processor 214. The read acknowledgment may be sent during the latency of the read execution, allowing the processor 212 to proceed to the next processing steps. The system agent 306 may cache the block of data retrieved from the mass storage 210 into the line cache 312. Likewise, the system agent 306 may provide a write acknowledgment and cache the write data in the line cache 312 and then cache write data in the mass storage device 210 used as memory.

[0036] The system agent 306 can also cache data supplied from the mass storage 210 in larger block sizes (in 4 KB blocks in the 4 KB line cache 312 instead of the 64 B request on the cache line).

[0037] A directory cache 310 may provide additional performance by holding a portion or subset of the memory directory. The directory cache 310 may be part of the FPGA 304 that caches a portion of the memory directory—the memory represented by the potentially several terabytes (or more) of available storage.

[0038] In embodiments, the FPGA 304 can emulate a PCIe root complex. By emulating the PCIe root complex and the PCIe interface, the system agent 306 can directly release memory in the mass storage 210 used as memory.

[0039] In some implementations, an existing PCIe IP in the FPGA 304 connects to existing PCIe-based storage solutions. To extend coherent memory to the device side, the QPI messages are channeled through the PCIe protocol. Instead of handling Non-Volatile Memory Express (NVMe) protocols 326 over PCIe, the controller must handle RD / WR transactions over PCIe.

[0040] Fig. 4 is a schematic diagram 400 of an exemplary multi-chip platform 402 including a field programmable gate array 404 and a system agent 406, illustrating inline accelerator circuitry according to embodiments of the present disclosure. Embodiments include inline accelerators 414a and 414b built into the FPGA 404 to perform memory-side streaming acceleration (e.g., encryption / decryption, compression / decompression, Structured Query Language (SQL) acceleration, Extract-Transform-Load (ETL) functions, etc.). The accelerators 414a and 414b may utilize an optional cache 412 and a cache controller 410 built into the FPGA logic to improve performance.

[0041] Fig. Figure 4 also illustrates how certain memory control components may be moved to the FPGA 404 to free up mass storage as memory 210. The FPGA 404 may include a memory controller 416 that includes a 4 KB cache memory 418. The FPGA 404 may also include the NVMe driver 420 as a hardware circuit design that emulates NVMe driver functionality.

[0042] Similar to the embodiments shown above, the processor 212 may include a system agent 214 that may interface with the FPGA 404 via a QPI-compliant connection, such as a UPI connection 218. The FPGA 404 is shown including a UPI interface 408 that may facilitate QPI-compliant (or UPI-specific) protocols between the system agent 406 or the caching agent 410 and the system agent 214. It should be understood that the FPGA generally described herein would include a protocol interface, such as a UPI interface 408, to facilitate communication between the system agent 214 and FPGA components, such as the system agent 406.

[0043] Fig. 5A is a schematic diagram 500 of an exemplary multi-chip platform 502 including a field programmable gate array 504 and a system agent 506 for connecting to a fabric-attached mass storage device used as memory, according to embodiments of the present disclosure. Fig. 5B is a schematic diagram 550 of an exemplary fabric-attached memory storage according to embodiments of the present disclosure. In embodiments of this disclosure, fabric-attached memory (or traditional DRAM memory) may be shared as memory. In this scenario, the HSSI 208 is connected to the external fabric, which drives memory transactions via the fabric protocols. Memory expansion could be used to share disaggregated memory storage 516 or disaggregated memory 518 across a fabric.

[0044] The FPGA 504 may include a fabric interface 514, which may provide hardware steps that emulate a fabric interface. The FPGA 504 may also include an NVMe driver 512 to provide memory access across the HSSI 208. In embodiments, the NVMe driver 512 or the fabric 514 may include circuitry that emulates the PCIe interface, enabling the NVMe driver 512 to perform memory RD / WR across the HSSI 208. The FPGA 504 may also include a cache 510 and a memory controller 508 coupled to the system agent 506.

[0045] Fig. 5B illustrates exemplary disaggregated storage 516 and disaggregated memory 518. Disaggregated memory 516 may include a plurality of networked storage devices 520. Disaggregated memory 518 may include a plurality of networked memory elements 522.

[0046] Although the fabric shown here has a 2D mesh topology, it can be replaced with any topology based on scaling requirements. Furthermore, the HSSI 208 can be extended to support larger bandwidths, particularly if DRAMs 522 are connected to the fabric. The components shown as implemented in an FPGA may ultimately be integrated into the processor as hardened logic for power / performance reasons.

[0047] For performance and potential functional issues with long-latency memory reads, asynchronous support can be used. This means that the system agent can issue and complete the command to the processor with a non-data response, rather than an asynchronous read providing a data response. The data is then received via user-level MWAIT, triggered by the arrival of the data at the 4 KB line cache in the FPGA.

[0048] Fig. 6A is a process flow diagram 600 for processing a memory access request according to embodiments of the present disclosure. The process may be performed by a field programmable gate array (FPGA) or one or more components of the FPGA, such as a hardware implementation of a system agent. For example, the system agent may receive a memory access request from another system agent of a processor coupled to the FPGA by a QuickPath Interconnect (QPI)-compliant interconnect, such as an UltraPath Interconnect (UPI)-compliant interconnect (602). The system agent may identify a memory location in an attached memory storage device via a high-speed serial interface (HSSI) (604) and execute the memory access request (606).

[0049] Fig. 6B is a process flow diagram 610 for asynchronous memory access execution according to embodiments of the present disclosure. The process may be performed by a field programmable gate array (FPGA) or one or more components of the FPGA, such as a hardware implementation of a system agent. For example, the system agent may receive a memory access request from another system agent of a processor coupled to the FPGA through a QuickPath Interconnect (QPI)-compliant interconnect, such as an UltraPath Interconnect (UPI)-compliant interconnect (612). The system agent may identify a memory location in an attached memory storage device via a high-speed serial interface (HSSI) (614) to execute the memory access request (616).

[0050] The system agent may then provide the requesting system agent with an acknowledgment of the execution of the memory access request (618). In embodiments, the acknowledgment may include a read acknowledgment. The system agent may cache the read data in a line cache in the FPGA (620) and transmit the read data from the FPGA line cache at a later time (622).

[0051] In embodiments, the system agent may provide a write acknowledgement and may cache the write data in a line cache in the FPGA and store the write data in a cache at a later time.

[0052] Fig. 6C is a process flow diagram 630 for performing inline data processing according to embodiments of the present disclosure. The process may be performed by a field programmable gate array (FPGA) or one or more components of the FPGA, such as a hardware implementation of a system agent. For example, the system agent may receive a memory access request from another system agent of a processor coupled to the FPGA by a QuickPath Interconnect (QPI)-compliant interconnect, such as an UltraPath Interconnect (UPI)-compliant interconnect (632). The system agent may identify a memory location in an attached mass storage device used as memory (634). The system agent may direct data (either read or write data) to one or more accelerator circuits that are part of the FPGA (636). The one or more accelerator circuits may process the data (638).The system agent can then either provide the data to the processor (for a read command) or can store the processed data in memory (for write commands) (640).

[0053] Aspects of the present disclosure expose low-latency large-capacity (mass storage) devices as memory over a non-DDR interface, the benefit of which includes accessing high-capacity memory with traditional memory RD / WR semantics without sacrificing high-performance DDR interfaces. This has the potential to improve application performance when massive computations occur in memory.

[0054] One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to allow components and devices from different vendors to interoperate in an open architecture that spans multiple market segments: clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices. PCI Express is a high-performance, general-purpose I / O interconnect defined for a wide range of future computing and communications platforms. Some PCI attributes, such as the usage model, load / store architecture, and software interfaces, have been retained across revisions, whereas earlier parallel bus implementations have been replaced by a highly scalable, fully serial interface.The newer versions of PCI Express take advantage of advances in point-to-point connections, switch-based technology, and packetized protocols to create new levels of performance and features. Power management, Quality of Service (QoS), hot-plug / hot-swap support, data integrity, and error handling are some of the advanced features supported by PCI Express.

[0055] Referring to Fig. Figure 7 illustrates one embodiment of a fabric composed of point-to-point interconnects connecting a set of components. System 700 includes a processor 705 and system memory 710 coupled to a control hub 715. Processor 705 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or another processor. Processor 705 is coupled to control hub 715 by front side bus (FSB) 706. In one embodiment, FSB 706 is a serial point-to-point interconnect, as described below. In another embodiment, interconnect 706 includes a serial differential interconnect architecture compliant with various interconnect standards.

[0056] System memory 710 includes any memory device, such as random access memory (RAM), non-volatile memory (NVM), or other memory accessible to devices in system 700. System memory 710 is coupled to control hub 715 through memory interface 716. Examples of a memory interface include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic random access memory (DRAM) memory interface.

[0057] In one embodiment, control hub 715 is a root hub, a root complex, or a root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of control hub 715 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root controller / hub. Often, the term chipset refers to two physically separate control hubs, i.e., a memory control hub (MCH) coupled to an interconnect control hub (ICH). It should be noted that current systems often include the MCH as integrated with processor 705, while controller 715 is intended to communicate with I / O devices in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported by root complex 715.

[0058] Here, the control hub 715 is coupled to the switch / bridge 720 through a serial connection 719. The input / output modules 717 and 721, which may also be referred to as interfaces / ports 717 and 721, include / implement a layered protocol stack to provide communication between the control hub 715 and the switch 720. In one embodiment, multiple devices are capable of being coupled to the switch 720.

[0059] The switch / bridge 720 routes packets / messages from the device 725 upstream, i.e., up one hierarchy toward a root complex, to the control hub 715, and downstream, i.e., down one hierarchy away from a root controller, from the processor 705 or system memory 710 to the device 725. The switch 720, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices.Device 725 includes any internal or external device or component to be coupled to an electronic system, such as an I / O device, a network interface controller (NIC), an expansion card, an audio processor, a network processor, a hard disk, a mass storage device, a CD / DVD-ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable mass storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices. In PCIe jargon, such a device is often referred to as an endpoint. Although not specifically shown, device 725 may include a PCIe-to-PCI / PCI-X bridge to support legacy or different version PCI devices.Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.

[0060] Graphics accelerator 730 is also coupled to control hub 715 through serial connection 732. In one embodiment, graphics accelerator 730 is coupled to an MCH, which is coupled to an ICH. Switch 720, and correspondingly, I / O device 725, is then coupled to the ICH. I / O modules 731 and 718 are also intended to implement a layered protocol stack to provide communication between graphics accelerator 730 and control hub 715. Similar to the MCH discussion above, a graphics controller or graphics accelerator 730 itself may be integrated into processor 705.

[0061] Referring to Fig. 8, one embodiment of a layered protocol stack is illustrated. The layered protocol stack 800 includes any form of layered communication stack, such as a QuickPath Interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computing interconnect stack, or another layered stack. Although the immediately following discussion is with reference to the Fig. 7-10 with respect to a PCIe stack, but the same concepts can be applied to other interconnect stacks. In one embodiment, protocol stack 800 is a PCIe protocol stack that includes a transaction layer 805, a link layer 810, and a physical layer 820. An interface, such as interfaces 717, 718, 721, 722, 726, and 731 in Fig. 7, can be represented as a communication protocol stack 800. The representation as a communication protocol stack can also be referred to as a module or interface that implements / includes a protocol stack.

[0062] PCI Express uses packets to transmit information between components. Packets are formed in the transaction layer 805 and the data link layer 810 to carry the information from the transmitting component to the receiving component. As the transmitted packets pass through the other layers, they are expanded with additional information required to handle packets at those layers. On the receiving side, the reverse process occurs, and packets are converted from their physical layer 820 representation to the data link layer 810 representation and finally (for transaction layer packets) to the form that can be processed by the transaction layer 805 of the receiving device. Transaction layer

[0063] In one embodiment, the transaction layer 805 is intended to provide an interface between a processing core of a device and the interconnect architecture, such as the data link layer 810 and the physical layer 820. In this regard, a primary responsibility of the transaction layer 805 is the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). The translation layer 805 typically manages credit-based flow control for TLPs. PCIe implements split transactions, i.e., transactions in which the request and response are separated in time, allowing a connection to carry other traffic while the destination device gathers data for the response.

[0064] In addition, PCIe uses credit-based flow control. In this scheme, a device offers an initial credit amount for each of the receive buffers in the transaction layer 805. An external device at the other end of the connection, such as a control hub 715 in Fig. 7, the amount of credit consumed by each TLP is counted. A transaction can be committed if the transaction does not exceed a credit limit. Upon receiving a response, a credit amount is returned. One advantage of a credit scheme is that the latency of credit return does not affect performance, provided the credit limit is not reached.

[0065] In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to / from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of PCIe devices. Transactions into the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0066] Therefore, in one embodiment, the transaction layer 805 assembles a packet header / payload 806. The format for current packet headers / payloads can be found in the PCIe specification on the PCIe specification website.

[0067] Briefly referring to Fig. Figure 9 illustrates an embodiment of a PCIe transaction descriptor. In one embodiment, transaction descriptor 900 is a mechanism for maintaining transaction information. In this regard, transaction descriptor 900 supports the identification of transactions within a system. Other potential uses include tracking modifications during the ordering of standard transactions and associating transactions with channels.

[0068] The transaction descriptor 900 includes a global identifier field 902, an attribute field 904, and a channel identifier field 906. In the illustrated example, the global identifier field 902 is mapped to include a local transaction identifier field 908 and a source identifier field 910. In one embodiment, the global transaction identifier 902 is unique for all outstanding requests.

[0069] According to one implementation, the local transaction identifier field 908 is a field generated by a requesting agent, and it is unique for all outstanding requests requiring completion for that requesting agent. Further, in this example, the source identifier 910 uniquely identifies the requesting agent within a PCIe hierarchy. Accordingly, the local transaction identifier field 908, together with the source ID 910, provides a global identification of a transaction within a hierarchy scope.

[0070] The attribute field 904 specifies properties and relationships of the transaction. In this regard, the attribute field 904 is potentially used to provide additional information that enables modification of the standard transaction handling. In one embodiment, the attribute field 904 includes a priority field 912, a reserved field 914, a sort field 916, and a no-snoop field 918. Here, the priority subfield 912 can be modified by an initiator to assign a priority to the transaction. The reserved attribute field 914 is reserved for future or vendor-defined use. Possible usage models using priority or security attributes can be implemented using the reserved attribute field.

[0071] In this example, the sort attribute field 916 is used to provide optional information conveying the type of sorting, which can modify standard sorting rules. According to an example implementation, a command attribute of "0" indicates that standard sorting rules are to be applied, whereas a sort attribute of "1" indicates relaxed ordering, where writes in the same direction can overtake writes and read completions in the same direction can overtake writes. The snoop attribute field 918 is used to determine whether transactions are snooped. As shown, the channel ID field 906 identifies a channel with which a transaction is associated. Data link layer

[0072] Now referring again to Fig. 8, the link layer 810, also referred to as the data link layer 810, acts as an intermediate layer between the transaction layer 805 and the physical layer 820. In one embodiment, a responsibility of the data link layer 810 provides a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a link. One side of the data link layer 810 accepts TLPs assembled from the transaction layer 805, applies the packet sequence identifier 811, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., CRC 812, and presents the modified TLPs to the physical layer 820 for transmission over a physical device to an external device. Physical layer

[0073] In one embodiment, physical layer 820 includes a logical subblock 821 and an electrical subblock 822 for physically transmitting a packet to an external device. Here, logical subblock 821 is responsible for the "digital" functions of physical layer 821. In this regard, the logical subblock includes a transmit section to prepare outgoing information for transmission by physical subblock 822 and a receive section to identify and prepare received information before forwarding it to link layer 810.

[0074] Physical block 822 includes a transmitter and a receiver. The transmitter receives symbols from logical subblock 821, which the transmitter serializes and transmits to an external device. Serialized symbols from an external device are supplied to the receiver, and the receiver converts the received signals into a bit stream. The bit stream is deserialized and supplied to logical subblock 821. In one embodiment, an 8b / 10b transmission code is used, with ten-bit symbols being transmitted / received. Here, special symbols are used to frame a packet with frames 823. In addition, in one example, the receiver also provides a symbol clock obtained from the incoming serial stream.

[0075] Although the transaction layer 805, the data link layer 810, and the physical layer 820 are discussed with reference to a specific embodiment of a PCIe protocol stack, as stated above, a layered protocol stack is not so limited. Indeed, it may include / implement any layered protocol. For example, a port / interface represented as a layered protocol includes: (1) a first layer to assemble packets, i.e., a transaction layer; a second layer to sequence packets, i.e., a data link layer; and a third layer to transmit the packets, i.e., a physical layer. As a specific example, a layered Common Standard Interface (CSI) protocol is used.

[0076] Next, referring to Fig. Figure 10 illustrates an embodiment of a PCIe point-to-point serial fabric. Although an embodiment of a PCIe point-to-point serial connection is illustrated, a point-to-point serial connection is not so limited, as it includes any transmission path for transmitting serial data. In the illustrated embodiment, a simple PCIe connection includes two differentially driven low-voltage signal pairs: a transmit pair 1006 / 1011 and a receive pair 1012 / 1007. Accordingly, device 1005 includes transmit logic 1006 to transmit data to device 1010 and receive logic 1007 to receive data from device 1010. In other words, a PCIe connection contains two transmit paths, i.e., paths 1016 and 1017, and two receive paths, i.e., paths 1018 and 1019.

[0077] A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or any other communication path. A link between two devices, such as device 1005 and device 1010, is referred to as a link, such as link 415. A link may support a lane—where each lane represents a set of differential signal pairs (one pair for transmit, one pair for receive). To scale bandwidth, a link may aggregate multiple lanes, denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0078] A differential pair refers to two transmission paths, such as lines 416 and 417, for transmitting differential signals. For example, when line 416 transitions from a low voltage level to a high voltage level, i.e., a rising edge, line 417 transitions from a high logic level to a low logic level, i.e., a falling edge. Differential signals potentially exhibit better electrical properties, such as better signal integrity, i.e., crosstalk, voltage overshoot / undershoot, ringing, etc. This allows for a better timing window, allowing for faster transmission frequencies.

[0079] Referring to Fig. Figure 11 is a block diagram of an exemplary computer system configured with a processor including execution units to execute an instruction, wherein one or more of the interconnections implement one or more features according to an embodiment of the present disclosure. System 1100 includes a component, such as a processor 1102, for employing execution units including logic to perform algorithms on process data according to the present disclosure, such as in the embodiment described herein.System 1100 is representative of processing systems based on the PENTIUM III™, PENTIUM 4™, Xeon™, Itanium, XScale™, and / or StrongARM™ microprocessors available from Intel Corporation of Santa Clara, California, USA, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes, and the like) may be used. In one embodiment, sample system 1100 executes a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, USA, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may be used. Thus, embodiments of the present disclosure are not limited to any particular combination of hardware circuitry and software.

[0080] Embodiments are not limited to computer systems. Alternative embodiments of the present disclosure may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, network computers (NetPC), set-top boxes, network nodes, wide-area network (WAN) switches, or any other system capable of performing one or more instructions according to at least one embodiment.

[0081] In this illustrated embodiment, processor 1102 includes one or more execution units 1108 to implement an algorithm to perform at least one instruction. One embodiment may be described in the context of a desktop or server system having a single processor, but alternative embodiments may be included in a multiprocessor system. System 1100 is an example of a "hub" system architecture. Computer system 1100 includes a processor 1102 to process data signals. Processor 1102 includes, as an illustrative example, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor.The processor 1102 is coupled to a processor bus 1110, which transmits data signals between the processor 1102 and other components in the system 1100. The elements of the system 1100 (e.g., graphics accelerator 1112, memory control hub 1116, memory 1120, I / O control hub 1124, wireless transceivers 1126, flash BIOS 1128, network controller 1134, audio controller 1136, serial expansion port 1138, I / O controller 1140, etc.) perform their conventional functions, which are well known to one of ordinary skill in the art.

[0082] In one embodiment, processor 1102 includes an internal level 1 (L1) cache 1104. Depending on the architecture, processor 1102 may include a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches, depending on the particular implementation and requirements. Register memory 1106 is used to store different types of data in various registers, including integer registers, floating-point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

[0083] Execution unit 1108, which includes logic to perform integer and floating-point operations, also resides in processor 1102. Processor 1102, in one embodiment, includes a microcode (Ucode) ROM to store microcode that, when executed, is used to perform algorithms for specific macroinstructions or to handle complex scenarios. Here, microcode is potentially updateable to handle logic bugs / fixes for processor 1102. For one embodiment, execution unit 1108 includes logic to handle a packed instruction set 1109. By incorporating packed instruction set 1109 into the instruction set of a general-purpose processor 1102, along with associated circuitry to execute the instructions, the operations used by many multimedia applications using packed data can be performed in a general-purpose processor 1102.Thus, many multimedia applications are accelerated and run more efficiently by using the full width of a processor's data bus to perform operations on packed data. This potentially eliminates the need to transfer smaller data units across the processor's data bus to perform one or more operations, one data element at a time.

[0084] Alternative embodiments of an execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. The system 1100 includes a memory 1120. The memory 1120 includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another memory device. The memory 1120 stores instructions and / or data, represented by data signals, to be executed by the processor 1102.

[0085] It should be noted that the above-mentioned features or aspects of the disclosure may be used in one or more of the Fig. 11 may be utilized. For example, an on-die interconnect (ODI), not shown, for coupling internal devices of processor 1102 implements one or more aspects of the disclosure described above. Or, the disclosure is associated with a processor bus 1110 (e.g., Intel QuickPath Interconnect (QPI) or other known high-performance computing interconnect), a high-bandwidth memory path 1118 to memory 1120, a point-to-point connection to graphics accelerator 1112 (e.g., a Peripheral Component Interconnect Express (PCIe)-compliant fabric), a control hub connection 1122, an I / O or other connection (e.g., USB, PCI, PCIe) for coupling the other illustrated components.Some examples of such components include the audio controller 1136, the firmware hub (flash BIOS) 1128, the wireless transceiver 1126, the data storage 1124, the legacy I / O controller 1110, which includes the user input and keyboard interface 1142, a serial expansion port 1138, such as a Universal Serial Bus (USB), and a network controller 1134. The data storage device 1124 may include a hard disk drive, a floppy disk drive, a CD-ROM drive, a flash memory device, or other mass data storage device.

[0086] Now referring to Fig. 12 shows a block diagram of a second system 1200 according to an embodiment of the present disclosure. As in Fig. 12, the multiprocessor system 1200 is a point-to-point interconnect system and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. Each of the processors 1270 and 1280 may be a version of a processor. In one embodiment, 1252 and 1254 are part of a serial, coherent point-to-point interconnect fabric, such as Intel's QuickPath Interconnect (QPI) architecture. Accordingly, the disclosure may be implemented in the QPI architecture.

[0087] Although shown with only two processors 1270, 1280, it should be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

[0088] Processors 1270 and 1280 are shown as each including an integrated memory controller 1272 and 1282, respectively. Processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its bus controllers; likewise, the second processor 1280 includes PP interfaces 1286 and 1288. Processors 1270, 1280 may exchange information via a point-to-point (PP) interface 1250 using PP interface circuits 1278, 1288. As shown in Fig. 12, the IMCs 1272 and 1282 couple the processors to a respective memory, namely a memory 1232 and a memory 1234, which may be portions of main memory locally attached to the respective processors.

[0089] The processors 1270, 1280 each exchange information with a chipset 1290 via individual PP interfaces 1252, 1254 using PP interface circuits 1276, 1294, 1286, 1298. The chipset 1290 also exchanges information with a high-performance graphics circuit 1238 via an interface circuit 1292 along a high-performance graphics interconnect 1239.

[0090] A shared cache (not shown) may be included in both processors or external to both processors; yet connected to the processors via a PP interconnect, so that the local cache information of one or both processors can be stored in the shared cache if one processor is placed in a low-power mode.

[0091] The chipset 1290 may be coupled to a first bus 1216 via an interface 1296. In one embodiment, the first bus 1216 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or other third-generation I / O interconnect bus, although the scope of the present disclosure is not so limited.

[0092] As in Fig. 12, various I / O devices 1214 are coupled to the first bus 1216, along with a bus bridge 1218 that couples the first bus 1216 to a second bus 1220. In one embodiment, the second bus 1220 includes a low pin count (LPC) bus. Various devices are coupled to the second bus 1220, including, in one embodiment, for example, a keyboard and / or mouse 1222, communication devices 1227, and a mass storage device 1228, such as a disk drive or other mass data storage device, which often includes instructions / code and data 1230. Further, an audio I / O 1224 is shown coupled to the second bus 1220. It should be noted that other architectures are possible, and the included components and interconnect architectures may vary. For example, instead of the point-to-point architecture, a system may comprise Fig.12 implement a multi-drop bus or other such architecture.

[0093] Example 1 is a processor device including a microprocessor comprising a microprocessor system agent and a field programmable gate array (FPGA). The FPGA includes an FPGA system agent for processing memory access requests received from the microprocessor system agent over a communication link; a memory controller communicatively coupled to the system agent; and a high-speed serial interface for connecting the system agent to a mass storage system.

[0094] Example 2 may include the subject matter of Example 1, wherein the communication link conforms to a QuickPath interconnect protocol.

[0095] Example 3 may include the subject matter of Example 1, wherein the FPGA further comprises hardware logic to emulate a Peripheral Component Interconnect Express (PCIe)-compliant root complex, wherein the hardware logic emulates a PCIe protocol through one or more hardware operations, and wherein the system agent is configured to process memory access requests over the high-speed serial interface using a PCIe-compliant protocol.

[0096] Example 4 may include the subject matter of any of Examples 1-3, wherein the FPGA comprises one or more accelerator circuits to perform processing of data transferred between the microprocessor and the mass storage system.

[0097] Example 5 may include the subject matter of Example 4, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, Structured Query Language (SQL) acceleration, or Extract-Transform-Load (ETL) operations.

[0098] Example 6 may include the subject matter of Example 4, wherein the FPGA further comprises a caching agent and a memory cache to cache data for the one or more accelerator circuits.

[0099] Example 7 may include the subject matter of any of Examples 1-6, wherein the FPGA includes a directory cache to store a subset of a mass storage directory in the FPGA.

[0100] Example 8 may include the subject matter of any of Examples 1-7, wherein the FPGA includes a cache line to cache data stored in the mass storage.

[0101] Example 9 may include the subject matter of any of Examples 1-8, wherein the FPGA comprises a fabric interface, wherein the fabric interface is to interface with a disaggregated storage system supported by a network fabric.

[0102] Example 10 may include the subject matter of any of Examples 1-9, wherein the FPGA comprises a Non-Volatile Memory Express (NVMe) memory controller to interface with an NVMe controller on a connected mass storage device via a High-Speed ​​Serial Interface (HSSI).

[0103] Example 11 is a method performed by a hardware element of a processor, the method comprising receiving a memory command from a hardware processor at a system agent implemented in a field programmable gate array (FPGA); identifying a memory location managed by the system agent, the memory location being part of a mass storage device communicatively coupled to the FPGA; executing the memory command; and providing an acknowledgment of the memory command execution to the hardware processor.

[0104] Example 12 may include the subject matter of Example 11 and may also include retrieving data stored in memory via a high-speed serial interface.

[0105] Example 13 may include the subject matter of Example 12 and may also include transferring data from the FPGA from memory to the hardware processor via a communication link.

[0106] Example 14 may include the subject matter of Example 11, wherein the confirmation of memory instruction execution comprises an asynchronous confirmation response.

[0107] Example 15 may include the subject matter of Example 14 and may also include retrieving data from the mass storage used as memory; transmitting a read response to the hardware processor; caching the data in a cache memory; and, after transmitting the read response to the hardware processor, transmitting the data from the cache memory to the hardware processor.

[0108] Example 16 may include the subject matter of Example 11 and may also include caching data retrieved from the working memory location in a cache in the FPGA.

[0109] Example 17 may include the subject matter of Example 11 and may also include offering a memory address space managed by the system agent implemented in the FPGA to a system agent of the hardware processor.

[0110] Example 18 may include the subject matter of Example 11 and may also include performing data processing on data incoming to the FPGA and / or data outgoing from the FPGA by one or more accelerator circuits.

[0111] Example 19 may include the subject matter of Example 18, wherein the data processing comprises performing one or more of compression and / or decompression, encryption and / or decryption, Structured Query Language (SQL) acceleration, or Extract-Transform-Load (ETL) operations.

[0112] Example 20 may include the subject matter of Example 11 and may also include receiving a memory access request at the FPGA system agent from a system agent associated with the hardware processor; determining a memory location for a disaggregated memory element of a fabric of memory elements; and processing the memory access request based on the determined memory location.

[0113] Example 21 is a system including a microprocessor including a microprocessor system agent and an accelerator system. The accelerator system includes a system agent to process memory access requests received from the microprocessor system agent over a communication link. The accelerator system also includes a memory controller communicatively coupled to the system agent. The accelerator system also includes a high-speed serial interface to connect the system agent to a mass storage system. The system also includes a mass storage device connected to the accelerator system through the high-speed serial interface.

[0114] Example 22 may include the subject matter of Example 21, wherein the mass storage device comprises a non-volatile solid-state drive (SSD) storage element.

[0115] Example 23 may include the subject matter of Example 21, wherein the accelerator system comprises a fabric interconnect; and wherein the storage device comprises disaggregated memory storage, the disaggregated memory storage comprising a plurality of non-volatile solid-state drive memory elements managed by a network fabric, the fabric coupled to the accelerator system by the fabric interconnect.

[0116] Example 24 may include the subject matter of Example 21, wherein the accelerator system comprises one or more accelerator circuits to perform processing of data transferred between the microprocessor and the mass storage system.

[0117] Example 25 may include the subject matter of Example 24, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, Structured Query Language (SQL) acceleration, or Extract-Transform-Load (ETL) operations.

Claims

[1] Processor device (202, 302, 402, 502), comprising: a microprocessor (212) comprising a microprocessor system agent (214); and a Field Programmable Gate Array (FPGA) (204, 304, 404, 504), wherein the FPGA (204, 304, 404, 504) comprises: an FPGA system agent (206, 306, 406, 506) for processing memory access requests (230) received from the microprocessor system agent (214) via a communication link (216, 218), wherein the FPGA system agent (206, 306, 406, 506) and the communication link (216, 218) are in a coherence region of the microprocessor (212); a memory controller (207, 316, 416, 508) communicatively coupled to the system agent (206, 306, 406, 506); a high-speed serial interface (208) for connecting the system agent (206, 306, 406, 506) to a mass storage system (218); wherein the FPGA system agent (206, 306, 406, 506) processes the memory access requests (230) by translating addresses in the memory access requests (230) into the addresses of the mass storage system (218) and accesses data at the addresses of the mass storage system (218) through a high-speed serial interface (208). [2] The processor device (202) of claim 1, wherein the communication link (216) conforms to a QuickPath Interconnect protocol. [3] The processor device (202) of claim 1, wherein the FPGA (204) further comprises hardware logic to emulate a Peripheral Component Interconnect Express (PCIe)-compliant root complex, wherein the hardware logic emulates a PCIe protocol through one or more hardware operations, and wherein the system agent (206, 306, 406, 506) is configured to process memory access requests via the high-speed serial interface using a PCIe-compliant protocol. [4] The processor device (202, 302) of claim 1, wherein the FPGA (204, 304) comprises one or more accelerator circuits (308) to perform the processing of data transferred between the microprocessor (212) and the mass storage system (218). [5] The processor device (202, 302) of claim 4, wherein the one or more accelerator circuits (308, 414a, 414b) are configured to perform one or more of compression and / or decompression, encryption and / or decryption, Structured Query Language (SQL) acceleration, or Extract-Transform-Load (ETL) operations. [6] The processor device (202) of claim 4, wherein the FPGA (204, 404) further comprises a caching agent (410) and a memory cache to cache data for the one or more accelerator circuits (414a, 414b). [7] The processor device (202) of claim 1, wherein the FPGA (204, 304, 404, 504) includes a directory cache to store a subset of a mass storage directory in the FPGA (204, 304, 404, 504). [8] The processor device (202, 302) of claim 1, wherein the FPGA (204, 304) includes a cache line (312) for caching data stored in the mass storage (210). [9] The processor device (202, 502) of claim 1, wherein the FPGA (204, 504) comprises a fabric interface (514), the fabric interface (514) being to interface with a disaggregated mass storage system (518) supported by a network fabric. [10] The processor device (202) of claim 1, wherein the FPGA comprises a Non-Volatile Memory Express (NVMe) memory controller to interface with an NVMe controller on a connected mass storage device via a High-Speed ​​Serial Interface (HSSI). [11] A method (600, 610, 630) performed by a hardware element of a processor, the method (600, 610, 630) comprising: Receiving (602) a memory command via a communication link (216, 218) from a hardware processor (212) at a system agent (214) implemented in a field programmable gate array (FPGA) (204, 304, 404, 504), wherein the FPGA system agent (206, 306, 406, 506) and the communication link (216, 218) are in a coherence region of the hardware processor (212); translating an address in the memory command to identify (604) a memory location managed by the system agent (214), the memory location being part of a mass storage device (210) communicatively coupled to the FPGA (204, 304, 404, 504); Executing (606) the memory instruction; and Providing (618) an acknowledgment of memory instruction execution to the hardware processor (212). [12] The method (600, 610, 630) of claim 11, further comprising retrieving data stored in memory via a high-speed serial interface. [13] The method (600, 610, 630) of claim 12, further comprising transferring from the FPGA (204, 304, 404, 504) data from the memory to the hardware processor via a communication link. [14] The method (600, 610, 630) of claim 11, wherein the confirmation of memory command execution comprises an asynchronous confirmation response. [15] The method (600, 610, 630) of claim 14, further comprising: Retrieving data from the mass storage used as main memory (210); Transmitting a read response to the hardware processor (212); Caching the data in a cache memory; and, after transmitting the read response to the hardware processor (212), transmitting the data from the cache memory to the hardware processor (212). [16] The method (600, 610, 630) of claim 11, further comprising caching data retrieved from the working memory location in a cache in the FPGA (204, 304, 404, 504). [17] The method (600, 610, 630) of claim 11, further comprising offering a memory address space managed by the system agent (206, 306, 406, 506) implemented in the FPGA (204, 304, 404, 504) to a system agent (214) of the hardware processor (212). [18] The method (600, 610, 630) of claim 11, further comprising performing data processing (636) of data incoming to the FPGA (204, 304, 404, 504) and / or data outgoing from the FPGA (204, 304, 404, 504) by one or more accelerator circuits (308, 4141a, 414b). [19] The method (600, 610, 630) of claim 18, wherein the data processing comprises performing one or more of compression and / or decompression, encryption and / or decryption, Structured Query Language (SQL) acceleration, or Extract-Transform-Load (ETL) operations. [20] The method of claim 11, further comprising: Receiving a memory access request at the FPGA system agent (206, 306, 406, 506) from a system agent (214) associated with the hardware processor (212); Determining a memory location for a disaggregated memory element of a fabric of memory elements; and Process the memory access request based on the determined memory location. [21] System comprising: a microprocessor (212) comprising a microprocessor system agent (214); a Field Programmable Gate Array (FPGA) (204, 304, 404, 504), wherein the FPGA (204, 304, 404, 504) comprises: an FPGA system agent (206, 306, 406, 506) for processing memory access requests received from the microprocessor system agent (214) via a communication link, wherein the FPGA system agent (206, 306, 406, 506) and the communication link (216, 218) are in a coherence region of the microprocessor (212); a memory controller communicatively coupled to the system agent (206, 306, 406, 506); and a high-speed serial interface (208) for connecting the system agent (206, 306, 406, 506) to a mass storage system (210, 516, 518); and a mass storage device connected to the FPGA (204, 304, 404, 504) through the high-speed serial interface; wherein the FPGA system agent (206, 306, 406, 506) processes the memory access requests (230) by translating addresses in the memory access requests (230) into the addresses of the mass storage system (218) and accesses data at the addresses of the mass storage system (218) through the high-speed serial interface (208). [22] The system of claim 21, wherein the mass storage device comprises a non-volatile solid-state drive (SSD) storage element. [23] The system of claim 21, wherein the FPGA (204, 304, 404, 504) comprises a fabric interconnect (514); and wherein the mass storage device comprises disaggregated memory storage, the disaggregated memory storage comprising a plurality of non-volatile solid-state drive memory elements managed by a network fabric, the fabric being coupled to the FPGA (204, 304, 404, 504) by the fabric interconnect (514). [24] The system of claim 21, wherein the FPGA (204, 304, 404, 504) comprises one or more accelerator circuits (308, 414a, 414b) to perform processing of data transferred between the microprocessor (212) and the mass storage system. [25] The system of claim 24, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, Structured Query Language (SQL) acceleration, or Extract-Transform-Load (ETL) operations.

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