SILICON CARBIDE SEMICONDUCTOR ELEMENT

Abstract

Semiconductor component (100, 500) that exhibits: a SiC semiconductor body (102); a first load connection (L1) on a first surface (104) of the SiC semiconductor body (102); a second load terminal (L2) on a second surface (106) of the SiC semiconductor body (102) opposite the first surface (102); a drift zone (112) of a first conductivity type in the SiC semiconductor body (102); a first semiconductor region (110) of a second conductivity type, which is electrically connected to the first load terminal (L1), wherein a pn junction between the drift zone (112) and the first semiconductor region (110) defines a voltage breaker strength of the semiconductor device (100, 500); and a second semiconductor region (114) of the second conductivity type between at least a part of the drift zone (112) and the second surface (106), wherein dopants of the second semiconductor region (114) comprise deep defects whose energy distance to the nearest band edge is more than 160 meV, and wherein the second semiconductor region (114) has a vertical extent (v) in a range from 20 nm to 1 µm.

Description

TECHNICAL FIELD

[0001] The present application relates to SiC (silicon carbide) semiconductor components, for example semiconductor switches with low on-resistance and high dielectric strength. BACKGROUND

[0002] Wide-bandgap semiconductor components are based on a semiconductor material with a bandgap of at least 2 eV or at least 3 eV and, compared to conventional silicon-based semiconductor devices, enable lower on-resistance, high-temperature operation, lower switching losses, and / or lower leakage currents. Examples of semiconductor components are known from the publications DE 10 2006 025 958 B3, DE 690 11 809 T2, DE 102 20 359 A1, and DE 10 2007 057 728 A1. When designing SiC semiconductor components, a variety of different component parameters, such as doping and dimensioning of semiconductor regions, must be optimized with respect to required component properties such as on-resistance or turn-off behavior.For example, compromises must be made regarding the required component properties, since changing a component parameter can have different effects on the component properties, e.g., leading to an improvement in one component property while simultaneously deteriorating another. Against this background, the application addresses the improvement of the turn-off process of SiC semiconductor components. SUMMARY

[0003] The invention is defined in claim 1. Further developments are the subject of the dependent claims. This disclosure relates to a semiconductor component having a SiC semiconductor body. A first load terminal is formed on a first surface of the SiC semiconductor body. A second load terminal is formed on a second surface of the SiC semiconductor body opposite the first surface. The semiconductor component further comprises a drift zone of a first conductivity type in the SiC semiconductor body and a first semiconductor region of a second conductivity type that is electrically connected to the first load terminal. A pn ​​junction between the drift zone and the first semiconductor region defines a voltage blocking capability of the semiconductor component. A second semiconductor region of the second conductivity type is formed between at least a portion of the drift zone and the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings are provided to assist in understanding embodiments, are incorporated in and constitute a part of this disclosure, and are not intended to limit the scope of the disclosure. The drawings merely illustrate embodiments and, together with the description, serve to explain the same. Other embodiments and many of the intended advantages will become apparent from the detailed description that follows. The elements and structures shown in the drawings are not necessarily drawn to scale. Like reference numerals refer to like or corresponding elements and structures. Fig. 1A and Fig. 1B are schematic cross-sectional views of SiC semiconductor devices with a flexible device header according to embodiments. The Fig. 2A is a schematic horizontal cross-section through a portion of a semiconductor device according to an embodiment of the Fig. 1A and Fig. 1B shown device head region with stripe-like transistor cells and deep trench gate electrodes as well as single-sided transistor channel. The Fig. Figure 2B is a schematic vertical cross-section through the portion of the semiconductor device according to Fig. 2A along the cross-section line BB. The Fig. 3 is a schematic vertical cross-section through a portion of a semiconductor device according to an embodiment of the Fig. 1A and Fig. 1B shown component head area with planar gate structures. The Fig. 4 is a schematic vertical cross-section through a portion of a semiconductor device according to an embodiment of the Fig. 1A and Fig. 1B shown device head region with shallow trench gate structures. The Fig. 5 is a schematic vertical cross-section through a portion of a semiconductor device according to another embodiment of the device described in Fig. 1A and Fig. 1B shown device header area with deep trench gate structures. The Fig. 6 is a schematic vertical cross-section through a portion of a SiC Merged PIN Schottky (MPS) diode according to another embodiment of the device described in Fig. 1A and Fig. 1B shown component head area. The Fig. 7 is a schematic vertical cross-section through a portion of a SiC junction field effect transistor according to another embodiment of the device described in Fig. 1A and Fig. 1B shown component head area. The Fig. 8A to 8D show schematic cross-sectional views with embodiments of semiconductor regions that serve for charge carrier injection during the turn-off process. DETAILED DESCRIPTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure and in which specific embodiments of a SiC semiconductor device are shown for illustrative purposes. The existence of further embodiments is to be understood. Likewise, it is to be understood that structural and / or logical changes may be made to the embodiments without departing from the scope of the invention. The description of the embodiments is not limiting in this respect. In particular, features of embodiments described below may be combined with features of other described embodiments, unless the context indicates otherwise.

[0006] The terms "have," "contain," "comprise," "have," and similar terms are open terms and indicate the presence of the identified structures, elements, or characteristics, but do not exclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0007] The term "electrically connected" describes a low-resistance connection between the electrically connected elements, for example, a direct contact between the elements in question or a connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more elements capable of conducting current may be present between the "electrically coupled" elements, for example, elements that can be controlled to temporarily establish a low-resistance connection in a first state and a high-resistance decoupling in a second state.

[0008] The figures illustrate relative doping concentrations by the symbols “-” or “+” next to the doping type “n” or “p”. For example, “n - ” to a doping concentration that is lower than the doping concentration of an “n” doping region, while in an “n +"-doping region, the doping concentration is higher than in an "n"-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions can have the same doping concentration or different absolute doping concentrations. The term "dopant concentration" refers to a net dopant concentration unless the context indicates otherwise.

[0009] If a range of values ​​is defined for a physical quantity by specifying one or two limit values, the prepositions "from" and "to" or "less" and "more" include the respective limit value. A statement such as "from ... to" is therefore understood as "from at least ... to at most." Similarly, a statement such as "less ..." ("more ...") is understood as "at most ..." ("at least ...").

[0010] One embodiment relates to a semiconductor component with a SiC semiconductor body. The semiconductor component has a first load terminal on a first surface of the SiC semiconductor body and a second load terminal on a second surface of the SiC semiconductor body opposite the first surface. The semiconductor component also has a drift zone of a first conductivity type in the SiC semiconductor body and a first semiconductor region of a second conductivity type that is electrically connected to the first load terminal. A pn ​​junction between the drift zone and the first semiconductor region defines a blocking strength of the semiconductor component. A second semiconductor region of the second conductivity type is formed between at least a part of the drift zone and the second surface.

[0011] For example, the SiC semiconductor body can be constructed from single-crystal silicon carbide (SiC), for example, 2H-SiC (SiC of the 2H polytype), 6H-SiC, or 15R-SiC. According to one embodiment, the material of the SiC semiconductor body is 4H-SiC. The fact that a component "is" made of a material or "is constructed of" a material can mean here and below that said component consists of the material within the manufacturing tolerances and with the exception of doping.

[0012] The first surface can form the front side of the SiC semiconductor body and can be planar or ribbed. A ribbed first surface can be caused by a tilt of a main lattice plane of the SiC semiconductor body relative to a growth direction. A normal to a planar section of the first surface or to a midplane of a ribbed first surface defines the vertical direction. The vertical direction can run along the growth direction. In the case of a ribbed first surface, this can comprise coplanar surface sections, each of which runs obliquely, i.e. inclined, to the vertical direction. Directions perpendicular to the vertical direction or, in other words, parallel to a planar section of the first surface or parallel to the midplane of a ribbed first surface, are lateral (horizontal) directions.

[0013] The semiconductor component is, for example, a unipolar semiconductor component, e.g. a field effect transistor (FET) such as a MOSFET (metal oxide semiconductor FET). If the semiconductor component corresponds to a FET, the first load terminal can be a source terminal and the second load terminal can be a drain terminal. The first semiconductor region forms, for example, a body region or a shielding region. The semiconductor component can also be designed, for example, as a unipolar semiconductor component in the form of a Schottky diode or a Merged PIN Schottky (MPS) diode. If the semiconductor component corresponds to an MPS diode, the first load terminal can be an anode terminal and the second load terminal can be a cathode terminal. The first semiconductor region forms, for example, an anode region.The semiconductor component can, for example, also be designed as a unipolar semiconductor component in the form of a junction field-effect transistor (JFET). If the semiconductor component corresponds to a JFET, the first load terminal can be a source terminal, and the second load terminal can be a drain terminal. The first semiconductor region forms, for example, a semiconductor region serving to form the depletion layer and having a conductivity type opposite to the drift zone, e.g., a buried semiconductor region in the case of a vertical JFET with a lateral channel.

[0014] According to a further embodiment, the semiconductor component is designed as a bipolar semiconductor component, e.g., as an insulated gate field-effect transistor (IGBT). If the semiconductor component corresponds to an IGBT, the first load terminal can be, for example, an emitter terminal, and the second load terminal can be, for example, a collector terminal. The first semiconductor region forms, for example, a body region or a shielding region.

[0015] The semiconductor component can also be designed, for example, as a bipolar semiconductor component in the form of a diode, such as a conduction semiconductor diode and / or a PN diode. If the semiconductor component corresponds to a diode, the first load terminal can be, for example, an anode terminal, and the second load terminal can be a cathode terminal. The first semiconductor region forms, for example, an anode region.

[0016] The semiconductor component can also be designed, for example, as a bipolar junction transistor (BJT). If the semiconductor component corresponds to a BJT, the first load terminal can be a base terminal, for example, and the second load terminal can be a collector terminal. The first semiconductor region forms, for example, a base region.

[0017] The second semiconductor region in the drift zone makes it possible to provide free charge carriers during a turn-off or commutation process, enabling soft turn-off, i.e., a gentle run-off of the space charge zone during the turn-off process (so-called softness). This prevents unwanted overvoltage peaks during the turn-off process. In the case of SiC MPS diodes or SiC Schottky diodes, the second semiconductor region can also help dampen oscillations during commutation. Such oscillations can, for example, be the cause of EMC (electromagnetic compatibility) problems in the application. Even in the case of fast-switching SiC MOSFETs, strong oscillations during switching can be counteracted, thus avoiding parasitic restart and increased losses.

[0018] The SiC-based semiconductor components described here advantageously benefit from the fact that the dopants of the second semiconductor region (e.g., aluminum, gallium, or boron), introduced by ion implantation, for example, diffuse only very slightly. This makes it possible, on the one hand, to ensure very well-defined pn junctions to the second semiconductor region and thus very reproducible breakdown behavior of these pn junctions, and, on the other hand, to keep the vertical extent of these regions very small. This results in low volume consumption of the second regions. This, in turn, has a very beneficial effect on the voltage drop in the on-state of these components, since it increases the proportion of the current-carrying region, e.g., the drift zone.This is particularly important compared to bipolar components such as diodes or IGBTs, because conventional unipolar SiC power semiconductors are not flooded with free charge carriers. If such silicon-based components are manufactured using epitaxial processes, for example, they are exposed to a significant and therefore disruptive vertical expansion of these regions.

[0019] According to one embodiment, dopants of the second semiconductor region comprise deep impurities whose energy separation from the nearest band edge is more than 160 meV or even greater than or equal to 200 mV, for example, 210 mV. In the case of a p-type second semiconductor region, one or a combination of the dopant species aluminum (Al), gallium (Ga), and boron (B) can be used for doping. The energetically low dopant level can have the advantage that the beneficial effect of the second semiconductor region becomes more pronounced at higher temperatures. Due to the large energetic separation of the p-type dopant level from the valence band edge, it is possible for the dopant atoms to be only partially ionized and to release only a small proportion of their charge carriers. As the temperature increases, the degree of ionization can increase, and more charge carriers can be released.This can increase the desired effect with temperature. Another positive effect is that low energy levels cause increased recombination of charge carriers, meaning that p-doped regions can contribute to reducing the propagation of stacking faults in SiC components and thus also to preventing or at least reducing so-called bipolar degradation. Since, particularly with boron atoms, it is possible that the majority of the introduced boron atoms diffuse only relatively slowly, while a small portion can diffuse significantly faster, it can be advantageous to adjust the total concentration of the introduced boron atoms so that the concentration of the fast portion lies below the drift zones and any optional buffer doping.

[0020] According to one embodiment, the second semiconductor region has a maximum lateral extent in a range from 500 nm to 300 µm or else in a range between 1 µm and 100 µm, or else in a range between 2 and 50 µm or else in a range between 5 and 30 µm. This makes it possible, for example, to keep a voltage drop in the on-state of the semiconductor component low and thus counteract an undesirable influence of the second semiconductor region in the on-state of the semiconductor component. The geometry of the second semiconductor region can be diverse, e.g., it can take the form of stripes or islands. Likewise, the second semiconductor region can be a contiguous region that has holes or other recesses.

[0021] According to one embodiment, the second semiconductor region has a vertical dimension v in a range from 20 nm to 1 µm or 50 nm to 500 nm. The small vertical dimension of the second semiconductor region offers, for example, the technical advantage of a low voltage drop in the on-state of the semiconductor component. Given the only slight diffusion of the dopants in SiC due to the thermal budget during component fabrication, such small vertical dimensions can be achieved, for example, by ion implantation.

[0022] The lateral and vertical dimensions of the second semiconductor region can be matched to one another, for example, with regard to the voltage drop in the on-state and the effect during turn-off / commutation of the semiconductor component.

[0023] According to one embodiment, a plurality of second semiconductor regions or a contiguous second semiconductor region with openings are arranged in the drift zone or a buffer zone, wherein an area proportion of the plurality of second semiconductor regions or of the contiguous second semiconductor region with respect to an active area of ​​the semiconductor component is in a range from 10% to 50%, or else from 15% to 30%. Here, the active area refers to the area into which a load current can flow at a front side of the SiC semiconductor substrate, i.e. in the case of a MOSFET, the area provided with source contacts on the front side of the SiC semiconductor substrate. For example, the area of ​​an edge region with edge termination structures such as JTE (Junction Termination Extension) structures or VLD (Variation of Lateral Doping) structures is not counted as the active area.The setting of the area ratio can, for example, be set as a compromise between optimized transmission state and optimized softness when switching off.

[0024] According to one embodiment, a ratio of the minimum lateral distance between adjacent second semiconductor regions and the minimum or maximum lateral extent of the second semiconductor region lies in a range from 0.1 to 20 or also in a range between 1 and 5. The minimum lateral distance between adjacent second semiconductor regions is, for example, at least 1 µm or at least 3 µm or at least 5 µm. For example, the minimum distance between adjacent further semiconductor regions is 1 µm. The volume filled by the second semiconductor regions is thus small compared to the total volume of the drift zone.

[0025] According to one embodiment, the blocking strength of the semiconductor component lies in a range from at least 400 V to at most 15 kV, for example, at most 10 kV and in particular at most 6.5 kV. The blocking strength can be influenced and thus adjusted, for example, by a suitable choice of doping and the vertical extension of the drift zone.

[0026] According to one embodiment, the semiconductor component is a power semiconductor component having a specified current carrying capacity between the first load terminal and the second load terminal of at least 1 A.

[0027] According to one embodiment, the dopants comprise one or more elements from aluminum, boron, gallium, chromium, iridium.

[0028] According to a further embodiment, the second semiconductor region is buried in the SiC semiconductor body at a vertical distance from the second surface and arranged in an electrically floating manner. For example, the second semiconductor region can be arranged in the region of a transition between a highly doped semiconductor substrate and a lightly or moderately doped drift zone portion. Likewise, the second semiconductor region can be embedded in a field stop zone or buffer zone.

[0029] According to one embodiment, the semiconductor component additionally has a third semiconductor region of the first conductivity type, which is formed between the second semiconductor region and the second surface and adjoins the second semiconductor region. A net doping is greater in the second semiconductor region than in a fourth semiconductor region of the first conductivity type adjoining the third semiconductor region at the same depth in the SiC semiconductor body. The third semiconductor region makes it possible, for example, to specifically adjust a breakdown voltage of a rear-side pn junction, i.e. one directed towards the second surface, between the second semiconductor region and the third semiconductor region in order to thus contribute to sufficient softness during the turn-off process of the component by means of additional hole injection at a specific current density during the turn-off process and thus to the lowest possible overvoltage of the component.

[0030] According to one embodiment, a maximum lateral extent of the third semiconductor region coincides with a maximum lateral extent of the second semiconductor region. According to an alternative embodiment, a maximum lateral extent of the third semiconductor region is smaller than a maximum lateral extent of the second semiconductor region. In general, the third semiconductor region can have a vertical extent in a range from 20 nm to 1.5 µm or 50 nm to 1 µm.

[0031] According to one embodiment, the semiconductor component has scattering centers for reducing charge carrier mobility in the third semiconductor region. This advantageously allows a lateral voltage drop below the second semiconductor region to be increased. The scattering centers can comprise, for example, lattice defects, electrically inactive dopants, or dopants for partially compensating the doping in the third semiconductor region, or a combination thereof.

[0032] According to a further embodiment, which may be suitable for increasing the lateral voltage drop at lower operating temperatures, dopants for the third semiconductor region can be selected that are as far apart as possible from the nearest band edge. For example, the energetic distance of the dopants from the nearest band edge is at least 160 meV or greater than or equal to 200 mV. In the case of an n-type third semiconductor region, chromium (Cr), iridium (Ir), selenium (Se), sulfur (S), or a combination thereof can be selected in SiC.

[0033] According to a further embodiment, the semiconductor component further comprises a fifth semiconductor region of the first conductivity type, which is formed between the third semiconductor region and the second surface and adjoins the third semiconductor region. A net doping in the fifth semiconductor region is smaller than in the third semiconductor region. The fifth semiconductor region can be, for example, a buffer zone such as a field stop zone. A dopant concentration of the buffer zone can be, for example, in the range 5×10 16 cm -3 up to 5×10 18 cm -3 or in the range between 2×10 17 cm -3 up to 2×10 18 cm -3 lay.

[0034] A sixth semiconductor region, e.g., a further buffer zone, may also extend between the second semiconductor region and the drift zone and have a vertical extension between 300 nm and 5 µm or between 1 and 4 µm. A dopant concentration of the sixth semiconductor region may, for example, be in the range of 5×10 16 cm -3 up to 5×10 18 cm -3 or in the range between 2×10 17 cm -3 up to 2×10 18 cm -3 lay.

[0035] According to a further embodiment, the second semiconductor region adjoins the second surface, e.g., a contact such as a metallization on the second surface. Unlike in the embodiments in which the second semiconductor region is vertically spaced from the second surface, during the turn-off process, a charge carrier injection from the second region into the drift zone, e.g., a hole injection, is not based on an avalanche mechanism but on an amplification effect of the second semiconductor region. Because the p-type regions adjoin the metallization of the second surface, holes can be injected into the first semiconductor region when the lateral voltage drop along the second semiconductor region, with a corresponding current flow in the adjacent n-type region facing the drift zone, turns on this second semiconductor region during the turn-off process.

[0036] According to one embodiment, the drift zone is n-type. In other words, the first conductivity type is n-type in this embodiment. It is generally possible for dopants in the drift zone to include impurities whose energy separation from the conduction band edge is less than 140 meV. In the case of an n-type as the first conductivity type, the deep dopants in the drift zone can be, for example, nitrogen (N) and / or phosphorus (P).

[0037] In the schematic cross-sectional view of Fig. 1A illustrates an embodiment of a unipolar semiconductor device 100. The semiconductor device 100 includes a SiC semiconductor body 102 and a first load terminal L1 on a first surface 104 of the semiconductor body 102. Likewise, the semiconductor device 100 includes a second load terminal L2 on a second surface 106 of the semiconductor body 102, which is opposite the first surface 102.

[0038] Adjacent to the first surface 104, a component head region 108 is formed, which, depending on the type of unipolar semiconductor component, comprises different structural elements that serve the functionality of the respective component type, e.g., MOSFET, MPS diode, or JFET. These structural elements also comprise a p-doped first semiconductor region 110, which in the schematic view of Fig. 1A is simplified and assigned to the component header area 108.

[0039] The semiconductor component also has a n - -doped drift zone 112 in the SiC semiconductor body 102. Between the n - -doped drift zone 112 and the second surface 106 is an n + -doped semiconductor substrate 113.

[0040] The p-doped first semiconductor region 110 in the component head region 108 is electrically connected to the first load terminal L1, wherein a pn junction is formed between the n --doped drift zone 112 and the p-doped first semiconductor region 110 define a voltage blocking capability of the semiconductor component 100.

[0041] A plurality of p-doped second semiconductor regions 114 are arranged between at least a portion of the n - -doped drift zone 112 and the second surface 106. In the embodiment of the Fig. 1A, the second semiconductor regions 114 are at the junction between the n - -doped drift zone 112 and the n + -doped semiconductor substrate 113.

[0042] The statements made with regard to the effect and design of the second semiconductor region 114 in the above embodiments, e.g. a maximum lateral extent lmax, a vertical extent v, a surface area of ​​the second regions 114, a vertical distance d to the second surface 106 can be applied to the Fig. 1A and the following illustrated embodiments.

[0043] The first load terminal L1 is shown in simplified form as a first contact. This is, for example, a conductive structure that can comprise electrically connected conductive components such as contact plugs, metallization tracks, and connection pads. The electrically conductive components, in turn, consist of conductive material such as a metal, a metal silicide, a metal alloy, a highly doped semiconductor, or a combination thereof. These electrically conductive components are, for example, parts of a metallization and wiring region of the semiconductor component 100 formed above the first surface 104. The second load terminal L2 is shown in simplified form as a second contact. The information provided above in connection with the first load terminal L1 applies analogously to the second load terminal L2.

[0044] In the schematic cross-sectional view of Fig. 1B shows another embodiment of a unipolar semiconductor device 100 which differs from the unipolar semiconductor device 100 of Fig. 1A in that the second region 114 directly adjoins the second surface 106.

[0045] The statements made with regard to the effect and design of the second semiconductor region 114 in the above embodiments, e.g. a maximum lateral extent lmax, a vertical extent v, a surface area of ​​the second regions 114 can be applied to the Fig. 1B and the following illustrated embodiments.

[0046] In the Fig. 2A to 7 are exemplary embodiments of the component head region 108 of the embodiments of the Fig. 1A and Fig. 1B.

[0047] The Fig. 2A and Fig. 2B show a semiconductor device 500 with the SiC semiconductor body 102 with strip-like transistor cells TC and deep trench gate structures 150.

[0048] On a front side, the SiC semiconductor body 102 has the first surface 104, which may include coplanar surface sections that may form a ribbed first surface. The first surface 104 may coincide with a main lattice plane or extend obliquely to a lattice plane at an angular deviation α, e.g., to the (0001) lattice plane, wherein the angular deviation may be at most 12°, e.g., approximately 4°.

[0049] In the illustrated embodiment, the <0001> -Crystal direction inclined by an angular deviation α to a normal N. The <11-20> crystal direction is inclined by the same angular deviation α to the horizontal plane. The <1-100> crystal direction is orthogonal to the cross-sectional plane.

[0050] The weakly n-doped drift zone 112 is formed in the SiC semiconductor body 102.

[0051] Transistor cells TC on the front side of the SiC semiconductor body 102 are formed along gate structures 150 that extend from the first surface 104 into the SiC semiconductor body 102, with mesa portions 190 of the SiC semiconductor body 102 separating adjacent gate structures 150 from each other.

[0052] A longitudinal extension of the gate structures 150 along a first horizontal direction x1 is greater than a width of the gate structures 150 along a second horizontal direction x2 orthogonal to the first horizontal direction and transverse to the longitudinal extension. The gate structures 150 can be elongated trenches that extend from one side of a cell array region containing the transistor cells TC to an opposite side. The length of the gate structures 150 can be up to several hundred µm, or up to several millimeters, or even up to several centimeters.

[0053] According to other embodiments, the gate structures 150 may be formed along parallel lines, each extending from one side of the cell array region to the opposite side, and wherein a plurality of separate gate structures 150 may be formed along the same line. The gate structures 150 may also form a grid with the mesa sections 190 in the meshes of the grid.

[0054] The gate structures 150 may be evenly spaced from one another, may have the same width, and / or may form a regular pattern. A center-to-center spacing of the gate structures 150 may be in a range from at least 1 µm to at most 10 µm, e.g., from at least 2 µm to at most 5 µm. A vertical extension of the gate structures 150 may be at least 300 nm to at most 5 µm, e.g., in a range from at least 500 nm to at most 2 µm.

[0055] Sidewalls of the gate structures 150 may be aligned vertically to the first surface 108 or may be slightly tilted relative to the vertical direction, wherein opposing sidewalls may run parallel or obliquely to each other. According to one embodiment, the width of the gate structures 150 decreases with increasing distance from the first surface 104. For example, one sidewall deviates from the normal N by the angular deviation α, and the other sidewall deviates by -α.

[0056] The mesa sections 190 have two opposing mesa sidewalls 191, 192, which directly border two adjacent gate structures 150. At least one first mesa sidewall 191 lies in a lattice plane with high charge carrier mobility, e.g., in the case of 4H-SiC, in a (11-20) lattice plane, the so-called A-plane. The second mesa sidewall 192 opposite the first mesa sidewall 191 can be inclined by twice the angular deviation α, for example, by approximately 8°, relative to the respective lattice plane.

[0057] The gate structures 150 include a conductive gate electrode 155, which may comprise a highly doped polycrystalline silicon layer, a single- or multi-part metal structure, or both. The silicon layer may be electrically connected to a gate metallization that forms a gate terminal or is electrically connected or coupled to such a terminal.

[0058] Along at least one side of the gate structure 150, a gate dielectric 159 separates the gate electrode 155 from the SiC semiconductor body 102. The gate dielectric 159 may comprise a semiconductor dielectric, for example, a thermally grown or deposited semiconductor oxide, e.g., silicon oxide, a semiconductor nitride, e.g., a deposited or thermally grown silicon nitride, a semiconductor oxide nitride, e.g., a silicon oxynitride, another deposited dielectric material, or any combination of the aforementioned materials. The layer thickness of the gate dielectric 159 may, for example, be selected such that a threshold voltage of the transistor cells TC is in a range from 1V to 8V.

[0059] The gate structures 150 may comprise exclusively the gate electrode 155 and the gate dielectric 159 or may comprise, in addition to the gate electrode 155 and the gate dielectric 159, further conductive and dielectric structures, e.g., field plates and isolation dielectrics.

[0060] In the mesa sections 190, source regions 111 are formed toward the front side of the SiC semiconductor body 102, which source regions can directly adjoin the first surface 104 and the first mesa sidewall 191 of the respective mesa section 190. Each mesa section 190 can have a source region 111 with sections connected to one another in the SiC semiconductor body 102 or with at least two sections separated from one another in the SiC semiconductor body 102, which are electrically connected to one another with low resistance via a contact or trench contact adjacent to the mesa section 190.

[0061] The mesa sections 190 further include doped regions 120 that separate the source regions 111 from the drift zone 112 and form first pn junctions pn1 with the drift zone 112 and second pn junctions pn2 with the source regions 111. The doped regions 120 form an ohmic contact with a first load electrode 310.

[0062] In the illustrated embodiment, a doped region 120 comprises a less heavily doped body region 121 and a more heavily doped shielding region 122. The more heavily doped shielding region 122 can correspond to the first semiconductor region 110 of the component head region 108 of the embodiments of the Fig. 1A and Fig. 1B.

[0063] The body region 121 directly adjoins the first mesa sidewall 191. In the on-state of the transistor cell TC, an inversion channel connecting the source region 111 to the drift zone 112 is formed in the body region 121 along the gate structure 150. A vertical extension of the body region 121 corresponds to a channel length of the transistor cells TC and can be, for example, 200 nm to 1500 nm.

[0064] The shielding regions 122, which ensure protection of a bottom of the gate structure 150 (so-called trench bottom) in the case of high field strengths in the blocking state, are formed between the body regions 121 and the second mesa sidewalls 192 and can directly adjoin the body regions 121. A vertical extension of the shielding regions 122 can be greater than a vertical extension of the body regions 121, for example, greater than a vertical extension of the gate structures 150. A part of a shielding region 122 can be formed directly between the bottom of the gate structure 150 and the second surface 112 and shield the gate structure 150 against the potential of the second load electrode 320. A maximum dopant concentration p12 in the shielding regions 122 along the second mesa sidewalls 192 is higher, e.g.at least twice or even five times higher than a maximum dopant concentration p11 in the body regions 121 along the first mesa sidewalls 191.

[0065] The first load electrode 310 may form a source terminal S or be electrically connected or coupled to the source terminal S.

[0066] According to one embodiment, the transistor cells TC are n-channel FET cells with p-doped body regions 121, n-doped source regions 111, and the n-doped drift zone 112. According to another embodiment, the transistor cells TC are p-channel FET cells with n-doped body regions 121, p-doped source regions 111, and a p-doped drift zone 131.

[0067] A load current flowing through the SiC semiconductor body 102 in the on-state of the semiconductor component 500 passes through the body regions 121 in inversion channels induced along the gate dielectric 159. The higher dopant concentration in the shielding regions 122 compared to the dopant concentration in the body regions 121 suppresses the formation of inversion channels along the second mesa sidewalls 192 during operation within the absolute limit data and, in particular, offers protection of the bottom of the gate structure 150 in the case of high field strengths in the off-state. Since this region serves, in particular, to protect the bottom of the gate structure 150 in the off-state, doping this region with dopants having low-lying energy levels is particularly advantageous.Since this region should only cause a relatively low injection of free charge carriers, this is excellently ensured in the on-state by the relatively low activation of these dopants, without, however, having to accept any loss in the protective effect for the bottom of the gate structure 150, since these atoms with low-lying energy levels are in turn almost fully activated as soon as they lie within a space charge region.

[0068] The Fig. 3 shows a semiconductor component 500 with planar gate structures 150 on the front side of the SiC semiconductor body 102, wherein within a cell field region a single gate structure 150 is assigned to two transistor cells TC formed symmetrically to the gate structure 150.

[0069] The gate structures 150 comprise a conductive gate electrode 155 and a gate dielectric 159, which is formed directly on the first surface 104 and separates the gate electrode 155 from the SiC semiconductor body 102. A doped region 120 extending from the first surface 104 into the SiC semiconductor body 102 is assigned to two adjacent transistor cells TC of two adjacent gate structures 150. Source regions 111 of the two transistor cells TC extend from the first surface 104 into the doped region 120. The doped region 120 has a contact region 129 in which the dopant concentration is higher than the dopant concentration in a main region of the doped region 120 outside the contact region 129, which can adjoin the first surface 104 between the source regions 111. The main region of the doped region 120 forms the body region 121 of the transistor cell TC.

[0070] The drift zone 112 is formed in the SiC semiconductor body 102, wherein the drift zone 112 can extend between adjacent body regions 121 and below the gate electrodes 155 to the first surface 108.

[0071] In the switched-on state, the transistor cells TC form lateral inversion channels in channel regions of the body regions 121 along the gate dielectric 159, which connect the source regions 111 to the portions of the drift zone 112 adjacent to the first surface 108. The body region 121 can, for example, correspond to the first semiconductor region 110 of the component head region 108 of the embodiments of the Fig. 1A and Fig. 1B.

[0072] An interlayer dielectric 210 separates the gate electrode 155 from a first load electrode 310 on the front side of the SiC semiconductor body 102. Contacts 315 in openings of the interlayer dielectric 210 connect the first load electrode 310 to the contact regions 129 and the source regions 111.

[0073] In Fig. 4, the gate structures 150 are formed in shallow trenches with an approximately V-shaped vertical cross-sectional area. The gate electrode 155 may extend in an approximately uniform layer thickness along the sidewalls and the bottom of the trenches. Mesa sections 190 of the SiC semiconductor body 102 between adjacent gate structures 150 comprise source regions 111 formed along the first surface 108 as well as doped regions 120 between the source regions 111 and the drift zone 112, wherein the doped regions 120 may each have a less heavily doped body region 121 and a more heavily doped contact region 129. The body region 121 may, for example, correspond to the first semiconductor region 110 of the component head region 108 of the embodiments of the Fig. 1A and Fig. 1B.

[0074] The semiconductor device 500 of the Fig. 5 has gate structures 150 extending from the first surface 104 into a SiC semiconductor body 102, wherein the sidewalls of the gate structures 150 run vertically to the first surface 108. Doped regions 120 are formed in mesa sections 190 of the SiC semiconductor body 100 between adjacent gate structures 150, which form first pn junctions pn1 with the drift zone 112 and second pn junctions pn2 with source regions 111 formed along the first surface 108.

[0075] An interlayer dielectric 210 separates a gate electrode 155 of the gate structures 150 from a first load electrode 310. Between adjacent gate structures 150, trench contacts 316 extend from the first load electrode 310 into the mesa sections 190, laterally contact the SiC semiconductor body 102, and connect the source regions 111 to the first load electrode 310. A vertical extension of a portion of the trench contact 316 in the SiC semiconductor body 102 may approximately correspond to the vertical extension of the gate structures 150.

[0076] A part of the doped region 120 can be formed below the trench contacts 316 and separate them from the drift zone 112. A more heavily doped contact region 129 of the doped region 120 can directly adjoin the trench contact 316. The body region 121 can correspond to the first semiconductor region 110 of the component head region 108 of the embodiments of the Fig. 1A and Fig. 1B.

[0077] The Fig. The semiconductor device 500 shown in Figure 6 is an MPS diode including separate anode regions 211 extending from the first surface 104 into the cathode structure 220, e.g., into the drift region 112. The anode regions 211 may be strip-shaped with one horizontal dimension significantly exceeding the second horizontal dimension orthogonal to the first horizontal dimension, may be point-shaped with both horizontal dimensions within the same order of magnitude, or may form a lattice, e.g., a hexagonal lattice. Between adjacent anode zones 211, channel regions 225 of the cathode structure 220 directly border the metal anode electrode 310 and form Schottky contacts with the metal anode electrode 310. The metal anode electrode 310 may, for example, comprise Schottky contact regions directly bordering the anode zones 211 and main regions 312 forming ohmic contacts with the anode zones 211.The anode zone 211 may correspond to the first semiconductor region 110 of the device head region 108 of the embodiments of FIG. Fig. 1A and Fig. 1B.

[0078] The Fig. The semiconductor device 500 shown in Figure 7 is a SiC JFET. The SiC JFET is exemplified as a vertical JFET with a lateral channel. The SiC JFET has a p + -doped buried semiconductor region 502, which separates a channel region 504 from the drift zone 112. With the help of this buried semiconductor region 502 and a gate electrode G as well as the p + -doped control region 505, the channel width is modulated. The channel connection is made via an n + -doped source region 506, which together with the p + -doped buried semiconductor region 502 is electrically connected to a source electrode S. The p +-doped buried semiconductor region 502 may be associated with the first semiconductor region 110 of the device head region 108 of the embodiments of the Fig. 1A and Fig. 1B.

[0079] The Fig. The component types shown in Figures 2A to 7 are examples of the device used in the embodiments of Fig. 1A and Fig. 1B shown component head area 108. Of course, the Fig. 2A to 7 also in structural modifications in the component head area 108 of the embodiments of the Fig. 1A and Fig. 1B can be used.

[0080] According to the schematic cross-sectional view of the Fig. 8A, the semiconductor component 100 further comprises a third semiconductor region 115 of the first conductivity type, which is formed between the second semiconductor region 114 and the second surface 106 and adjoins the second semiconductor region 114. A net doping is greater in the second semiconductor region 114 than in a fourth semiconductor region 116 of the first conductivity type, which adjoins the third semiconductor region 115 at the same depth in the SiC semiconductor body 102. The fourth semiconductor region 116 corresponds, for example, to a part of the drift zone 112 or a buffer zone. The third semiconductor region 115 makes it possible to achieve a breakdown voltage of a rear-side, ieto specifically adjust the pn junction 117 directed towards the second surface 106 between the second semiconductor region 114 and the third semiconductor region 115 in order to contribute to sufficient softness during the turn-off process of the component and thus to the lowest possible overvoltage of the component at a certain current density during the turn-off process by means of additional hole injection.

[0081] According to the Fig. 8A, a maximum lateral extent of the third semiconductor region 115 is smaller than a maximum lateral extent of the second semiconductor region 114. According to the embodiment shown in Fig. In the embodiment shown in FIG. 8B, a maximum lateral extent of the third semiconductor region 115 coincides with a maximum lateral extent of the second semiconductor region 114. For example, the third semiconductor region 115 may have a vertical extent in a range from 100 nm to 1 µm.

[0082] According to the Fig. 8C, the semiconductor component 100 also has scattering centers (illustrated in simplified form with "×") for reducing the charge carrier mobility in the third semiconductor region 115. This advantageously allows a lateral voltage drop below the second semiconductor region 114 to be increased. The scattering centers can, for example, comprise lattice defects, electrically inactive dopants, or dopants for partially compensating the doping in the third semiconductor region, or a combination thereof.

[0083] According to another in Fig. In the embodiment shown in Figure 8D, which is suitable for increasing the lateral voltage drop at lower operating temperatures, dopants can be selected for the third semiconductor region (illustrated simply with "◯") that are as far away from the nearest band edge as possible. In the case of an n-type third semiconductor region 115, chromium (Cr), iridium (Ir), selenium (Se), sulfur (S), or a combination thereof can be selected in SiC, for example.

[0084] According to the Fig. In the embodiments shown in Figures 8A to 8D, the semiconductor component 100 further comprises a fifth semiconductor region 118 of the first conductivity type, which is formed between the third semiconductor region 115 and the second surface 106 and adjoins the third semiconductor region 115. A net doping in the fifth semiconductor region 118 is smaller than in the third semiconductor region 115. The fifth semiconductor region 118 may, for example, be a buffer zone such as a field stop zone. A dopant concentration of the buffer zone may, for example, be in the range of 5×10 17 cm -3 up to 5×10 18 cm -3 A sixth semiconductor region 130 of the first conductivity type can be formed between the drift zone 112 and the second semiconductor region 114 and can be designed, for example, as a buffer zone like the fifth semiconductor region. From the embodiments of the Fig.8A to 8D, further embodiments result directly, e.g. by omitting the fifth semiconductor region 118 or the sixth semiconductor region 130.

[0085] Charge carrier injection during the turn-off process is achieved, for example, by avalanche generation at the pn junction 117.

Claims

[1] A semiconductor device (100, 500) comprising: a SiC semiconductor body (102); a first load terminal (L1) on a first surface (104) of the SiC semiconductor body (102); a second load terminal (L2) on a second surface (106) of the SiC semiconductor body (102) opposite the first surface (102); a drift zone (112) of a first conductivity type in the SiC semiconductor body (102); a first semiconductor region (110) of a second conductivity type electrically connected to the first load terminal (L1), wherein a pn junction between the drift zone (112) and the first semiconductor region (110) defines a voltage blocking capability of the semiconductor component (100, 500); and a second semiconductor region (114) of the second conductivity type between at least a part of the drift zone (112) and the second surface (106), wherein dopants of the second semiconductor region (114) comprise deep defects whose energetic distance from the nearest band edge is more than 160 meV, and wherein the second semiconductor region (114) has a vertical extent (v) in a range from 20 nm to 1 µm. [2] Semiconductor component (100, 500) according to claim 1, wherein the second semiconductor region (114) has a maximum lateral extent (lmax) in a range from 500 nm to 300 µm. [3] The semiconductor device (100, 500) of claim 1, wherein the semiconductor device is a unipolar semiconductor device. [4] The semiconductor device (100, 500) of claim 3, wherein the semiconductor device is a merged PIN Schottky (MPS) diode, a Schottky diode, a field effect transistor, FET, a bipolar diode, or a junction FET. [5] Semiconductor device (100, 500) according to one of the preceding claims, wherein the barrier strength is in a range of 400 V to 15 kV. [6] Semiconductor component (100, 500) according to one of the preceding claims, wherein the semiconductor component is a power semiconductor component having a specified current carrying capacity between the first load terminal and the second load terminal of at least 1 A. [7] Semiconductor device (100, 500) according to one of the preceding claims, wherein the dopants comprise one or more elements selected from the group consisting of aluminum, boron, gallium, chromium, iridium. [8] Semiconductor component (100, 500) according to one of the preceding claims, comprising a plurality of second semiconductor regions (114), wherein an area proportion of the plurality of second semiconductor regions (114) with respect to an active area of ​​the semiconductor component is in a range of 10% to 50%. [9] Semiconductor component (100, 500) according to one of the preceding claims, wherein the second semiconductor region (114) is buried at a vertical distance (d) from the second surface (106) in the SiC semiconductor body (102) and arranged to be electrically floating. [10] Semiconductor component (100, 500) according to one of the preceding claims, further comprising a third semiconductor region (115) of the first conductivity type formed between the second semiconductor region (114) and the second surface (106) and adjoining the second semiconductor region (114), wherein a net doping in the second semiconductor region (114) is greater than in a fourth semiconductor region (116) of the first conductivity type adjoining the third semiconductor region (115) at the same depth in the SiC semiconductor body (102). [11] Semiconductor component (100, 500) according to claim 10, wherein a maximum lateral extent of the third semiconductor region (115) coincides with a maximum lateral extent (lmax) of the second semiconductor region (114). [12] Semiconductor component (100, 500) according to claim 10, wherein a maximum lateral extent of the third semiconductor region (115) is smaller than a maximum lateral extent (lmax) of the second semiconductor region (114). [13] Semiconductor component (100, 500) according to one of claims 10 to 12, wherein the third semiconductor region (115) has a vertical extension in a range of 20 nm to 1.5 µm. [14] Semiconductor component (100, 500) according to one of claims 10 to 13, which further comprises scattering centers for reducing the charge carrier mobility in the third semiconductor region (115). [15] Semiconductor component (100, 500) according to claim 14, wherein the scattering centers comprise lattice defects, or electrically inactive dopants or dopants for partially compensating the doping in the third semiconductor region (115). [16] Semiconductor component (100, 500) according to claim 14 or 15, wherein dopants of the third semiconductor region (115) comprise deep defects whose energetic distance to the nearest band edge is more than 160 meV. [17] Semiconductor component (100, 500) according to one of the preceding claims, further comprising a fifth semiconductor region (118) of the first conductivity type formed between the third semiconductor region (115) and the second surface (106) and adjoining the third semiconductor region (115), wherein a net doping in the fifth semiconductor region (118) is smaller than in the third semiconductor region (115). [18] Semiconductor device (100, 500) according to one of the preceding claims, further comprising a sixth semiconductor region (130) of the first conductivity type formed between the drift zone (112) and the second semiconductor region (114). [19] Semiconductor device (100, 500) according to one of claims 1 to 9, wherein the second semiconductor region (114) is adjacent to the second surface (106). [20] A semiconductor device (100, 500) according to any one of the preceding claims, wherein the first conductivity type is an n-type. [21] Semiconductor component (100, 500) according to claim 20, wherein dopants of the drift zone (112) comprise impurities whose energetic distance from the conduction band edge is less than 140 meV. [22] Semiconductor component (100, 500) according to one of the preceding claims, wherein a ratio of minimum lateral spacing of adjacent second semiconductor regions (114) and minimum lateral extent of the second semiconductor region (114) is in a range from 0.1 to 20.

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