Embedded storage using SOI structures and methods

Abstract

Integrated circuit (IC), comprising: a semiconductor-on-insulator (SOI) substrate (106) comprising a handling substrate (106A), an insulating layer (106B) over the handling substrate (106A) and a semiconductor device layer (106C) over the insulating layer (106B); a logic device (112) comprising a logic gate (122) arranged above the semiconductor device layer (106C), wherein the logic gate (122) is arranged in a high-κ dielectric layer; a memory cell (102) comprising a control gate (118) and a selection gate (120) arranged side by side and above the semiconductor device layer (106C), wherein a charge trap layer (130) lies below the control gate (118); a single source / drain region (134a) located on a first side of the control gate (118a); an intermediate source / drain region (136a) arranged laterally between a second side of the control gate (118a) and a first side of the selection gate (120a), the second side of the control gate (118a) being opposite the first side; and a common source / drain region (138) located on a second side of the selection gate (120a) opposite the first side, wherein the common source / drain region (138) has a bottom section extending into the handling substrate (106A).

Description

GENERAL STATE OF THE ART

[0001] Embedded memory is an electronic memory that is integrated with logic devices on a single integrated circuit (IC) die or chip. The embedded memory supports the operation of the logic devices and is frequently used with very-large-scale integration (VLSI) IC dies or chips. This integration advantageously improves performance by eliminating the need for interconnects between chips and reduces manufacturing costs by sharing process steps between the embedded memory and the logic devices.

[0002] Document CN 1 07 039 456 A describes an integrated circuit with a high-k metal gate and an embedded silicon oxide nitride oxide silicon memory cell. A logic device is mounted on a semiconductor-on-insulator substrate and includes a logic gate. The logic gate is located within a high-k dielectric layer. The memory cell is mounted on the semiconductor-on-insulator substrate and includes a control transistor and a select transistor, which are arranged side by side. The control transistor and the select transistor each include a control gate and a select gate. The control transistor includes a charge-trap layer located beneath the control gate.

[0003] The invention provides for an integrated circuit according to claim 1, an integrated circuit device according to claim 8, and a method according to claim 12. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may have been enlarged or reduced for clarity of explanation. Fig. Figure 1A shows a cross-sectional view of some embodiments of an integrated circuit (IC) incorporating high-κ-metal-gate (HKMG) technology and including an embedded silicon oxide-nitrite oxide-silicon (SONOS) memory cell. Fig. Figure 1B shows a cross-sectional view of some further detailed embodiments of the IC of Fig. 1 dar. Fig. Figure 1C shows a cross-sectional view of some embodiments of an embedded memory IC with buried common source trace. Fig. 2 shows a top view of some embodiments according to Fig. 1C. Fig. Figures 3-22 show a series of cross-sectional views of some embodiments for the manufacture of an IC with an embedded SONOS memory cell. Fig. 23 presents a flowchart of some embodiments of the method of Fig. 3-22 dar. Fig. Figures 15A-15D and 16A represent a series of cross-sectional views of some alternative embodiments for manufacturing an IC with an embedded SONOS memory cell. DETAILED DESCRIPTION

[0005] The present disclosure provides many different embodiments or examples of implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature above or on top of a second feature in the description below may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition is intended for the sake of simplicity and clarity and does not in itself imply any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatial terms such as "under," "below," "lower," "above," "upper," and the like may be used here to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial descriptions in this patent specification may be interpreted accordingly.

[0007] Some integrated circuits (ICs) include logic devices and embedded memory. The logic devices comprise polysilicon logic gates arranged perpendicularly above and through dielectric logic regions on a semiconductor substrate. The embedded memory comprises an array of memory cells, such as static random access (SRAM), dynamic random access (DRAM), flash memory, or other types of memory cells. In some embodiments, each memory cell may, for example, be in the form of a two-transistor (2T) silicon oxide nitrite oxide silicon (SONOS) or two-transistor (2T) metal oxide nitrite oxide silicon (MONOS) memory cell. A 2T SONOS memory cell comprises a polysilicon control gate and a polysilicon select gate arranged laterally spaced above the semiconductor substrate.The situation is similar with a MONOS memory cell, except that a metal control gate and a metal selection gate replace the polysilicon control gate and polysilicon selection gate, respectively. One challenge with the aforementioned ICs is that they are currently reaching performance and / or scalability limits. Performance can be quantified, for example, in terms of power consumption and / or switching speed. Furthermore, in some cases, challenges arise when integrating SONOS / MONOS memory cells and logic devices.

[0008] The present patent application, in various embodiments, relates to an integrated circuit (IC) comprising logic devices and embedded memory cells on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a lower semiconductor section—the so-called "handling" substrate—which provides structural integrity; an insulating layer above the handling substrate; and a semiconductor device layer above the insulating layer. By using an SOI substrate (instead of a conventional bulk silicon substrate), the embedded memory cells can achieve lower leakage currents and lower power consumption and are more compatible with the manufacturing process for logic devices compared to other solutions using a bulk (e.g., monocrystalline) substrate.This is largely due to the presence of the insulating layer in the SOI substrate, which provides good insulation for the logic devices and embedded memory cells. Compared to a conventional bulk substrate, the SOI substrate lowers parasitic capacitance, reduces device losses, and provides greater latch-up resistance. For example, in some cases, the logic device may be a high-k-metal-gate (HKMG) logic device, and the embedded memory cell may be a SONOS or MONOS embedded memory cell. When the HKMG logic device and the SONOS / MONOS memory cell are mounted on an SOI substrate with a silicon dioxide insulating layer, the insulating layer of the SOI substrate reduces leakage currents and power consumption of the SONOS / MONOS memory cell.Furthermore, by integrating the HKMG logic device with the SONOS or MONOS memory cell above the SOI substrate, the IC achieves good performance, low power consumption, and scalability. Additionally, the metal gate and high-kκ layer reduce leakage current, increase maximum drain current, mitigate Fermi level fixation, and lower the threshold voltage for the logic device.

[0009] The present patent application, in various embodiments, also relates to a method for fabricating the IC. In some embodiments, a control gate, a selection gate, and a dummy gate made of polysilicon (or metal) are formed and spaced laterally above an SOI substrate. The dummy gate is then removed to form a gate opening, and a high-kκ layer is formed in the gate opening. A metal logic gate is also formed in the gate opening. By forming the high-kκ layer and the metal gate last, the manufacturing costs are low and the process is short. Furthermore, the SOI substrate can be used without modifying the existing fabrication process for a SONOS / MONOS memory cell and an integrated logic device.The following description may refer to SONOS memory cells, but it should be understood that it is also applicable to MONOS memory cells as well as other types of memory cells, such as SRAM, DRAM, etc.

[0010] Reference is made to Fig. Figure 1A shows a cross-sectional view 100 of some embodiments of an IC. As shown, the IC is arranged on an SOI substrate 106, which has a handling substrate 106A, an insulating layer 106B over the handling substrate 106A, and a semiconductor device layer 106C over the insulating layer 106B.

[0011] The IC comprises a pair of embedded SONOS memory cells 102a, 102b and a logic device 112. The memory cells 102a, 102b are arranged on a memory region 104 of the SOI substrate 106 and, in some cases, may be symmetrically arranged around a central axis 103 of the pair of embedded SONOS memory cells. Memory cell 102a comprises a control transistor 108a and a selection transistor 110a, and memory cell 102b comprises a control transistor 108b and a selection transistor 110b. Furthermore, the logic device 112 is arranged on a logic region 114 of the SOI substrate 106. The memory region 104 and the logic region 114 are laterally adjacent and, in some embodiments, separated from each other by an isolation region 116.

[0012] The respective gates 118a, 118b, 120a, 120b of the memory cells 102a, 102b and gate 122 of the logic device 112 are arranged perpendicularly spaced from the SOI substrate 106 above and through respective dielectric regions 124, 126, 128. In some embodiments, the upper or top surfaces of the gates 118, 120, 122 are on substantially the same plane or, in some cases, substantially coplanar. The gates comprise control gates (CG) 118a, 118b and selection gates (SG) 120a, 120b, which are arranged side by side and correspond to the control transistors 108a, 108b and selection transistors 110a, 110b. Furthermore, gates 118a, 118b, 120a, 120b, 122 comprise a logic gate (LG) 122 corresponding to the logic device 112. Control gates 118a, 118b and selection gates 120a, 120b have a first material, and the logic gate 122 has a second material. In some embodiments, the first material is doped polysilicon and the second material is metal.

[0013] The dielectric regions 124, 126, 128 comprise a dielectric control region 124, a dielectric select region 126, and a dielectric logic region 128, corresponding to the control, select, and logic gates 118, 120, and 122, respectively. The dielectric control region 124 comprises a charge trap layer 130 and, in some embodiments, an overlying dielectric subregion 132. Furthermore, the dielectric logic region 128 comprises a high-κ layer (i.e., a dielectric layer with a dielectric constant κ greater than approximately 3.9) or is otherwise such a layer.

[0014] Advantageously, in various embodiments, the IC in which HKMG technology is integrated into the logic device 112 achieves good performance, low power consumption, and a small form factor. The metal gate and the high-kκ layer reduce leakage current, increase the maximum drain current, mitigate Fermi level fixation, and lower the threshold voltage for the logic device 112.

[0015] The respective source / drain regions 134a, 134b, 136a, 136b, 138 of gates 118a, 118b, 120a, 120b, 122 are arranged in an upper surface of the SOI substrate 106. The storage cells 102a, 102b have individual source / drain regions 134a, 134b, intermediate source / drain regions 136a, 136b, and the common drain region 138, which is shared by or "common" to the storage cells 102a, 102b. The individual source / drain regions 134a, 134b are arranged on opposite sides of the control gates 118a, 118b. The intermediate source / drain regions 136a and 136b are located between the respective control gates 118a and 118b and selection gates 120a and 120b; and the common source / drain region 138 is located between selection gates 120a and 120b. The source / drain regions are separated from each other by respective channel regions beneath the gates.For example, the control channel regions 142a, 142b are located below the control gates 118a, 118b; the selection channel regions 140a, 140b are located below the selection gates 120a, 120b; and the logic channel 144 is located below the logic gate 122. The source / drain regions 134a, 134b, 136a, and 138 have lower surfaces in various embodiments that directly contact an upper surface of the insulating layer 106B. In some cases, the channel region between the source / drain regions may have a lower doping level (e.g., no doping or intrinsic doping) compared to conventional solutions due to the presence of the SOI substrate instead of a bulk substrate. For example, the control gate well doping can be in the range of 1E15 atoms / cm3 to 1E17 atoms / cm3, which is lower than is usual in conventional bulk substrates and is due to the better channel control in FDSOI.This lighter well doping can achieve a tighter Vt distribution for the control gate, as the lighter well doping can exhibit less random doping variation and thus a lower Vt standard deviation.

[0016] In various embodiments, the SOI substrate is a fully depleted SOI (FDSOI) substrate. In various embodiments, the FDSOI substrate has a sufficiently thin semiconductor device layer 106C such that, during operation of the memory cell 102a, 102b, and / or the logic device 112, the depletion region in the channel region of the memory cell 102a, 102b, and / or the logic device 112 extends completely over the depth of the semiconductor device layer 106C. For example, in various embodiments, the semiconductor device layer 106C is a monocrystalline silicon layer with a thickness in the range of 5 nm to 40 nm and, in some cases, is approximately 10 nm to 12 nm thick. and the insulating layer 106B is a silicon dioxide or sapphire layer with a thickness in the range of 10 nm to 60 nm and is in some cases approximately 25 nm thick, which can provide FDSOI functionality.In contrast, a partially depleted SOI MOSFET has a semiconductor device layer 106C that is thicker than that of an FDSOI substrate; therefore, the depletion region extends only partially through the semiconductor device layer 106C in the PDSOI substrate (e.g., through less than 100% of the thickness of the semiconductor device layer 106C in the PDSOI substrate).

[0017] A first interlayer dielectric (ILD) layer 146 is arranged laterally between the control, selection and logic gates 118a, 118b, 120a, 120b, 122 and in some embodiments has an upper or top surface which is on a substantially the same plane as (or in some cases substantially coplanar with) the upper or top surfaces of the control, selection and logic gates 118a, 118b, 120a, 122. A second ILD layer 148 is arranged above the first ILD layer 146 and, in some embodiments, has a lower or bottom surface which is on an essentially the same plane as (or in some cases substantially coplanar with) the upper or top surfaces of the control, selection and logic gates 118a, 118b, 120a, 120b, 122.Contacts 150, 152, 154 extend perpendicularly through the first and second ILD layers 146, 148 to one or more of the source / drain regions 134a, 134b, 136a, 136b, 138 and / or one or more of the control, selection and logic gates 118a, 118b, 120a, 120b, 122.

[0018] In operation, the charge trap layer 130 stores charge in each memory cell and selectively switches between different amounts of stored charge, each representing a logical "0" or a logical "1". In this way, each of the SONOS memory cells 102a, 102b can store its own bit of data, or, if a higher resolution of the quantized amount of stored charge is used, multiple bits can be stored in each memory cell. For example, to measure the amount of stored charge in the SONOS memory cell 102a, in some embodiments a bias circuit applies a bias voltage to the control gate 118a, causing the control channel region 140a, located beneath the control gate 118a, to conduct selectively depending on the amount of stored charge. Depending on whether the control channel region 140a is conducting, the charge trap layer 130 stores a logical "0" or a logical "1".Since the stored charge shields an electric field generated by the control gate 118a, the threshold voltage that causes the control channel region 140a to conduct varies with the amount of stored charge. Accordingly, the bias voltage is selected between the threshold voltages at different amounts of stored charge. In some embodiments, to add charge to the charge trap layer 130, the bias circuit biases the control and selection gates 118a and 120a, respectively, with comparatively high and low voltages to promote hot carrier injection.In some embodiments, to remove the charge in the charge trap layer 130, the biasing circuit biases the control gate 118a with a high voltage of opposite polarity to the voltage stored in the charge trap layer 130 in order to promote Fowler-Nordheim tunneling (FNT) of the charge out of the charge trap layer 130.

[0019] For example, in some embodiments, an erase operation on a memory cell (e.g., 102a) can be performed by biasing the common source / drain (e.g., 138) to +4 V, the individual source / drain (e.g., 134a) to +4 V, the select gate (e.g., 120a) to +4 V, and the control gate (e.g., 118a) to -3.5 V. Furthermore, a programming operation can be performed by biasing the common source / drain (e.g., 138) to -3.5 V, the individual source / drain (e.g., 134a) to -3.5 V, the select gate (e.g., 120a) to -3.5 V, and the control gate to +4 V. Furthermore, a programming lock operation can be performed by biasing the common source / drain (e.g., 138) to -3.5 V, the individual source / drain (e.g., 134a) to +1.1 V, the select gate (e.g., 120a) to -3.5 V, and the control gate to +4 V. Furthermore, a read operation can be performed by biasing the common source / drain (e.g., 138) to 0 V, the individual source / drain (e.g., 134a) to +1.1 V, the select gate (e.g., 120a) to -3.5 V, and the control gate to +4 V.134a) to 0.5 V, the selection gate (e.g. 120a) to 2.5 V and the.

[0020] The control gate (e.g., 118a) is biased to 0 V. Furthermore, in some embodiments, the programming lock operation can operate with a reduced individual source / drain voltage, lower than in conventional solutions using a bulk substrate. For example, in some embodiments, the programming lock operation can operate with an individual source / drain voltage between 0 V and +1.1 V, and in some cases, the individual source / drain voltage can be in the range of +0.5 V to +0.9 V. This reduced individual source / drain voltage can achieve the same Vt window, thanks to the better blocking effectiveness of the FDSOI substrate compared to a bulk substrate.

[0021] These voltages are merely non-limiting examples, and it is understood that other voltages may be used in other embodiments. For example, in some other embodiments, a programming operation can be performed by biasing the common source / drain (e.g., 138) to between -5 and -2 V, the single source / drain (e.g., 134a) to between -5 V and -2 V, the select gate (e.g., 120a) to between -5 V and -2 V, and the control gate (e.g., 118a) to between +2 V and +8 V. Furthermore, a programming lock operation can be performed by biasing the common source / drain (e.g., 138) to between -5 V and -2 V, the individual source / drain (e.g., 134a) to between -3 V and -0.5 V, the select gate (e.g., 120a) to between -5 V and -2 V, and the control gate (e.g., 118a) to between +2 V and +8 V. Even further, a read operation can be performed by biasing the common source / drain (e.g.,138) to between 0 V, the individual source / drain (e.g. 134a) to between 0.1 V and 1 V, the selection gate (e.g. 120a) to between 1 V and 4 V and the control gate (e.g. 118a) to 0 V.

[0022] Although the IC is described in relation to embedded 2T SONOS memory cells 102a, 102b, it is clear that other types of embedded memory cells are suitable. For example, the IC can include an embedded memory cell with control and selection gates made of metal (instead of polysilicon) to achieve a MONOS memory cell. SRAM, DRAM, and other flash types, among others, are also considered to fall within the scope of this disclosure.

[0023] Reference is made to Fig. 1B, a cross-sectional view of 200 some detailed embodiments of the IC of Fig. Figure 1A, although shown with only one memory cell 102b and with three logic devices 112a, 112b, and 112c. As shown, the embedded memory cell 102b is located on a memory region 104 of the SOI substrate 106, and multiple logic devices 112a, 112b, and 112c are located on a logic region 114 of the SOI substrate 106. The embedded memory cell 102b can, for example, be a 2T SONOS memory cell and / or can, for example, include a control transistor and a selection transistor. The logic devices 112a–112c can, for example, include a first logic device 112a, a second logic device 112b, a third logic device 112c, or a combination thereof.The first logic device 112a can be, for example, a high-voltage transistor, the second logic device 112b can be, for example, a single-gate oxide transistor, and the third logic device 112c can be, for example, a dual-gate oxide transistor.

[0024] Memory region 104 and logic region 114 are located side by side and, in some embodiments, separated from each other by an isolation region 116. Furthermore, in some embodiments, logic devices 112a-112c are separated from each other laterally by second isolation regions 202, 204. The first and / or the second isolation regions 116, 202, 204 can be, for example, shallow trench isolation (STI) regions, deep trench isolation (DTI) regions, implantation isolation regions, or a combination thereof. The first and / or second isolation regions 116, 202, 204 can extend downwards through the semiconductor device layer 106C and have lower surfaces that are in direct contact with an upper surface of the isolation layer 106B.

[0025] The respective gates 118b, 120b, 122a, 122b, 122c of the memory cell 102b and the logic devices 112a-112c are arranged perpendicularly spaced from the SOI substrate 106 above and through respective dielectric regions 124, 126, 128a, 128b, 128c. In some embodiments, the upper or top surfaces of the gates 118b, 120b, 122a-122c are on substantially the same plane or, in some cases, substantially coplanar. Furthermore, in some embodiments, the heights of the gates 118b, 120b, 122a-122c are different from one another. Gates 118b, 120b, and 122a-122c comprise a control gate 118b and a select gate 120b, arranged side-by-side, both corresponding to memory cell 102b. Furthermore, gates 118b, 120b, and 122a-122c comprise logic gates 122a-122c, corresponding to logic devices 112a-112c. The control and select gates 118b and 120b constitute a first material, and the logic gates 122a-122c constitute a second material.In some embodiments, the first material comprises doped polysilicon or another silicon and / or the second material comprises metal. The metal may be, for example, titanium, tantalum, tungsten, copper, aluminum-copper, or aluminum, or may otherwise comprise metals.

[0026] The dielectric regions 124, 126, 128a-128c are arranged between the gates 118b, 120b, 122a-122c and the SOI substrate 106 to isolate and space the gates 118b, 120b, 122a-122c from the semiconductor device layer 106c. In some embodiments, the dielectric regions 124, 126, 128a-128c comprise lower or bottom surfaces that are substantially on the same plane or, in some cases, substantially coplanar and / or have varying heights H1, H2, H3, H4, H5. The dielectric regions 124, 126, 128a-128c comprise a dielectric control region 124, a dielectric selection region 126 and dielectric logic regions 128a-128c, which correspond to the control, selection and logic gates 118b, 120b, 122a-122c.

[0027] In various embodiments, the logic dielectric regions 128a-128c comprise respective high-κ layers 208a, 208b, 208c, which cover the lower or bottommost surfaces of the logic gates 122a-122c. In some embodiments, the high-κ layers 208a-208c also cover sidewall surfaces of the logic gates 122a-122c and / or directly abut the logic gates 122a-122c. The high-κ layers 208a-208c may, for example, be or otherwise comprise hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium tantalum oxide, zirconium silicate, or zirconium oxide.

[0028] The dielectric control region 124 comprises a charge-trapping layer 130 designed to store charge. In some embodiments, the charge-trapping layer 130 is an oxide-nitrite-oxide (ONO) structure or an oxide-nanocrystal-oxide (ONCO) structure, or otherwise comprises these. The ONO structure may, for example, comprise a first oxide layer, a nitrite layer arranged above and adjacent to the first oxide layer, and a second oxide layer arranged above and adjacent to the nitrite layer. The first and second oxide layers may, for example, comprise silicon dioxide, and / or the nitrite layer may, for example, be silicon nitrite. The ONCO structure may, for example, comprise a first oxide layer, a nanocrystal layer arranged above and adjacent to the first oxide layer, and a second oxide layer arranged above and adjacent to the nanocrystal layer.The nanocrystal layer can, for example, consist of a layer of silicon dots.

[0029] In some embodiments, the dielectric regions 128a-128c each comprise dielectric layers 210, 212, 214, which lie below the high-κ layers 208a-208c and / or above the charge-trap layer 130. For example, a first dielectric logic region 128a may comprise a first dielectric layer 210; the second dielectric logic region 128b may comprise a second dielectric layer 212, and the third dielectric logic region 128c may comprise a third dielectric layer 214. In some embodiments, the first dielectric layer 210 is a high-voltage gate oxide with a height H3 in the range between 90 angstroms and 250 angstroms; the second dielectric layer 212 is a low-voltage gate oxide with a height H4 in the range between 10 angstroms and 25 angstroms. and the third dielectric layer 214 is a medium-voltage oxide with a height in the range of 90 angstroms to 250 angstroms.More detailed embodiments, such as how the first, second and third dielectric layers 210, 212, 214 can be formed, and corresponding structural features are described, for example, further below in the manufacturing process in . Fig. 3-22 can be found.

[0030] The respective source / drain regions 134b, 136b, 138, and 139 are located in an upper region of the semiconductor device layer 106C of the SOI substrate 106. The source / drain regions 134b, 136b, 138, and 139 are located on opposite sides of the gates 118b, 120b, and 122a-122c, respectively, and define channel regions 140b, 142b, 144a, 144b, and 144c below the gates 120b, 118b, and 122a-122c, respectively. The channel regions 140b, 142b, 144a-144c conduct depending on the bias voltages applied to the gates 120b, 118b, 122a-122c. The source / drain regions 134b, 136b, 138, 139 can, for example, be doped regions exhibiting a doping type (n- or p-doping) opposite to that of the surrounding regions of the SOI substrate 106. Furthermore, the source / drain regions 134b, 136b, 138, 139 can, for example, be covered with silicide layers 216, 218. In some embodiments, the silicide layers 216, 218 comprise nickel silicide or titanium silicide.

[0031] In some embodiments, a main sidewall structure 220 and / or a contact etch stop layer (CESL) 222 cover the sidewalls of gates 118, 120, 122a-122c. Furthermore, in some embodiments, the CESL 222 extends laterally to cover the source / drain regions 134, 136, 138a, 138b and / or the first and / or second isolation regions 116, 202, 204. In some further embodiments, the main sidewall structure 220 is arranged laterally between the CESL 222 and gates 118b, 120b, 122a-122c and / or between the CESL 222 and the high-κ layers 208a-208c. Furthermore, in some embodiments, the upper or top surfaces of the main side wall structure 220 and / or the CESL 222 are on a substantially the same plane as the upper or top surfaces of the gates 118b, 120b, 122a-122c.The main sidewall structure 220 and / or the CESL 222 may, for example, contain silicon dioxide, silicon nitride or another dielectric.

[0032] A first ILD layer 146 is arranged laterally between gates 118b, 120b, 122a-122c and, in some embodiments, has an upper or top surface that is on substantially the same plane as the upper or top surfaces of gates 118b, 120b, 122a-122c. A second ILD layer 148 is arranged above the first ILD layer 146 and, in some embodiments, has a lower or bottom surface that is on substantially the same plane as the upper or top surfaces of gates 118b, 120b, 122a-122c. The first and / or the second ILD layer 146, 148 can, for example, comprise an oxide, polysilicate glass (PSG), a dielectric material with a dielectric constant less than approximately 3.9 (i.e., a low-κ dielectric material), or another dielectric material.Contacts 150, 152, 154a, 154b extend perpendicularly through the first and second ILD layers 146, 148 to one or more of the source / drain regions 134b, 136b, 138, 139 and / or one or more of the gates 118a, 120b, 122a-122c. The contacts 150, 152, 154a, 154b may, for example, comprise tungsten, copper, aluminum-copper, or another conductive material.

[0033] Even if the IC of Fig. Figure 1B, which shows several logic devices 112a-112c, indicates that more or fewer logic devices are possible. For example, the IC of Fig. 1B omits the first and third logic devices 112a, 112c. As a further example, the IC of Fig. 1B dispenses with the first and second logic devices 112a, 112b. As yet another example, the IC of Fig. 1B to forgo the second and third logic devices 112b, 112c.

[0034] Fig. 1C and Fig. 2 shows another embodiment of an IC, wherein Fig. 1C shows a cross-sectional view of the IC and Fig. Figure 2 shows a top view of the IC. Reference is made to Fig. 2; the top view shows an array of SONOS storage cells consisting of eight SONOS storage cell pairs arranged in four columns and two rows. For clarity, only one SONOS storage cell pair of 250 is shown. Fig. 2 labeled, and it can be seen that storage arrangements can have any number of SONOS storage cell pairs and Fig. Figure 2 is therefore merely an example. Other types of memory cells, such as MONOS memory cells, can also be used instead of the SONOS memory cell pairs. Furthermore, in NAND flash configurations, each memory cell pair can have a single select gate and a chain of multiple control gates connected in series and accessible via the select gate. Bit lines (BL) extend along respective columns of the memory array, while a pair of control gates (CG) and a pair of select gates (SG) extend along a row along each pair of SONOS cells. For example, a first bit line BL1 extends along the first column, a second bit line BL2 extends along the second column, and so on.Furthermore, a first pair of control gates (CG1a, CG1b), a first pair of selection gates (SG1a, SG1b) and a first common source line (CSL1) extend along the first row; whereas a second pair of control gates (CG2a, CG2b), a second pair of selection gates (SG2a, SG2b) and a second common source line (CSL2) extend along the second row; and so on.

[0035] As in the cross-section of Fig. As shown in Figure 1C, the embedded SONOS memory cell pair 250 comprises a first SONOS memory cell 102a and a second SONOS memory cell 102b. The memory cells 102a and 102b are arranged in a memory region 104 of the SOI substrate 106. Memory cell 102a includes a control transistor 108a and a selection transistor 110a, and memory cell 102b includes a control transistor 108b and a selection transistor 110b. Furthermore, a logic device 112 is arranged on a logic region 114 of the SOI substrate 106. The memory region 104 and the logic region 114 are laterally adjacent and, in some embodiments, separated from each other by an isolation region 116.

[0036] As in Fig. As shown in Figure 1C, the SONOS memory cell pair 250 has a common source / drain region 135 shared between the first SONOS memory cell 102a and the second SONOS memory cell 102b. The common source / drain region 135 has an epitaxial conductor 137 extending perpendicularly between an upper face of the semiconductor device layer 106C and a lower face of the insulating layer 106B. The epitaxial conductor 137 is typically made of doped monocrystalline silicon. The epitaxial conductor 137 directly contacts a doped region 139 located in the handling substrate 106A. The doped region 139, which is typically formed by ion implantation and subsequent annealing, extends outwards under the lower surface of the handling substrate 106A and meets the handling substrate 106A at a connection point with rounded corners 141.The epitaxial lead 137 and the doped region 139 have the same doping type as the source / drain regions 134a, 134b, 136a, and 136b. The doped region 139 has outermost edges 141 located directly beneath the selection gates 120a and 120b. For example, in some embodiments, the doped region 139 may extend beneath approximately 5%, 10%, 30%, or 50% of each selection gate 120a and 120b.

[0037] As in Fig. As shown in Figure 2, the epitaxial lead 137 and the doped region 139 extend continuously between multiple memory cell pairs of several respective columns in the array. Thus, the epitaxial lead 137 and the doped region 139 function as a common source lead (CSL) coupled to multiple SONOS memory cell pairs along a row in the memory array. Because the epitaxial lead 137 and the doped region 139 extend deeper into the substrate than in conventional solutions, they have a larger cross-sectional area and lower resistance than conventional source leads, resulting in higher efficiency during programming, erasing, program locking, and reading operations.

[0038] Reference is made to Fig. 3-22; a series of cross-sectional views of some embodiments of a high-κ-load method for fabricating an IC with an embedded SONOS memory cell are provided.

[0039] As seen in the cross-sectional view 300 of Fig. As shown in Figure 3, a first isolation region 116 is formed on the upper side of an SOI substrate 106 to laterally separate a memory region 104 of the SOI substrate 106 from a logic region 114 of the SOI substrate 106. Furthermore, one or more second isolation regions 202, 204 are formed on the upper side of the SOI substrate 106 to subdivide the logic region 114 into logic device regions 302, 304, 306. The logic device regions 302, 304, 306 can correspond, for example, to different device types, such as high-voltage transistors and dual-gate oxide transistors. In some embodiments, the first and second isolation regions 116, 202, 204 are formed simultaneously. Furthermore, in some embodiments, the process for forming the first and / or second insulation regions 116, 202, 204 includes etching into the SOI substrate 106 to form trenches, and subsequently filling the trenches with a dielectric material.

[0040] As seen in the cross-sectional view 400 of Fig. As shown in Figure 4, a charge-trap layer 130 is configured to cover the SOI substrate 106 and the first and second insulation regions 116, 202, 204. In some embodiments, the charge-trap layer 130 comprises a first oxide layer 402, a nitrite or nanocrystal layer 404 arranged above the first oxide layer 402, and a second oxide layer 406 arranged above the nitrite or nanocrystal layer 404. The first and second oxide layers 402, 406 may, for example, comprise silicon dioxide, and / or the nitrite or nanocrystal layer 404 may, for example, comprise silicon nitrite or silicon nanocrystals. Furthermore, in some embodiments the nitrite or nanocrystal layer 404 is arranged directly above the first oxide layer 402 and / or the second oxide layer 406 is arranged directly on the nitrite or nanocrystal layer 404.The process for forming the charge-trap layer 130 can, for example, involve successively forming the first oxide layer 402, the nitrite or nanocrystal layer 404, and the second oxide layer 406. The first and second oxide layers 402, 406, and the nitrite or nanocrystal layer 404 can be formed, for example, by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination of the above.

[0041] As seen in the cross-sectional view 500 of Fig. As shown in Figure 5, a first etch is performed on the charge trap layer 130. The first etch places the charge trap layer 130 on a selection transistor region 502 of the memory region 104, which is located laterally next to a control transistor region 504 of the memory region 104. The process of performing the first etch can, for example, include depositing and structuring a first photoresist layer 506 over the charge trap layer 130 to mask a region of the charge trap layer 130 that has been placed on the selection transistor region 502. Furthermore, the process can, for example, include applying one or more etchants 508 to the charge trap layer 130 while the first photoresist layer 506 is used as a mask. In addition, the process can, for example, subsequently include removing or otherwise abrading the first photoresist layer 506.

[0042] As seen in the cross-sectional view 600 of Fig. As shown in Figure 6, the first dielectric layer 210 is configured to cover the charge-trap layer 130 and the exposed regions of the SOI substrate 106. The first dielectric layer 210 can be, for example, silicon dioxide or another oxide. Furthermore, the first dielectric layer 210 can be formed, for example, by one or more processes of thermal oxidation, CVD, PVD, or ALD. In some embodiments, the first dielectric layer 210 is conformally formed (e.g., with a substantially uniform thickness).

[0043] As seen in the cross-sectional view 700 of Fig. As shown in Figure 7, a second etching is performed on the first dielectric layer 210 to place the first dielectric layer 210 on the first and second logic device regions 302, 304. The process for performing the second etching can, for example, involve depositing and structuring a second photoresist layer 702 over the first dielectric layer 210 to mask a region of the first dielectric layer 210 that is placed on the first and second logic device regions 302, 304. Furthermore, the process can, for example, involve applying one or more etchants 704 to the first dielectric layer 210, while the second photoresist layer 702 serves as a mask.The etchants 704 remove the unmasked portion of the first dielectric layer 210, and to help ensure that the unmasked portion of the first dielectric layer 210 is completely removed, the etchants 704 can also completely remove the second oxide layer 406 and stop at the nitrite or nanocrystal layer 404. In other embodiments, the etchants 704 can leave some portions of the second oxide layer 406 in place (not shown). Furthermore, the process can, for example, subsequently include removing or otherwise abrading the second photoresist layer 702.

[0044] As seen in the cross-sectional view 800 of Fig. As shown in Figure 8, the second dielectric layer 802 is configured to cover the charge-trap layer 130, the first dielectric layer 210, and the exposed regions of the SOI substrate 106. The second dielectric layer 802 can, for example, comprise silicon dioxide or another oxide. Furthermore, the second dielectric layer 802 can be formed, for example, by one or more processes of thermal oxidation, CVD, PVD, or ALD. In some embodiments, the second dielectric layer 802 is conformally formed.

[0045] As seen in the cross-sectional view 900 of Fig. As shown in Figure 9, a third etching is performed into the first and second dielectric layers 210, 802 to expose a second logic device region 304 between the first and third logic device regions 302, 306. The process for performing the third etching can, for example, involve depositing and structuring a third photoresist layer 902 over regions of the second dielectric layer 802 that laterally surrounds the second logic device region 304. Furthermore, the process can, for example, involve applying one or more etchants 904 to the first and second dielectric layers 210, 802, while the third photoresist layer 902 serves as a mask. Finally, the process can, for example, involve subsequently removing or otherwise abrading the third photoresist layer 902.

[0046] As seen through the cross-sectional view 1000 of Fig. As shown in Figure 10, a third dielectric layer 1002 is formed, which covers the second dielectric layer 802 and the second logic device region 304. The third dielectric layer 1002 can, for example, comprise silicon dioxide. Furthermore, the third dielectric layer 1002 can, for example, be formed by one or more processes of thermal oxidation, CVD, PVD, or ALD. In some embodiments, the third dielectric layer 1002 is conformally formed.

[0047] As also shown by the cross-sectional view 1000 of Fig. As shown in Figure 10, a first conductive layer 1004 is formed, which covers the third dielectric layer 1002. The first conductive layer 1004 can, for example, comprise polysilicon (e.g., doped polysilicon) or another conductive material. Furthermore, the first conductive layer 1004 can, for example, be formed by one or more CVD, PVD, or ALD layers. In some embodiments, the first conductive layer 1004 is conformally formed.

[0048] As seen in the cross-sectional view 1100 of Fig. As shown in Figure 11, a fourth etch is made into the charge trap layer 130, the first conductive layer 1004 (see e.g. Fig. 10) and the first, second and third dielectric layer 210, 802, 1002 (see e.g. Fig. 10) carried out. The fourth etching forms a control gate 118 or a selection gate 120 over the control and selection transistor regions 502, 504, as well as a first, second and third dummy gate 1102, 1104, 1106 over the first, second and third logic device regions 302, 304, 306. Furthermore, the fourth etch places the charge trap layer 130 under the control gate 118 and the first dielectric layer 210 under the first dummy gate 1102. In addition, the fourth etch divides the second dielectric layer 802 into several second dielectric layers 212, 1108, 1110, 1112 individually at and under the third and first dummy gates 1106, 1102, as well as the selection and control gates 120, 118. Furthermore, the fourth etch divides the third dielectric layer 1002 into several third dielectric layers 214, 1114, 1116, 118, 1120 individually at and under the second, third, and first dummy gates 1104, 1106, 1102, as well as the selection and control gates 120, 118.

[0049] The process for performing the fourth etching can, for example, involve depositing and structuring a fourth photoresist layer 1122 over regions of the first conductive layer 1004 corresponding to the control, selection, and dummy gates 118, 120, 1102-1106. Furthermore, the process can, for example, involve applying one or more etchants 1124 to the charge-trap layer 130, the first conductive layer 1004, and the first, second, and third dielectric layers 210, 802, 1002, while using the fourth photoresist layer 1122 as a mask. Finally, the process can involve subsequently removing or otherwise abrading the fourth photoresist layer 1124.

[0050] As seen in the cross-sectional view 1200 of Fig. As shown in Figure 12, the lightly doped drain (LDD) regions 1202, 1204, 1206 are formed in exposed regions of the SOI substrate 106. In some embodiments, LDD regions 1202, 1204, 1206 are formed by implanting ions 1208 into the SOI substrate 106, for example by ion implantation.

[0051] As seen in the cross-sectional view 1300 of Fig. As shown in Figure 13, a sidewall layer 1302 is configured to cover the first, second, and third dummy gates 1102, 1104, 1106; the control and selection gates 118, 120; and the LDD regions 1202, 1204, 1206. The sidewall layer 1302 can be, for example, silicon dioxide, silicon nitride, or another dielectric. Furthermore, the sidewall layer 1302 can be formed, for example, by one or more processes of thermal oxidation, CVD, PVD, or ALD. In some embodiments, the sidewall layer 1302 is configured to conform to the design.

[0052] As seen in the cross-sectional view 1400 of Fig. As shown in Figure 14, the sidewall layer 1302 is back-etched to form a main sidewall structure 220 that covers the sidewalls of the first, second, and third dummy gates 1102, 1104, 1106, as well as the control and select gates 118, 120. In some embodiments, the main sidewall structure 220 is limited to the sidewalls (i.e., without lateral extensions). The process for performing the back-etching may, for example, involve applying one or more etchants 1402 to the sidewall layer 1302 for approximately the time required by the etchant(s) 1402 to penetrate a certain thickness of the sidewall layer 1302.

[0053] As seen in the cross-sectional view 1500 of Fig. Figure 15 shows source / drain regions 134, 136, 138a, 138b, which are the LDD regions 1202, 1204, 1206 (see e.g. Fig. 14) exhibit, formed. In some embodiments, the source / drain regions 134, 136, 138a, 138b are formed by implanting ions 1502 into the SOI substrate 106, for example by ion implantation.

[0054] As seen in the cross-sectional view 1600 of Fig. As shown in Figure 16, in some embodiments silicide layers 216, 218 are formed on the source / drain regions 134, 136, 138a, 138b. The process for forming the silicide layers 216, 218 can, for example, include a nickel silidation process. Furthermore, the process for forming the silicide layers 216, 218 can, for example, include forming a resist protect oxide (RPO) layer that covers the areas around the source / drain regions 134, 136, 138a, 138b to prevent silicide formation on these areas.

[0055] As also shown by the cross-sectional view 1600 of Fig. As shown in Figure 16, a CESL 222 is formed that covers the main sidewall structure 220; the upper or top surfaces of the first, second, and third dummy gates 1102, 1104, 1106, as well as the control and selection gates 118, 120; and the source / drain regions 134, 136, 138a, 138b. The CESL 222 can be, for example, silicon dioxide, silicon nitride, or another dielectric. Furthermore, the CESL 222 can be formed, for example, by one or more thermal oxidation, CVD, PVD, or ALD processes. In some embodiments, the CESL 222 is conformally formed.

[0056] As also shown by the cross-sectional view 1600 of Fig. As shown in Figure 16, a first ILD layer 146 is formed, covering the CESL 222. The first ILD layer 146 can be, for example, an oxide, PSG, a low-κ dielectric, or another dielectric. Furthermore, the first ILD layer 146 can be formed, for example, by one or more CVDs or PVDs.

[0057] As seen in the cross-sectional view 1700 of Fig. As shown in Figure 17, a first planarization is carried out in the first ILD layer 146, the main sidewall structure 220 and the CESL 222 to expose the upper or top surfaces of the first, second and third dummy gates 1102, 1104, 1106 as well as the control and selection gates 118, 120. The first planarization can be carried out, for example, by chemical-mechanical polishing (CMP) and / or back-etching.

[0058] As seen in the cross-sectional view 1800 of Fig. As shown in Figure 18, a fifth etching is made into the first, second and third dummy gates 1102, 1104, 1106 (see, for example, Figure 18). Fig. 17) carried out to remove the dummy gates 1102, 1104, 1106 and form the respective gate openings 1802, 1804. The process for performing the fifth etching may, for example, include depositing and structuring a fifth photoresist layer 1806 covering the control and select gates 118, 120. Furthermore, the process may, for example, include applying one or more etchants 1808 to the first, second, and third dummy gates 1102, 1104, 1106, while the fifth photoresist layer 1806 is used as a mask. The process may also, for example, subsequently include removing or otherwise abrading the fifth photoresist layer 1806a.

[0059] As seen in the cross-sectional view from 1900 Fig. As shown in 19, a high-κ layer 1902 is formed, which forms the gate openings 1802, 1804 (see e.g. Fig. 18) covers, which were previously occupied by the first, second and third dummy gates 1102, 1104, 1106 (see e.g. Fig. 17) The high-κ layer 1902 has a dielectric constant κ above 3.9 and can, for example, be hafnium oxide. Furthermore, the high-κ layer 1902 can be formed, for example, by CVD, PVD, ALD, or a combination of the aforementioned. In some embodiments, the high-κ layer 1902 is conformally formed.

[0060] As also shown by the cross-sectional view from 1900 Fig. As shown in Figure 19, a second conductive layer 1904, which covers the high-κ layer 1902, is formed in the gate openings 1802, 1804 (see, for example, Figure 19). Fig. 18). The second conductive layer 1904 consists of a different material than the first conductive layer 1004 (see e.g. Fig. 10) and can be, for example, copper, tungsten, aluminum, or another metal. Furthermore, the second conductive layer 1904 can be formed, for example, by CVD, PVD, ALD, or a combination of the aforementioned.

[0061] As shown by the cross-sectional view 2000 of Fig. 2000, a second planarization is carried out in the second conductive layer 1904 (see e.g. Fig. 19) and the high-κ layer 1902 (see e.g. Fig. 19) was carried out to approximate the upper or top surfaces of the control and selection gates 118, 120. The second planarization forms logic gates 122a, 122b, 122c in the gate openings 1802, 1804 (see e.g. Fig. 18). Furthermore, the second planarization divides the high-κ layer 1902 into several high-κ layers 208a, 208b, 208c individually at and below the logic gates 122a, 122b, 122c. In addition, in some embodiments, the planarization plans the upper or top surfaces of the logic gates 122a-122c to the same plane as the upper or top surfaces of the first ILD layer 146 and the control gate 118. The second planarization can be performed, for example, by means of CMP and / or back-etching.

[0062] As shown in the cross-sectional view 2100 of Fig. As shown in Figure 21, a second ILD layer 148 is formed such that it covers the first ILD layer 146 as well as the control and selection gates 118, 120 and the logic gates 122a-122c. The second ILD layer 148 can, for example, be an oxide, PSG, or a low-κ dielectric. Furthermore, the second ILD layer 148 can, for example, be formed by CVD or PVD.

[0063] As seen in the cross-sectional view 2200 of Fig. As shown in Figure 22, a third planarization is performed in the second ILD layer 148. The third planarization can be carried out, for example, by means of CMP and / or back etching.

[0064] As also shown by the cross-sectional view 2200 of Fig. As shown in Figure 22, contacts 150, 152, 154a, 154b are configured to extend through the first and second ILD layers 146, 148 to the source / drain regions 134, 136, 138a, 138b. Additionally or alternatively, contacts 150, 152, 154a, 154b are configured to extend to the control, selection, and logic gates 118, 120, 122a-122c. Contacts 150, 152, 154a, 154b can be made of, for example, tungsten, copper, aluminum-copper, or another conductive material. Furthermore, the process for forming the contacts 150, 152, 154a, 154b may, for example, include performing a sixth etching into the first and second ILD layers 146, 148 to create contact openings, filling the contact openings with a third conductive layer, and planarizing the third conductive layer on the same plane as the top surfaces of the second ILD layer 148 and the third conductive layer.

[0065] Reference is made to Fig. 23; a flowchart 2300 of some embodiments of a high-k-load process for fabricating an IC with an embedded SONOS memory cell is provided. The high-k-load process can, for example, be used to produce a series of cross-sectional views relating to Fig. 3-22 are shown.

[0066] At 2302, an isolation region is formed that laterally separates memory and logic regions of a semiconductor substrate. See, for example, Fig. 3.

[0067] In 2304, several dielectric regions are formed laterally spaced above the memory and logic regions. Furthermore, the multiple dielectric regions, one of which comprises a charge-trap layer, are formed above the memory region. In some embodiments, the dielectric regions of the multiple regions have varying thicknesses. See, for example, [reference]. Fig. 4-10.

[0068] In 2306, a control gate, a select gate, and a dummy gate made of polysilicon are formed over the dielectric regions. The dummy gate is formed over the logic region, and the control and select gates are spaced laterally above the memory region. Furthermore, the control gate is formed over the charge trap layer. See, for example, [reference to relevant example]. Fig. 10 and Fig. 11.

[0069] In version 2308, source / drain regions are formed on opposite sides of the control, select, and dummy gates. See, for example, [reference to example]. Fig. 12-15.

[0070] At 2310, an initial ILD layer is formed, covering the control, selection, and dummy gates as well as the source / drain regions. See, for example... Fig. 16 and Fig. 17.

[0071] At 2312, the dummy gate is removed to create a gate opening. See, for example... Fig. 18.

[0072] In 2314, a high-κ layer forms in the gate aperture. This high-κ layer has a dielectric constant κ higher than approximately 3.9. See, for example... Fig. 19.

[0073] In 2316, a logic gate made of metal is formed in the gate opening above the high-κ layer. See, for example, Fig. 20.

[0074] At 2318, a second ILD layer is formed, covering the first ILD layer as well as the control, selection, and logic gates. See, for example... Fig. 21 and Fig. 22.

[0075] At 2320, contacts are established that extend through the first and second ILD layers to the source / drain regions and / or to the control, selection, and logic gate. See, for example, Fig. 22.

[0076] Although the process is described using polysilicon control, selection, and dummy gates and a metal logic gate, other gate materials may also be used. Furthermore, although the process is described using a high-kκ layer, the high-kκ layer may be omitted or replaced by another material. It should also be understood that, although the process is illustrated and described here as a series of actions or events, as shown in Flowchart 2300, the sequence of these actions or events is not to be interpreted restrictively. For example, some actions may occur in different sequences and / or simultaneously with other actions or events in addition to those illustrated and / or described in this document.Furthermore, not all illustrated actions may be necessary to implement one or more aspects or embodiments of the description contained in this document, and one or more of the actions illustrated in this document may be carried out in one or more separate actions and / or phases.

[0077] Fig. 15A-15D and Fig. 16A together represent an alternative manufacturing process for manufacturing an IC according to Fig. 1C. The cross-sectional view 1500A of Fig. 15A corresponds to the one discussed above. Fig. 15, in which source / drain regions 134, 136, 138a, 138b were formed. In some embodiments, the source / drain regions 134, 136, 138a, 138b are formed by implanting ions 1502 into the SOI substrate 106, for example by ion implantation.

[0078] As shown in cross-sectional view 1500B from Fig. As shown in Figure 15B, a fourth photoresist layer can be applied and structured to provide a fifth photoresist mask 1550, which has an opening 1552 corresponding to a common source / drain region of the IC. Furthermore, the process can, for example, include applying one or more etchants to remove the exposed portion of the semiconductor device layer 106C and the underlying insulating layer 106B, thereby forming a recess extending downwards through the semiconductor device layer 106C and the underlying insulating layer 106B, while the fourth photoresist layer 1122 acts as a mask.

[0079] As shown in the cross-sectional view 1500C from Fig. As shown in Figure 15C, one or more ion implantation operations can be performed to form a doped region 139 in the handling substrate 106A. After ion implantation, an annealing process is carried out to diffuse the implanted dopants beneath the insulating layer 106B and repair the surface damage resulting from the ion implantation. However, even with annealing, some surface damage, such as lattice displacements, will remain on the upper surface of the doped region 139. Due to the diffusion that occurs during annealing, the doped region 139 typically has a width greater than that of the opening 1552.

[0080] As seen in the 1500D cross-sectional view from Fig. As shown in Figure 15D, a selective epitaxial growth process can be performed to grow an epitaxial conductor 137 over the doped region 139. In some embodiments, the epitaxial growth can be stopped so that an upper surface of the epitaxial conductor 137 is substantially planar with the upper surface of the semiconductor device layer 106C; however, more typically, the epitaxial conductor 137 has a top surface that either extends above or remains below the upper surface of the semiconductor device layer 106C. Furthermore, the process can subsequently include removing or otherwise abrading the fifth photoresist mask 1150.

[0081] As shown in the cross-sectional view 1600A from Fig. As shown in Figure 16A, in some embodiments silicide layers 216 are formed on the source / drain regions 134, 136, 138a, 138b and over the epitaxial conduit 137. The process for forming the silicide layers 216, 218 can, for example, include a nickel silidation process. Furthermore, the process for forming the silicide layers 216, 218 can, for example, include forming a resist protect oxide (RPO) layer that covers the areas around the source / drain regions 134, 136, 138a, 138b and the epitaxial conduit 137 to prevent silicide formation on these areas.

[0082] As also shown by the cross-sectional view 1600A from Fig. As shown in Figure 16A, a CESL 222 is formed that covers the main sidewall structure 220; the upper or top surfaces of the first, second, and third dummy gates 1102, 1104, 1106, as well as the control and selection gates 118, 120; the source / drain regions 134, 136, 138a, 138b; and the epitaxial conductor 137. The CESL 222 can be, for example, silicon dioxide, silicon nitride, or another dielectric. Furthermore, the CESL 222 can be formed, for example, by one or more thermal oxidation, CVD, PVD, or ALD processes. In some embodiments, the CESL 222 is conformally formed.

[0083] As also shown by the cross-sectional view 1600A from Fig. As shown in Figure 16A, a first ILD layer 146 is formed, covering the CESL 222. The first ILD layer 146 can be, for example, an oxide, PSG, a low-κ dielectric, or another dielectric. Furthermore, the first ILD layer 146 can be formed, for example, by one or more CVDs or PVDs. According to Figure 16A, the alternative process then reverts to the one shown above. Fig. 17 back and will continue until Fig. Continued on page 22.

[0084] Thus, as can be seen from the foregoing, the present disclosure provides an integrated circuit (IC) comprising a logic device and a memory cell. The logic device is arranged on a semiconductor substrate and includes a logic gate embedded in a high-κ dielectric layer. The memory cell is also arranged on the semiconductor substrate and comprises a control transistor and a select transistor positioned side by side. The control transistor and the select transistor each comprise a control gate and a select gate, and the control transistor further comprises a charge-trap layer beneath the control gate. The control and select gates constitute a first material, and the logic gate is a second material.

[0085] In other embodiments, the present disclosure provides a high-κ-load method for fabricating an integrated circuit. A charge-trap layer is formed over a semiconductor substrate. A control gate, a select gate, and a dummy gate are formed from a first material and spaced laterally above the semiconductor substrate. The control gate is formed over the charge-trap layer. An ILD layer is formed laterally between the control, select, and dummy gates, with a top surface lying on substantially the same plane as the top surfaces of the control, select, and dummy gates. The dummy gate is removed to form a gate opening. The high-κ dielectric layer is formed such that it covers the gate opening. A logic gate made of a second material is formed in the gate opening and over the high-κ dielectric layer.

[0086] In other embodiments, the present disclosure provides an integrated circuit (IC) comprising a logic device and a memory cell. The logic device is arranged on a semiconductor substrate and includes a logic gate. The memory cell is also arranged on the semiconductor substrate and comprises a control transistor and a select transistor positioned side by side. The control transistor and the select transistor each comprise a control gate and a select gate, and the control transistor further comprises a charge-trap layer beneath the control gate. The control and select gates constitute a first material, and the logic gate is a second material.

Claims

[1] Integrated circuit (IC), comprising: a semiconductor-on-insulator (SOI) substrate (106) comprising a handle substrate (106A), an insulating layer (106B) over the handle substrate (106A), and a semiconductor device layer (106C) over the insulating layer (106B); a logic device (112) comprising a logic gate (122) disposed over the semiconductor device layer (106C), the logic gate (122) disposed in a high-κ dielectric layer; a memory cell (102) comprising a control gate (118) and a select gate (120) arranged laterally adjacent to each other and above the semiconductor device layer (106C), wherein a charge trap layer (130) lies below the control gate (118); a single source / drain region (134a) disposed on a first side of the control gate (118a); an intermediate source / drain region (136a) disposed laterally between a second side of the control gate (118a) and a first side of the select gate (120a), the second side of the control gate (118a) being opposite the first side; and a common source / drain region (138) disposed on a second side of the select gate (120a) opposite the first side, the common source / drain region (138) having a lowermost portion extending into the handle substrate (106A). [2] The IC of claim 1, wherein the SOI substrate (106) is a fully depleted SOI (FDSOI) substrate. [3] The IC of claim 1 or 2, wherein the semiconductor device layer (106C) is a monocrystalline silicon layer having a thickness in the range of 5 nm to 40 nm, wherein the insulating layer (106B) is a silicon dioxide or sapphire layer having a thickness in the range of 10 nm to 60 nm. [4] The IC of any preceding claim, wherein the semiconductor device layer (106C) has a thickness such that during operation of the memory cell (102) or logic device (112), a depletion region in a channel region of the memory cell (102) or logic device (112) extends completely across the depth of the semiconductor device layer (106C). [5] IC according to one of the preceding claims, further comprising: a bias circuit configured to perform a program lock operation on the memory cell (102) by biasing the common source / drain region (138) to approximately -3.5 volts while biasing the single source / drain region (134a) to less than +1.1, while biasing the select gate (120a) to approximately -3.5 volts, and while biasing the control gate (118a) to approximately +4 volts. [6] The IC of any one of the preceding claims 1 to 4, wherein the single source / drain region (134a) and the intermediate source / drain region (136a) have lower portions in direct contact with an upper surface of the insulating layer (106B) of the SOI substrate (106). [7] The IC of claim 6, further comprising: an isolation region disposed in the semiconductor device layer (106C) between the memory cell (102) and the logic device (112), the isolation region extending from a top surface of the semiconductor device layer (106C) and contacting the top surface of the isolation layer (106B). [8] Integrated circuit device (IC) with a memory device, comprising: a semiconductor-on-insulator (SOI) substrate (106) comprising a handle substrate (106A), an insulating layer (106B) over the handle substrate (106A), and a semiconductor device layer (106C) over the insulating layer (106B); a first and a second single source / drain region (134a, 134b) arranged in the semiconductor device layer (106C) and spaced from each other; first and second intermediate source / drain regions (136a, 136b) disposed in the semiconductor device layer (106C) and between the first and second single source / drain regions (134a, 134b), the first single source / drain region (134a) being spaced from the first intermediate source / drain region (136a) by a first control channel region (142a) and the second single source / drain region (134b) being spaced from the second intermediate source / drain region (136b) by a second control channel region (142b); a common source / drain region (138) disposed in the semiconductor device layer (106C) and between the first (136a) and second intermediate source / drain regions (136b), the first intermediate source / drain region (136a) being spaced from the common source / drain region (138) by a first select channel region (140a) and the second intermediate source / drain region (136b) being spaced from the common source / drain region (138) by a second select channel region (140b); a first and a second control gate (118a, 118b) arranged over the first and second control channel regions (142a, 142b), respectively; and first and second selection gates (120a, 120b) disposed over the first and second selection channel regions (140a, 140b), respectively; wherein the common source / drain region (138) comprises a doped region (139) disposed in the handle substrate (106A) and an epitaxial semiconductor region (137) extending from near a top surface of the semiconductor device layer (106C) to a top surface of the doped region (139). [9] The IC of claim 8, wherein the common source / drain region (138) extends in a continuous path between a plurality of common source / drain regions of a plurality of respective columns of the memory device. [10] The IC of claim 8 or 9, wherein the common source / drain region (138) has outermost edges located immediately below the first and second select gates (120a, 120b). [11] The IC of any one of the preceding claims 8 to 10, wherein the doped region (139) has a first width measured in a first direction between nearest edges of the first and second select gates (120a, 120b) and wherein the epitaxial semiconductor region (137) has a second width measured in the first direction, the second width being greater than the first width. [12] A method of manufacturing an integrated circuit, the method comprising: Forming a charge trapping layer (130) over a semiconductor-on-insulator (SOI) substrate (106), the SOI substrate (106) comprising a handle substrate (106A), an insulating layer (106B) over the handle substrate (106A), and a semiconductor device layer (106C) over the insulating layer (106B); Forming a control gate (118), a select gate (120) and a dummy gate (1102) from a first material and laterally spaced above the semiconductor device layer (106C), wherein the control gate (118) is formed above the charge trap layer (130); Forming an interlayer dielectric (ILD) layer (146) laterally between the control (118), select (120) and dummy gates (1102) and having a top surface substantially coplanar with top surfaces of the control, select and dummy gates (118, 120, 1102); removing the dummy gate (1102) to form a gate opening (1802); Forming a high-κ dielectric layer (1902) covering the gate opening (1802); Forming a logic gate (122a) from a second material in the gate opening (1802) and over the high-κ dielectric layer (1902); Removing a portion of the semiconductor device layer (106C) and the insulating layer (106B) to form a recess in the SOI substrate (106) along a side of the select gate (120), the recess exposing a portion of the handle substrate (106C); Performing an ion implantation process to implant ions into the exposed portion of the handling substrate (106A), thereby forming a doped region in the handling substrate (106A); and Performing an epitaxial growth process to grow an epitaxial semiconductor region in the recess such that it is in direct contact with an upper surface of the doped region. [13] The method of claim 12, further comprising: Remove the dummy gate (1102), but not the control gate (118) and the selection gate (120). [14] The method of claim 12 or 13, wherein removing the dummy gate comprises: performing an etching process into the dummy gate (1102) to form the gate opening (1802). [15] The method of any one of the preceding claims 12 to 14, wherein forming the logic gate (122a) comprises: Forming a conductive layer of the second material that fills the gate opening (1802) above the high-κ dielectric layer (1902); Performing planarization into the conductive layer to form the logic gate (122a). [16] The method of claim 12, further comprising: Performing an annealing process after the ion implantation process to diffuse dopants from the ion implantation such that the dopants extend directly under a lower surface of the insulating layer (106B). [17] Method according to one of the preceding claims 12 to 16, further comprising: Forming a plurality of dielectric regions laterally spaced above the semiconductor device layer (106C) and with varying heights between the dielectric regions; and Forming the control, selection or logic gate (118, 120, 122a) over the dielectric regions.

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