METHOD AND STRUCTURES RELATING TO IMPROVED FERROELECTRIC DIRECT ACCESS STORAGE (FeRAM)

Abstract

Storage device, comprising: a lower electrode structure (104); an upper electrode (114) that lies above the lower electrode structure (104), wherein the upper electrode (114) has a first width; a ferroelectric structure (112) that separates the lower electrode structure (104) from the upper electrode (114), wherein the ferroelectric structure (112) has a second width that is larger than the first width, such that the ferroelectric structure (112) includes a projection (119) that reflects a difference between the first width and the second width; a dielectric sidewall spacer structure (118) arranged on the projection (119) and covering outermost sidewalls of the upper electrode (114); a conductive residue (117) arranged along outermost sidewalls of the dielectric sidewall spacer structure (118), along outermost sidewalls of the ferroelectric structure (112), and along outermost sidewalls of the lower electrode structure (104); and a hard mask (116) over an upper surface of the upper electrode (114), wherein the conductive residue (117) is further arranged on an upper surface of the dielectric sidewall spacer structure (118) and directly on an upper surface of the hard mask (116).

Description

GENERAL STATE OF THE ART

[0001] Many modern electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data without a power supply. A promising candidate for the next generation of non-volatile memory is ferroelectric random access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2004 / 0 084 701 A1, US 2005 / 0 205 911 A1, US 2006 / 0 008 965 A1, US 6 376 325 B1 and US 2015 / 0 072 441 A1.

[0003] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced to clarify explanation. Fig. 1A illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) including a FeRAM cell. Fig. 1B illustrates a top view of some embodiments of an integrated circuit (IC) including a FeRAM cell configured with Fig. 1A matches. Fig. 2 illustrates cross-sectional views of various embodiments of an IC including a memory region with one or more FeRAM cells and a peripheral region including logic circuitry spaced from the memory region. Fig. 3 to 13 illustrate a series of cross-sectional views of some embodiments of a method for forming an IC including a FeRAM cell. Fig. 14 illustrates some embodiments of a method in flowchart format for forming an IC including a FeRAM cell. DETAILED DESCRIPTION

[0005] This disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature or a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features need not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for convenience in describing the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative designators used herein may also be interpreted accordingly.

[0007] A single-transistor-one-capacitor (1T1C) memory cell is a type of memory that comprises a capacitor and a transistor. The capacitor stores different amounts of charge corresponding to a single bit of data stored in the capacitor, and the transistor facilitates access to the capacitor for read and write operations. The relatively simple structure of the 1T1C memory cell allows for high storage density, resulting in high storage capacity and low cost per bit. 1T1C memory cells are typically used with dynamic random-access memory (DRAM). However, DRAM reaches performance limits, is volatile, has high power consumption, and depends on complex refresh circuits. Volatile memory is electronic memory that cannot store data without a power supply. A promising alternative to DRAM is ferroelectric random-access memory (FeRAM).Unlike DRAM, FeRAM has lower power consumption, has the potential for better performance, does not depend on complex refresh circuits, and is non-volatile.

[0008] FeRAM memory cells comprise a transistor and a ferroelectric capacitor structure, which includes a ferroelectric structure sandwiched between a top electrode and a bottom electrode. The FeRAM memory cell is configured to store a bit of data depending on how atoms in the ferroelectric capacitor structure are aligned relative to each other. For example, a first state of the FeRAM memory cell, in which atoms in the ferroelectric structure are polarized in an "up" direction, may represent a binary value "1," while a second state of the FeRAM memory cell, in which atoms in the ferroelectric structure are polarized in a "down" direction, may represent a binary value "0," or vice versa.

[0009] However, as understood in some aspects of this disclosure, an etching process during the fabrication of some FeRAM cells may lead to reliability issues. Specifically, during fabrication, a bottom electrode layer is formed, a ferroelectric layer is formed over the bottom electrode layer, and a top electrode layer is formed over the ferroelectric layer; and a mask is formed over the top electrode layer. Then, with the mask in place, an etch is performed to cut through the top electrode layer, the ferroelectric layer, and the bottom electrode layer to form the top electrode, the ferroelectric structure, and the bottom electrode.As the inventors understand, this etching can lead to atoms removed from these layers during the etching process inevitably redepositing as conductive residues on the sidewalls of the ferroelectric structure. These conductive residues can ultimately cause a short circuit between the bottom electrode and the top electrode, leading to failure and / or inoperability of the FeRAM device.

[0010] Therefore, this disclosure utilizes a dielectric sidewall spacer structure disposed along outer sidewalls of the top electrode. This dielectric sidewall spacer structure acts as an electrical barrier to prevent conductive residues generated during device fabrication from causing a short circuit between the bottom electrode and the top electrode. Thus, the dielectric sidewall spacer and the corresponding fabrication process help improve yield for FeRAM devices.

[0011] With reference to Fig. 1A provides a cross-sectional view 100 of some embodiments of an IC including a ferroelectric capacitor structure 102. In some embodiments, the ferroelectric capacitor structure 102 includes a ferroelectric structure 112 disposed between a bottom electrode structure 104 and a top electrode 114. With this structure, the ferroelectric capacitor structure 102 is configured to store a bit of data. For example, a first state of the ferroelectric capacitor structure 102, in which atoms in the ferroelectric structure 112 are polarized in an "up" direction, may represent a binary value "1," while a second state of the ferroelectric capacitor structure 102, in which atoms in the ferroelectric structure 112 are polarized in a "down" direction, may represent a binary value "0," or vice versa.

[0012] The lower electrode structure 104 is overlaid on and electrically coupled to a lower electrode wire 106be. The lower electrode wire 106be may, for example, consist of or comprise aluminum, copper, copper, aluminum, one or more other suitable conductive materials, or a combination of the above. As used herein, a term, for example, with the suffix "(ien)," may represent the singular or plural. In some embodiments, the lower electrode structure 104 has a T-shaped profile or other suitable profile. In some embodiments, the lower electrode structure 104 is homogeneous (e.g., when the entire body of the lower electrode structure 104 is a single material). In other embodiments, the lower electrode structure 104 is heterogeneous (e.g., when the body of the lower electrode structure 104 comprises multiple layers and / or materials).The bottom electrode structure 104 may, for example, consist of or comprise titanium nitride, tantalum nitride, titanium, tantalum, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or a combination of the above. The bottom electrode structure 104 includes a bottom electrode 108 and a bottom electrode via 110. For example, the bottom electrode 108 and the bottom electrode via 110 may be individual regions of the bottom electrode structure 104.

[0013] The lower electrode 108 is electrically coupled to the lower electrode wire 106be through the lower electrode via 110, which extends from the lower electrode 108 to the lower electrode wire 106be. In some embodiments, the ferroelectric structure includes an upper ferroelectric portion 112A having the first width, a lower ferroelectric portion 112B having the second width, and a protrusion 119 corresponding to a height at which the upper ferroelectric portion 112A meets the lower ferroelectric portion 112B. Thus, Fig. 1A illustrates an example in which the bottom electrode 108 and the ferroelectric structure 112 each have a first width, w1, and the top electrode has a second width, w2, where w2 is greater than w1. In some embodiments, the first width is about 10 nm and the second width is about 12 nm. In various embodiments, the first width ranges from about 50% to about 95% of the second width. Further, in some cases, the width of the bottom electrode 108 is uniform or substantially uniform, and / or the width of the bottom electrode via 110 is uniform or substantially uniform. In some embodiments, the bottom electrode 108 and the bottom electrode via 110 are made of or comprise the same material(s). In other embodiments, the bottom electrode 108 and the bottom electrode via 110 are made of different materials.In some embodiments, the bottom electrode 108 and the bottom electrode via 110 are integrated together and / or continuous with each other. In other embodiments, the bottom electrode 108 and the bottom electrode via 110 are independent and / or separate from each other.

[0014] The ferroelectric structure 112 overlies the lower electrode structure 104. The ferroelectric structure 112 may consist of or include, for example, strontium bismuth tantalite (e.g., SBT), lead zirconate titanate (e.g., PZT), hafnium zirconium oxide (e.g., HZO), doped hafnium oxide (e.g., Si:HfO2), one or more other suitable ferroelectric materials, or a combination of the above. The doped hafnium oxide may be doped, for example, with zirconium, silicon, yttrium, aluminum, gadolinium, lanthanum, strontium, one or more other suitable elements, or a combination of the above. The ferroelectric structure 112 is configured to store one bit of data.For example, in a first state, atoms in the ferroelectric structure 112 are polarized in an "up" direction, representing a binary value "1", while in a second state, atoms in the ferroelectric structure 112 are polarized in a "down" direction, representing a binary value "0", or vice versa.

[0015] A top electrode 114 overlies the ferroelectric structure 112. The top electrode 114 may be made of or comprise, for example, titanium nitride, tantalum nitride, titanium, tantalum, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or a combination of the above. The top electrode has a first width w1, measured between its outermost sidewalls, and the ferroelectric structure has a second width w2, measured between its outermost sidewalls. The second width is greater than the first width, such that the ferroelectric structure includes a protrusion 119 reflecting a difference between the first width and the second width.

[0016] In some embodiments, a hard mask 116 overlies the top electrode 114. The hard mask 116 may, for example, serve as a mask in the formation of the top electrode 114, the ferroelectric structure 112, and the bottom electrode 108. Furthermore, the hard mask 116 may, for example, consist of or include silicon nitride, silicon oxynitride, one or more other suitable dielectrics, or a combination of the above.

[0017] A dielectric sidewall spacer structure 118 is located on outer sidewalls of the ferroelectric structure 112 and may extend partially into an upper surface of the ferroelectric structure 112. A lower surface of the dielectric sidewall spacer structure rests on the protrusion 119 and is spaced from an upper surface of the lower electrode 108. Viewed in cross-section, the dielectric sidewall spacer structure 118 includes a pair of spacer segments, and the spacer segments are each located on opposite outer sides of the ferroelectric structure 112. The spacer segments have curved upper sidewalls. In cross-section of Fig. 1A, it can be seen that the spacer segments have inner sidewalls that are vertical and outer sidewalls that are rounded and / or conical. The dielectric sidewall spacer structure 118 may have a height, h s, from about 5 nm to about 50 nm and may have a bottom surface on protrusion 119 that may correspond to the bottom surface of 114 or may be located below the bottom surface of 114 and within the ferroelectric structure 112. Each spacer segment of the dielectric sidewall spacer structure 118 may have a width, w s , from about 5 nm to about 50 nm, and the ratio of the width, w s , to the width, w1, (w s :w1) in some embodiments may range from 1:20 to 2:1, although other values ​​for this example and other examples in this application are within the scope of this disclosure. As shown in the plan view of Fig. As seen from above in Figure 1B, in some embodiments, the dielectric sidewall spacer structure 118 may be a continuous spacer laterally surrounding an outer sidewall of the top electrode 114. The dielectric sidewall spacer structure 118 may, for example, be made of or comprise silicon nitride, silicon oxide, another suitable dielectric or multiple suitable dielectrics, or a combination of the above. In some embodiments, the dielectric sidewall spacer structure 118 and the hard mask 116 may be made of or comprise the same material(s).

[0018] As in Fig. 1A, in some embodiments, a conductive remnant 117 may be formed on outer sidewalls of the dielectric sidewall spacer structure 118 and in direct physical and electrical contact with the bottom electrode 108. The conductive remnant 117 may be spaced from outer sidewalls of the top electrode 114 and insulated therefrom by the dielectric sidewall spacer structure 118, such that the dielectric sidewall spacer structure 118 prevents the conductive remnant 117, if present, from shorting the top electrode 114 to the bottom electrode structure 104. Thus, the conductive remnant 117 may comprise chemical species included in the ferroelectric layer and / or the bottom electrode layer that were redeposited during manufacturing along outermost sidewalls of the dielectric sidewall spacer structure.The conductive remnant 117 may be a continuous layer in some cases, but in other cases may be patchy or discontinuous across the underlying surfaces. For example, in some cases, the conductive remnant 117 may be a fully formed blanket with a uniform or non-uniform thickness covering the top surface of the mask 116, the top and sidewall surfaces of the dielectric sidewall spacer structure 118, the outer sidewalls of the ferroelectric structure 112, and the outer sidewalls of the bottom electrode 108.In other embodiments, the conductive remnant 117 may be patchy in that the conductive remnant 117 covers some, but not all, portions of the top surface of the mask 116, the top and sidewall surfaces of the dielectric sidewall spacer structure 118, the outer sidewalls of the ferroelectric structure 112, and the outer sidewalls of the bottom electrode 108; for example, it may cover more than 1% but less than 100% of the underlying surfaces, although other values ​​for this example and other examples in this application are within the scope of this disclosure.

[0019] In some embodiments, a first dielectric liner 128 and / or a second dielectric liner 130 laterally surround the sidewall spacer dielectric structure 118, the ferroelectric structure 112, and the bottom electrode 108. The first dielectric liner 128 may, for example, serve as an etch stop during the formation of adjacent vias and / or may, for example, consist of or comprise silicon carbide, another suitable dielectric (or dielectrics), or a combination of the above. The second dielectric liner 130 may, for example, consist of or comprise TEOS silicon dioxide, another suitable dielectric (or dielectrics), or a combination of the above.

[0020] A top electrode wire 106te and a top electrode via 120te overlie the top electrode 114. The top electrode via 120te extends from the top electrode wire 106te to the top electrode 114 for electrically coupling the top electrode wire 106te to the top electrode 114. In some embodiments, the top electrode wire 106te and the top electrode via 120te are made of the same material. In other embodiments, the top electrode wire 106te and the top electrode via 120te are made of different materials. In some embodiments, the top electrode wire 106te and the top electrode via 120te are integrated with each other and / or continuous with each other. In other embodiments, the top electrode wire 106te and the top electrode via 120te are independent and / or separate from each other.

[0021] The lower and upper electrode wires 106be, 106te, the upper electrode via 120te, and the ferroelectric capacitor structure 102 are surrounded by a dielectric structure. The dielectric structure includes a lower dielectric interconnect layer 122, a dielectric via layer 124 overlying the lower dielectric interconnect layer 122, and an upper dielectric interconnect layer 126 overlying the dielectric via layer 124. The dielectric structure may, for example, consist of or comprise tetraethylorthosilicate (TEOS) silicon dioxide, another suitable silicon dioxide, silicon oxynitride, a low-kappa dielectric, silicon carbide, silicon nitride, another suitable dielectric, or a combination of the above.As used herein, a low-kappa dielectric may, for example, be a dielectric having a dielectric constant kappa of less than about 3.9, 3, 2, or 1. In some embodiments, the lower and upper interconnect dielectric layers 122, 126 are made of or comprise silicon oxide, a low-kappa dielectric, another suitable dielectric or multiple other suitable dielectrics, or a combination of the above, and / or the via dielectric layer 124 is made of or comprise silicon carbide, silicon nitride, silicon oxynitride, another suitable dielectric or multiple other suitable dielectrics, or a combination of the above.

[0022] With reference to Fig. 2, a cross-sectional view 200 of some embodiments of an IC is provided. The IC includes a memory region 402 including one or more ferroelectric capacitor structures, and a peripheral region 404 including one or more logic devices.

[0023] Within the storage region 402, the ferroelectric capacitor structure 102 is defined from Fig. 1 shows a first storage capacitor structure 102a and a second storage capacitor structure 102b. The first storage capacitor structure 102a overlies an access transistor 304 and is electrically coupled thereto by an interconnect structure 306. Thus, this is an example configuration of a ferroelectric random access memory (FeRAM) device. The access transistor 304 overlies a semiconductor substrate 308 and may, for example, be a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a fin field-effect transistor (FinFET), another suitable insulated gate field-effect transistor (IGFET), or another suitable transistor. The semiconductor substrate 308 may, for example, be a monocrystalline bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or another suitable semiconductor substrate.

[0024] The access transistor 304 includes a pair of memory source / drain regions 310, a selectively conductive memory channel 312, a memory gate dielectric layer 314, and a memory gate electrode 316. The memory source / drain regions 310 and the selectively conductive memory channel 312 are disposed within the semiconductor substrate 308, and the selectively conductive memory channel 312 extends laterally from one of the memory source / drain regions 310 to another of the memory source / drain regions 310. The memory gate dielectric layer 314 and the memory gate electrode 316 are stacked over the semiconductor substrate 308 and interposed between the memory source / drain regions 310. The memory gate dielectric layer 314 may be made of or include, for example, silicon oxide, a high-k dielectric layer, another suitable dielectric or a plurality of other suitable dielectrics, or a combination of the above.The memory gate electrode 316 may be made of or comprise, for example, doped polysilicon, metal, one or more other conductive materials, or a combination of the above.

[0025] In some embodiments, an isolation structure 318 extends into the top surface of the semiconductor substrate 308 to provide electrical isolation between the access transistor 304 and other semiconductor devices in the semiconductor substrate 308. In some embodiments, the isolation structure 318 laterally surrounds an active area of ​​the access transistor 304. The isolation structure 318 may, for example, consist of or include a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, one or more other suitable isolation structures, or a combination of the above.

[0026] The interconnect structure 306 overlies the access transistor 304 and the semiconductor substrate 308. The interconnect structure 306 includes a dielectric structure and further includes a plurality of wires 106 and a plurality of vias 120. For ease of illustration, only some of the wires 106 and vias 120 are labeled, while others are unlabeled. The dielectric structure includes the lower dielectric interconnect layer 122, the via dielectric layer 124 overlying the lower dielectric interconnect layer 122, and the upper dielectric interconnect layer 126 overlying the via dielectric layer 124. In some embodiments, the dielectric structure further includes a first dielectric liner 128 and / or a second dielectric liner 130.The first and / or second dielectric liners 128, 130 further separate the ferroelectric structure 112 and the via dielectric layer 124 from the upper dielectric interconnect layer 126. The first dielectric liner 128 may, for example, serve as an etch stop during the formation of adjacent vias and / or may, for example, consist of or comprise silicon carbide, another suitable dielectric (or dielectrics), or a combination of the above. The second dielectric liner 130 may, for example, consist of or comprise TEOS silicon dioxide, another suitable dielectric (or dielectrics), or a combination of the above.

[0027] The plurality of wires 106 include the lower and upper electrode wires 106be, 106te, and the plurality of vias 120 include the upper electrode via 120te. The wires 106 and the vias 120 are alternately stacked in the dielectric structure to define conductive paths, one of which electrically couples the lower electrode wire 106be to one of the memory source / drain regions 310. Further, the wires 106 and the vias 120 are each grouped into wire levels and via levels. A wire level is a set of wires with a common height above the semiconductor substrate 308, and a via level is a set of vias with a common height above the semiconductor substrate 308. The upper electrode wire 106te is located in the wire level directly above the wire level that houses the lower electrode wire 106be.In some embodiments, as illustrated, the lower electrode wire 106be is located in wire level 4, which in some contexts may also be referred to as Metal4 (M4). However, in other embodiments, the lower electrode wire 106be may also be located in all other wire levels / metal layers. For example, in other embodiments, the lower electrode wire 106be may be located in wire level 1.

[0028] The first storage capacitor structure 102a, the access transistor 304, and the electrical interconnections between the first storage capacitor structure 102a and the access transistor 304 define a first 1T1C FeRAM memory cell. Note that the electrical interconnections between the first storage capacitor structure 102a and the access transistor 304 are defined by the wires 106 and the vias 120. In some embodiments, the first 1T1C FeRAM memory cell is one of many 1T1C FeRAM memory cells arranged in rows and columns to define a memory array. In some such embodiments, the plurality of wires 106 include a source row wire 106sl defining a source row of the memory array, the memory gate electrode 316 defining a word row of the memory array, the top electrode wire 106te defining a bit row of the memory array, or a combination of the above.For example, the bottom electrode wire 106be and the source row wire 106sl may each be electrically coupled to the memory source / drain regions 310.

[0029] In the peripheral region 404 of the IC, the metal layers of the interconnect structure are spaced at the same distances or heights as in the memory region 402. The peripheral region 404 includes a logic transistor 408, which includes a pair of logic source / drain regions 410, a selectively conductive logic channel 412, a logic gate dielectric layer 414, and a logic gate electrode 416. The logic source / drain regions 410 and the selectively conductive logic channel 412 are disposed within the semiconductor substrate 308, and the selectively conductive logic channel 412 extends laterally from one of the logic source / drain regions 410 to another of the logic source / drain regions 410. The logic gate dielectric layer 414 and the logic gate electrode 416 are stacked over the semiconductor substrate 308 and interposed between the logic source / drain regions 410.The logic gate dielectric layer 414 may, for example, consist of or comprise silicon oxide, a high-k dielectric layer, one or more other suitable dielectrics, or a combination of the above. The logic gate electrode 416 may, for example, consist of or comprise doped polysilicon, metal, one or more other conductive materials, or a combination of the above.

[0030] With reference to Fig. 3 to 13 illustrate a series of cross-sectional views 300 to 1300 of some embodiments of a method for forming an IC comprising a ferroelectric capacitor structure, wherein the ferroelectric capacitor structure is a portion of a 1T1C memory cell. The method may be used, for example, to form an IC in one of the Fig. 1 to 2. While the cross-sectional views 300 to 1300, which are shown in Fig. 3 to 13 are described with reference to a method, it is to be understood that the structures of Fig. 3 to 13 are not limited to the procedure and can be taken alone without the procedure.

[0031] As shown in cross-sectional view 300 in Fig. 3, the IC includes a memory region 402 corresponding to one or more ferroelectric capacitor structures, as well as a peripheral region 404 corresponding to one or more logic devices. Note that for a more compact drawing, a lower portion of the IC (shown in Fig. 2) in Fig. 3 to 13 has been omitted. A planarization is applied to the upper surface of the lower dielectric interconnect layer 122 or the upper surfaces of the wires (e.g. 106be in Fig. 1) along the upper surface of the lower dielectric interconnect layer 122 such that the upper surface of the lower dielectric interconnect layer 122 is equal to or approximately equal to the upper surfaces of the respective wires along the upper surface of the lower dielectric interconnect layer 122. The planarization may be performed, for example, by CMP, one or more other suitable planarization processes, or a combination of the above.

[0032] As shown in cross-sectional view 400 of Fig. 4, a dielectric via layer 124 is formed covering the lower dielectric interconnect layer 122. The dielectric via layer 124 may be made of, or may include, silicon carbide, silicon nitride, one or more other suitable dielectrics, or a combination of the above. The dielectric via layer 124 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), one or more other suitable deposition processes, or a combination of the above.

[0033] As shown in cross-sectional view 500 of Fig. 5, the dielectric via layer 124 is patterned to form a plurality of storage openings 502. The storage openings 502 each overlie and expose the lower electrode wires 106be. In some embodiments, the patterning is performed by an etching process, one or more other suitable patterning processes, or a combination of the above. In some embodiments, the etching process includes forming a mask 506 on the dielectric via layer 124, performing an etch into the dielectric via layer 124 with the applied mask 506, and removing the mask 506 after the etching. The mask 506 may, for example, be made of or include photoresist, silicon nitride, one or more other suitable mask materials, or a combination of the above.

[0034] As shown in cross-sectional view 600 of Fig. 6, a conductive liner layer 602 is formed covering the dielectric via layer 124 and lining the memory openings 502 (see Fig. 5). Further, a lower conductive body layer 604 is formed, covering the conductive liner layer 602 and filling the storage openings 502. The conductive liner layer 602 and the lower conductive body layer 604 fully or partially define the lower electrode vias 110 in the storage openings 502. Furthermore, the conductive liner layer 602 is configured to prevent material from the lower conductive body layer 604 from moving away from the lower conductive body layer 604 toward the surrounding structure. The conductive liner layer 602 may, for example, consist of or comprise titanium nitride, titanium, tantalum nitride, tantalum, one or more other suitable conductive barrier materials for the lower conductive body layer 604, or a combination of the above.The lower conductive body layer 604 may be made of or comprise, for example, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or a combination of the above. The conductive liner layer 602 and the lower conductive body layer 604 may be formed, for example, by CVD, PVD, electroless plating, electroplating, sputtering, one or more other suitable deposition processes, or a combination of the above.

[0035] As shown in cross-sectional view 700 of Fig. 7, a planarization is formed in the upper surfaces of the conductive lining layer 602 (see Fig. 6) and the lower conductive body layer 604 (see Fig. 6) until an upper surface of the dielectric via layer 124 is reached. The planarization may be performed, for example, by CMP, one or more other suitable planarization processes, or a combination of the above.

[0036] As shown in cross-sectional view 800 of Fig. 8, an upper conductive body layer 802, a ferroelectric layer 804, a top electrode layer 806, and a hard mask layer 808 are formed on the via dielectric layer 124 and the lower conductive body layer 604. The upper conductive body layer 802 may be made of, or include, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or a combination of the above. Often, the upper conductive body layer 802 is made of the same material as the lower conductive body layer 604, but in alternative embodiments, they may be made of different materials.The ferroelectric layer 804 may, for example, consist of or comprise strontium bismuth tantalite, lead zirconate titanate, hafnium zirconium oxide, doped hafnium oxide, one or more other suitable ferroelectric materials, or a combination of the above. The top electrode layer 806 may, for example, consist of or comprise titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or a combination of the above. The hard mask layer 808 may, for example, consist of or comprise silicon nitride, silicon oxynitride, silicon oxide, one or more other suitable dielectrics, or a combination of the above.

[0037] A process for forming the stack may include, for example, depositing the upper conductive body layer 802, subsequently depositing the ferroelectric layer 804, subsequently depositing the upper electrode layer 806, and subsequently depositing the hard mask layer 808. The upper conductive body layer 802, the ferroelectric layer 804, the upper electrode layer 806, and the hard mask layer 808 may be formed, for example, by CVD, PVD, ALD, electroless plating, electroplating, one or more other suitable deposition processes, or a combination of the above.

[0038] As shown in cross-sectional view 900 of Fig. 9, the upper electrode layer 806 (see Fig. 8), and the hard mask layer 808 (see Fig. 8) to form the top electrodes 114 and hard masks 116. This etch may extend into the top surface of the ferroelectric layer 804, in some embodiments, for example, reaching from 5% to about 30% into the depth of the ferroelectric layer 804 to build up a protrusion (see, e.g., protrusion 119 in Fig. 1).

[0039] The patterning may be performed, for example, by an etching process, one or more other suitable patterning processes, or a combination of the above. The etching process may, for example, include: forming a mask 902 on the hard mask layer 116; performing an etch into the upper electrode layer and the hard mask layer with the applied mask 902; thereby forming upper electrodes 114 and the hard mask 116. The mask 902 may be removed after etching. The mask 902 may, for example, consist of or include photoresist, a hard mask, and / or one or more other suitable mask materials, or a combination of the above.

[0040] As shown in the cross-sectional view 1000 from Fig. 10, a dielectric spacer layer 1002, such as silicon nitride or silicon oxynitride, is formed over a top surface of the ferroelectric structure 112 along sidewalls of upper electrodes 114 and along sidewalls and upper surfaces of hard masks 116. The dielectric spacer layer 1002 is therefore a continuous dielectric layer over the structure of Fig. 9, and is generally compliant.

[0041] As shown in cross-sectional view 1100 of Fig. 11, the dielectric spacer layer (see e.g. 1002 in Fig. 10) using a first etch, such as a dry etch or plasma etch with a strong vertical component, typically without forming another mask after the dielectric spacer layer has been formed. Thus, the etch removes lateral portions of the dielectric spacer layer (see, e.g., 1002 in Fig. 10), leaving the dielectric sidewall spacer structure 118 after the etching. The second etch is then performed with the existing dielectric sidewall spacer structure 118 to expose exposed portions of the ferroelectric layer (see, e.g., 804 in Fig. 8) and the upper conductive body layer (see e.g. 802 in Fig. 8). This etching may cause the conductive residue 117, which includes chemical species etched / removed from the ferroelectric layer 804 and / or the upper conductive body 802, to form on outer sidewalls of the lower electrode, outer sidewalls of the ferroelectric layer, and / or outer sidewalls of the dielectric sidewall spacer structure 118, as well as on the upper surface of the dielectric sidewall spacer structure 118 and the upper surface of the hard mask 116. However, for the dielectric sidewall spacer structure 118, this conductive residue may short the upper electrode and the lower electrode together, resulting in device inoperability.In some cases, rather than being a continuous layer, the conductive remnant 117 may be "patchy" or "piecemeal," covering some portions of the exposed structure but not other portions of the exposed structure. Furthermore, due to the way the etching and redeposition of the conductive remnant progresses from the top of the structure to the bottom of the structure, the conductive remnant 117 may be thicker toward the top of the dielectric spacer structure 118 and thinner toward the bottom electrode, although other structures for this example and other examples in this application are also within the scope of this disclosure.

[0042] As shown in cross-sectional view 1200 of Fig. 12, a first dielectric liner 128 and a second dielectric liner 130 are formed, covering the via dielectric layer 124 and the memory structures. For example, in some embodiments, the first dielectric liner 128 may be made of or comprise silicon carbide, and the second dielectric liner 130 may be made of TEOS silicon dioxide. A top dielectric interconnect layer 126 is then formed to cover the first dielectric liner 128 and the second dielectric liner 130 and may be made of or comprise, for example, silicon oxide, a low-kappa dielectric, one or more other suitable dielectrics, or a combination of the above.

[0043] As shown in cross-sectional view 1300 of Fig. 13, planarization is performed into an upper surface of the upper dielectric interconnect layer 126 to smooth the upper surface. The planarization may be performed, for example, by CMP, one or more other suitable planarization processes, or a combination of the above. Then, openings are formed in the upper dielectric interconnect layer 126, and vias (e.g., 120te and 120) and metal wires (e.g., 106te, 1304) are formed in the openings. The vias and metal wires may be formed, for example, by a damascene process or a dual damascene process. The vias and metal wires may be made of or include, for example, copper, aluminum, nickel, titanium, tantalum, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, one or more other suitable conductive materials, or a combination of the above.In the peripheral region 404 of the IC, the metal layers of the interconnect structure may be spaced at the same distances or heights as in the memory region 402, simplifying the integration of the memory region 402 and the peripheral region 404. For example, the metal layers 1302, 1304 in the peripheral region 404 may have the same vertical spacing as 106be and 106te in the memory region 402.

[0044] Fig. 14 illustrates a method in flowchart format 1400 according to some embodiments.

[0045] In act 1402, a bottom electrode layer is formed and a ferroelectric layer is formed over the bottom electrode layer. An upper electrode layer is formed over the ferroelectric layer. In some embodiments, this act may, for example, involve all or portions of Fig. 3 to 8 be consistent.

[0046] In act 1404, a mask is formed over the upper electrode layer. In some embodiments, this act may, for example, involve all or portions of Fig. 9. be consistent.

[0047] In act 1406, an etch is performed with the existing mask to remove a portion of the upper electrode layer to leave a top electrode structure. The etch is interrupted at a height corresponding to an area of ​​the ferroelectric layer. In some embodiments, this act may, for example, be performed with all or portions of Fig. 9. be consistent.

[0048] In act 1408, a conformal dielectric layer is formed along over the surface of the ferroelectric layer, along sidewalls of the top electrode structure, and over a top surface of the top electrode structure. In some embodiments, this act may, for example, involve all or portions of Fig. 10. Be consistent.

[0049] In act 1410, the conformal dielectric layer is etched back to form a dielectric sidewall spacer structure on the surface of the ferroelectric layer and along sidewalls of the top electrode structure and along sidewalls of the mask. In some embodiments, this act may, for example, be performed with all or portions of Fig. 11. be consistent.

[0050] At 1412, with the mask and dielectric sidewall spacer structure in place, a portion of the ferroelectric layer and a portion of the bottom electrode layer are removed. In some embodiments, this action may be performed, for example, with all or portions of Fig. 11. be consistent.

[0051] In 1414, a first liner is formed along outermost sidewalls of the dielectric sidewall spacer structure and over a top surface of the hard mask. In some embodiments, this action may, for example, involve all or portions of Fig. 12. be consistent.

[0052] In 1416, a second liner is formed along outermost sidewalls of the first liner and over a top surface of the first liner. In some embodiments, this action may, for example, involve all or portions of Fig. 12. be consistent.

[0053] At 1418, a via is formed through the first liner and through the second liner to make electrical contact with the top electrode. In some embodiments, this action may, for example, be performed with all or portions of Fig. 13. be consistent.

[0054] Thus, some embodiments relate to a memory device. The memory device includes a bottom electrode structure and a top electrode overlying the bottom electrode structure. The top electrode has a first width. A ferroelectric structure separates the bottom electrode structure from the top electrode, and the ferroelectric structure has a second width greater than the first width, such that the ferroelectric structure includes a protrusion reflecting a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the protrusion and covers outermost sidewalls of the top electrode.

[0055] Other embodiments relate to the method. In this method, a bottom electrode layer is formed, a ferroelectric layer is formed over the bottom electrode layer, and a top electrode layer is formed over the ferroelectric layer. A mask is formed over the top electrode layer. With the mask in place, an etch is performed to remove a portion of the top electrode layer to leave a top electrode structure. The etch stops at a height corresponding to an area of ​​the ferroelectric layer. A conformal dielectric layer is formed over the area of ​​the ferroelectric layer, along sidewalls of the top electrode structure, and over a top surface of the top electrode structure.The conformal dielectric layer is etched back to form a dielectric sidewall spacer structure on the surface of the ferroelectric layer and along the sidewalls of the top electrode structure. With the mask and dielectric sidewall spacer structure in place, a portion of the ferroelectric layer and a portion of the bottom electrode layer are removed.

[0056] Furthermore, other embodiments relate to a memory device comprising a bottom electrode structure and an top electrode overlying the bottom electrode structure. The top electrode has a first width measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure includes an upper ferroelectric portion having the first width and a lower ferroelectric portion having a second width greater than the first width such that a protrusion corresponds to a height at which the upper ferroelectric portion meets the lower ferroelectric portion. A dielectric sidewall spacer structure is disposed on the protrusion and covers outermost sidewalls of the top electrode.

Claims

[1] A storage device comprising: a lower electrode structure (104); an upper electrode (114) overlying the lower electrode structure (104), the upper electrode (114) having a first width; a ferroelectric structure (112) separating the lower electrode structure (104) from the upper electrode (114), the ferroelectric structure (112) having a second width that is greater than the first width such that the ferroelectric structure (112) includes a protrusion (119) that reflects a difference between the first width and the second width; a dielectric sidewall spacer structure (118) disposed on the protrusion (119) and covering outermost sidewalls of the upper electrode (114); a conductive remnant (117) disposed along outermost sidewalls of the dielectric sidewall spacer structure (118), along outermost sidewalls of the ferroelectric structure (112), and along outermost sidewalls of the lower electrode structure (104); and a hard mask (116) over a top surface of the top electrode (114), wherein the conductive remnant (117) is further disposed on a top surface of the dielectric sidewall spacer structure (118) and directly on a top surface of the hard mask (116). [2] The memory device of claim 1, wherein the ferroelectric structure (112) comprises an upper ferroelectric portion (112A) having the first width and a lower ferroelectric portion (112B) having the second width, and the protrusion (119) corresponds to a height at which the upper ferroelectric portion (112A) meets the lower ferroelectric portion (112B). [3] The memory device of claim 2, wherein the protrusion (119) is separated from a top surface of the ferroelectric structure (112) by a distance that is about 5% to about 30% of a total height of the ferroelectric structure (112). [4] A storage device according to any one of the preceding claims, further comprising: a first dielectric liner (128) along the outermost sidewalls of the dielectric sidewall spacer structure (118) and over the top surface of the hard mask. [5] A memory device according to any preceding claim, wherein the first dielectric liner (128) comprises silicon carbide. [6] A storage device according to any one of the preceding claims, further comprising: a second dielectric liner (130) along outermost sidewalls of the first dielectric liner (128) and over a top surface of the first dielectric liner (128). [7] A storage device according to any one of the preceding claims, further comprising: a metal line extending over the upper electrode (114); and a conductive via extending through the hard mask, the first dielectric liner (128) and the second dielectric liner (130) to electrically couple the metal line to the top electrode (114). [8] Method comprising: Forming a lower electrode layer (802), a ferroelectric layer (804) over the lower electrode layer (802) and an upper electrode layer (806) over the ferroelectric layer (804); Forming a mask (116) over the upper electrode layer (806); with the existing mask (116), performing an etch to remove a portion of the upper electrode layer (806) to leave an upper electrode structure (114) and interrupting the etching at a height corresponding to an area of the ferroelectric layer (804); Forming a conformal dielectric layer (1002) over the surface of the ferroelectric layer (804), along sidewalls of the top electrode structure (114) and over a top surface of the top electrode structure (114); Etching back the conformal dielectric layer (1002) to form a dielectric sidewall spacer structure (118) on the surface of the ferroelectric layer (804) and along sidewalls of the top electrode structure (114); and with the existing mask (116) and dielectric sidewall spacer structure (118), removing a portion of the ferroelectric layer (804) and removing a portion of the lower electrode layer (802), wherein removing the portion of the ferroelectric layer (804) and removing the portion of the lower electrode layer (802) results in chemical species being removed from the ferroelectric layer (804) and the lower electrode layer (802) and redepositing along outermost sidewalls of the dielectric sidewall spacer structure (118), on outer sidewalls of a remaining portion of the lower electrode layer (802), on outer sidewalls of a remaining portion of the ferroelectric layer (804), on an upper surface of the dielectric sidewall spacer structure (118), and directly on an upper surface of the mask (116). [9] The method of claim 8, further comprising: Forming a first SiC liner (128) along the outermost sidewalls of the dielectric sidewall spacer structure (118) and over the top surface of the mask (116). [10] The method of claim 9, further comprising: Forming a TEOS liner (130) along outermost sidewalls of the SiC liner (128) and over a top surface of the SiC liner (128). [11] The method of claim 10, further comprising: Forming a via (120te) through the SiC liner (128) and through the TEOS liner (130) to make electrical contact with the top electrode structure (114). [12] A storage device comprising: a lower electrode structure (104); an upper electrode (114) overlying the lower electrode structure (104), the upper electrode (114) having a first width as a measurement between outermost sidewalls of the upper electrode (114); a ferroelectric structure (112) separating the lower electrode structure (104) from the upper electrode (114), the ferroelectric structure (112) comprising an upper ferroelectric portion (112A) having the first width and a lower ferroelectric portion (112B) having a second width greater than the first width, such that a protrusion (119) corresponds to a height at which the upper ferroelectric portion (112A) meets the lower ferroelectric portion (112B); a dielectric sidewall spacer structure (118) disposed on the protrusion (119) and covering the outermost sidewalls of the upper electrode (114); a conductive remnant (117) disposed along outermost sidewalls of the dielectric sidewall spacer structure (118), along outermost sidewalls of the ferroelectric structure (112), and along outermost sidewalls of the lower electrode structure (104); and a dielectric hard mask (116) disposed over the upper electrode (114) and disposed within inner sidewalls of the dielectric sidewall spacer structure (118), wherein the conductive residue (1 17 ) is further disposed on an upper surface of the dielectric sidewall spacer structure (118) and directly on an upper surface of the dielectric hard mask (116). [13] The storage device of claim 12, further comprising: a first liner (128) along the outermost sidewalls of the dielectric sidewall spacer structure (118) and over the top surface of the dielectric hard mask (116); a second liner (130) along outermost side walls of the first liner (128) and over a top surface of the first liner (128), the second liner (130) having a second composition that is different from a first composition of the first liner (128); and a via (120te) extending through the dielectric hard mask (116), through the first liner (128) and through the second liner (130) to make electrical contact with the top electrode (114). [14] The memory device of claim 12 or 13, wherein the protrusion (119) is separated from a top surface of the ferroelectric structure (112) by a distance that is about 5% to about 30% of a total height of the ferroelectric structure (112). [15] The memory device of any one of the preceding claims 12 to 14, wherein the conductive residue (117) comprises a chemical species and the ferroelectric structure (112) comprises the chemical species.

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