MANUFACTURING TECHNOLOGIES FOR NON-VOID STORAGE ARRANGEMENTS

Abstract

Methods for manufacturing a memory cell, comprising: Forming a memory cell stack (204) over a substrate (102), wherein the memory cell stack (204) has a lower electrode layer (1002), a resistive switching dielectric layer (1004) over the lower electrode layer (1002) and an upper electrode layer (1006) over the resistive switching dielectric layer (1004); Forming a first insulating layer (1108) over the upper electrode layer (1006); Forming a first metal hard mask layer (1110) over the first insulating layer (1108); and Performing an etching series to structure the first metal hard mask layer (1110), the first insulating layer (1108), the upper electrode layer (1006) and the resistance switching dielectric layer (1004) to form a first metal hard mask (1110), a hard mask insulator (120), an upper electrode (118) and a resistance switching dielectric (116); Furthermore, comprehensively, before carrying out the etching series: Forming a second insulating layer (1112) over the first metal hard mask layer (1110); and Forming a second metal hard mask layer (1114) over the second insulating layer (1112).

Description

BACKGROUND

[0001] Many modern electronic devices incorporate electronic memory. Electronic memory can be volatile or non-volatile (NVM). Non-volatile memory can retain data even without power, while volatile memory cannot. Non-volatile memory, such as magnetoresistive random-access memory (MRAM) and resistive random-access memory (RRAM), is a promising candidate for next-generation non-volatile memory technology due to its relatively simple structures and compatibility with CMOS logic manufacturing processes.

[0002] Patent application US 2012 / 0091425A1 relates to a non-volatile storage device comprising an upper electrode layer; a lower electrode layer; a variable-resistance layer arranged between the upper electrode layer and the lower electrode layer; and a charge diffusion prevention mask formed on a portion of the upper electrode layer. The variable-resistance layer comprises a first film containing a low-oxygen transition metal oxide and a second film containing a low-oxygen transition metal oxide with a higher oxygen content than the first film.

[0003] In US patent application 9,779,794 B2, techniques for forming a spin-transfer torque memory (STTM) element with an annular contact are disclosed to reduce critical current requirements. These techniques reduce the critical current requirements for a given magnetic tunnel junction because the annular contact reduces the contact size and increases the local current density, thereby decreasing the current required to switch the direction of the MTJ's free magnetic layer.

[0004] Document US 2016 / 0351799A1 describes magnetic random-access memory devices comprising a film stack with a magnetic tunnel junction layer, a dielectric cover layer, an etch stop layer, a conductive hard mask layer, a dielectric hard mask layer, a spin-on carbon layer, and an antireflective coating layer. The film stack can be etched by one or more selected chemicals to achieve improved verticality of the film stack's sidewall.

[0005] Document DE 10 2019 107 906 A1 discloses an integrated chip with one or more lower interconnect layers arranged in a dielectric structure over a substrate.

[0006] Publication US 2020 / 0 020 745 A1 concerns an integrated circuit with a first dielectric intermediate layer over a substrate.

[0007] In publication KR 10 2003 0 002 095 A, a lower electrode, a ferroelectric layer, and an upper electrode are stacked sequentially on a semiconductor substrate. A dielectric hard mask and a metallic hard mask are formed successively on the upper electrode. A photoresist pattern is formed on the metallic hard mask to define a capacitor. The metallic hard mask and the dielectric hard mask are etched simultaneously using the photoresist pattern.

[0008] Publication US 2016 / 0351806A1 relates to an integrated circuit device with an RRAM cell and an associated manufacturing process. The integrated circuit device has a lower electrode arranged over a lower metal compound layer. The integrated circuit device also has a resistive layer with variable resistance arranged on the lower electrode and an upper electrode arranged over the resistive layer.

[0009] In US Publication 2014 / 0097396A1, a non-volatile storage device comprises a first electrode; a variable resistive layer formed on and over the first electrode; a second electrode formed on and over the variable resistive layer; a sidewall protective layer with insulating capability covering one sidewall of the first electrode, one sidewall of the variable resistive layer, and one sidewall of the second electrode; and an electrically conductive layer connected to the second electrode; wherein the non-volatile storage device includes a connecting layer provided between the second electrode and the electrically conductive layer to connect the second electrode and the electrically conductive layer.

[0010] In US patent 2017 / 0141300A1, a metal-insulator-metal capacitor structure of an RRAM device comprises a first electrode and a second electrode with an insulating layer positioned between the first and second electrodes. The conductive filament, which provides the switching function of the RRAM device, may be located within the insulating layer. Furthermore, a nitrogen-rich metal layer is positioned between the second electrode and the insulating layer. The nitrogen-rich metal layer has a higher nitrogen concentration than the adjacent second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a schematic representation of the production of a memory cell. Fig. Figure 2 shows a cross-sectional view of some embodiments of a memory cell with a hard mask stack having an insulating layer. Fig. Figure 3 shows a cross-sectional view of some alternative embodiments of a memory cell of the Fig. 2 with a hard mask stack having several insulating layers. Fig. Figure 4 shows a cross-sectional view of some embodiments of a memory cell with an insulating hard mask, wherein the memory cell of the Fig. 4. A final product can be produced after the memory cell of the Fig. 2 or Fig. 3 is structured according to the hard mask stack. Fig. Figure 5 shows a cross-sectional view of some alternative embodiments of a memory cell of the Fig. 5 with insulating hard mask. Fig. Figure 6 shows a cross-sectional view of some alternative embodiments of a memory cell. Fig. 4 and Fig. 5 with insulating hard mask. Fig. Figure 7 shows a cross-sectional view of some embodiments of an integrated circuit with the memory cell of the Fig. 4, Fig. 5 or Fig. 6. Fig. Figures 8-19 show a series of cross-sectional views of some embodiments of an integrated circuit at various stages of manufacture, wherein the integrated circuit includes a memory cell. Fig. Figure 20 shows a flowchart of some embodiments of a method for manufacturing an integrated circuit with a memory cell. DETAILED DESCRIPTION

[0012] The present disclosure provides many different embodiments or examples of the implementation of various features of this disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For instance, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the various examples of the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0013] Furthermore, for the sake of simplicity, spatially relative terms such as "above," "above," "over," "below," "below," "under," and the like can be used here to describe the relationship of one element or feature to one or more other elements or features, as shown in the drawings. These spatially relative terms are intended to encompass various orientations of the device during use or operation, in addition to the orientation shown in the drawings. The device may be arranged differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here can be interpreted accordingly.

[0014] Furthermore, for the sake of simplicity, terms like "first," "second," "third," etc., can be used here to distinguish between different elements of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding element. Therefore, "a first dielectric layer" described in connection with a first figure does not necessarily correspond to "a first dielectric layer" described in connection with a different figure.

[0015] Non-volatile memory such as magnetoresistive random-access memory (MRAM) or resistive random-access memory (RRAM) comprises an array of memory cells. A memory cell consists of a stack with an upper electrode and a lower electrode separated by a resistive switching dielectric. Depending on a voltage applied to the electrode pair, the resistive switching dielectric undergoes a reversible transition between a high-resistance state associated with a first data state (for example, "0" or "RESET") and a low-resistance state associated with a second data state (for example, "1" or "SET"). The resistive switching dielectric can be made of several materials.For example, the resistive switching dielectric layer can have a magnetic tunnel junction (MTJ) structure with a pinned magnetic layer and a free magnetic layer vertically separated by a dielectric barrier layer. Given the ongoing demand for ever smaller pitch sizes, structuring the memory cell stacks at small dimensions and very dense pitches remains a challenge for high-density non-volatile memory due to the difficulty of etching the memory cell stacks. In some embodiments, a hard mask stack is used for the structuring process. The hard mask stack can include dielectric hard mask layers formed from dielectric materials such as silicon nitride or silicon oxynitride, and one or more metal hard mask layers formed from metal or metal alloys such as tantalum or tantalum nitride.With reference to a cross-sectional view 100 of the . Fig. For example, a hard mask stack 202' is formed for structuring on a memory cell stack 204'. The hard mask stack 204' can have a first metal hard mask layer 1110 and a second metal hard mask layer 1114, for example, a tantalum nitride layer and a tantalum layer. After structuring an upper electrode layer 1106 of the memory cell stack 204' to form an upper electrode 118, the applicant observed a shrinkage section and a constriction section of the first metal hard mask layer 1110 and the second metal hard mask layer 1114, which are circled as 1110s and 1114s, respectively. The galvanic effect on neighboring metals contributes to this problem. A metal is more easily oxidized when it comes into contact with another metal with a lower redox potential.The metal hard mask layers 1110 and 1114 have a more negative redox potential than the top electrode layer 1006 and are therefore oxidized and etched during the structuring of the top electrode layer 1006. For example, the applicant observed that the lateral width of the first metal hard mask layer 1110 can shrink to approximately 35 nm and the lateral width of the second metal hard mask layer 1114 can shrink to approximately 15 nm when the lateral width of the top electrode layer 118 is approximately 50 nm. This shrinkage or constriction problem could lead to a failure of the structuring process.

[0016] Against this background, the present application, in some advanced embodiments, relates to an improved method for manufacturing a memory device using a hard mask stack and corresponding NVM memory device structures. In some embodiments, an insulating layer is formed between two metal layers of different materials during the formation of the hard mask stack for the memory device, so that the shrinkage or constriction problem discussed above can be reduced or avoided.

[0017] Fig. Figure 2 shows a cross-sectional view 200 of some embodiments of a memory cell with a hard mask stack 202. The hard mask stack has a first insulating layer 1108 arranged between an upper electrode 1006 and a first metal hard mask layer 1110. In particular, the hard mask stack 202 is formed for structuring over a memory cell stack 204, as shown in Fig. 2 according to some embodiments. Further details of the structuring processes are described below in conjunction with Fig. The memory cell stack 204 is described in Figures 11-17. It can comprise a lower electrode layer 1002, a resistive switching dielectric layer 1004, and an upper electrode layer 1006, stacked one above the other on a substrate 102. The upper electrode layer 1006 can contain or be made of a first type of metallic material (for example, tungsten). The hard mask stack 202 can comprise a first insulating layer 1108 at the bottom, a first metal hard mask layer 1110 on top of the first insulating layer 1108, and a first dielectric hard mask layer 1116 above the first metal hard mask layer 1110. The first metal hard mask layer 1110 can contain or be made of a second type of metallic material (for example, tantalum) that is different from that of the upper electrode layer 1006.The first insulating layer 1108 is positioned at the bottom of the hard mask stack and contacts the upper electrode layer 1006, separating it from the first metal hard mask layer 1110 to prevent shrinkage or constriction problems of the upper electrode layer 1006 or the first metal hard mask layer 1110. A series of etchings is then performed, which are carried out in . Fig. Figure 2 (not shown) is used to structure the hard mask stack 202, the upper electrode layer 1006, the resistance switching dielectric layer 1004, and the lower electrode layer 1002 to form a hard mask, an upper electrode, a resistance switching dielectric, and a lower electrode, respectively. The lower electrode can be electrically coupled to a metal conductor of a metallization layer 224 via a lower electrode via 110. A sidewall spacer and an etch stop layer can then be formed along the sidewalls and outlines of the structured stack.

[0018] Fig. Figure 3 shows a cross-sectional view of 300 of some alternative embodiments of a memory cell of the Fig. 2, wherein the hard mask stack 202 has several insulating layers 1108, 1110. Although two insulating layers 1108, 1110 in Fig. As shown in Figure 3, the hard mask stack 202 can have more than two stacked sets of metal hard mask layers and insulating layers. The additional sets of metal hard mask layers and insulating layers provide a greater mask thickness for structuring the memory cells. Further details of the structuring processes are given below in conjunction with the Fig. 11-17 described. As in Fig. As shown by way of example in Figure 3, in some embodiments a second insulating layer 1112 is arranged on the first metal hard mask layer 1110 and a second metal hard mask layer 1114 is arranged on the second insulating layer 1112. The second insulating layer 1112 separates the first metal hard mask layer 1110 and the second metal hard mask layer 1114 from each other, thus preventing the shrinkage or necking problem in the first metal hard mask layer 1110 or the second metal hard mask layer 1114. The second metal hard mask layer 1114 can contain a third type of metal material that differs from that of the first metal hard mask layer 1110 or the upper electrode layer 1006. For example, the second metal hard mask layer 1114 can contain or be made of tantalum nitride. Due to its selectivity properties, tantalum may be a better material than tantalum nitride for use as a hard mask material in structuring.However, the tantalum layer exhibits high stress and can lead to flaking if its thickness is too great. Therefore, a hard mask stack containing both tantalum and tantalum nitride can help achieve a desired hard mask height while maintaining selectivity and stability. Other applicable metallic materials are also within the scope of this disclosure and are to be used as metal hard mask layers 1110, 1114. The second insulating layer 1112 can contain the same or a different dielectric material as the first insulating layer 1108 (for example, silicon dioxide). The second insulating layer 1112 and the first insulating layer 1108 can also contain or be made from silicon carbide (SiC), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), or a combination thereof.Other applicable dielectric materials also fall within the scope of disclosure and are to be used as the second insulating layer 1112 or the first insulating layer 1108. In some embodiments, the second insulating layer 1112 and the first insulating layer 1108 can each have a thickness in the range of about 1 nm to about 10 nm. In some alternative embodiments, the second insulating layer 1112 and the first insulating layer 1108 can each have a thickness in the range of about 3 nm to about 10 nm. With thicknesses of the second insulating layer 1112 or the first insulating layer 1108 of less than 3 nm, a problem of non-uniformity may arise due to the properties of CVD deposition.A thickness of the second insulating layer 1112 or the first insulating layer 1108 of more than 10 nm may not be desirable, as the use of metal layers as hard mask layers provides more selectivity advantages than the use of insulating layers.

[0019] Fig. Figure 4 shows a cross-sectional view 400 of some embodiments of a memory cell with an insulating hard mask 202. The memory cell of the Fig. 4 can be an intermediate product or a final product, after the memory cell of the Fig. 2 or Fig. 3 is structured according to the hard mask stack 202. In some embodiments, a memory cell 114 has a lower electrode 112 arranged over a substrate 102. A resistive switching dielectric 116 is arranged over the lower electrode 112 and has a variable resistance. An upper electrode 118 is arranged over the resistive switching dielectric 116. During operation of the memory cell 114, voltages are applied between the upper electrode 118 and the lower electrode 112 to read, store, or erase the memory cell 114 by forming or breaking one or more conductive filaments of the resistive switching dielectric 116. Thus, the memory cell 114 can have a variable resistance in a comparatively low-resistance or high-resistance state to represent, for example, a low or high bit state.

[0020] A hard-mask insulator 120 is arranged directly on the upper electrode 118 and can have side walls that are flush with or coplanar to the upper electrode 118. The hard-mask insulator 120 can form a partial remnant of the first insulating layer 1108, which is located in Fig. 2 or Fig. Figure 3 shows the process used in memory cell structuring. In some embodiments, a sidewall spacer 122 is arranged on an upper surface of the lower electrode 112 and extends upward along the sidewalls of the resistive switching dielectric 116 and the upper electrode 118, and can extend to a lower portion of the hard mask insulator 120. The sidewall spacer 122 can also extend to the entire sidewall surface of the hard mask insulator 120. An etch stop layer 126 is arranged over the substrate 102 and can conform to the lower electrode 112, the sidewall spacer 122, and extend over the hard mask insulator 120. The etch stop layer 126 can directly contact and cover an upper surface of the insulating layer. The etch stop layer 126 and the sidewall spacer 122 can be made of different materials or the same material with different densities.The sidewall spacer 122 and the etch stop layer 126 can also contain one or more layers with a dielectric composition, such as silicon oxide, silicon nitride, silicon carbide, or the like. The sidewall spacer 122 can be used during the fabrication of the memory cell 114 to define a base area for the lower electrode 112. The etch stop layer 126 protects the upper electrode 118 during the placement of the upper electrode via 132.

[0021] According to some embodiments, the memory cell 114 can be inserted into a backend-of-line metallization stack (BEOL metallization stack) comprising a lower interconnection structure 140 and an upper interconnection structure 142 arranged above the substrate 102. The lower interconnection structure 140 has a lower metallization line 106 located within a lower dielectric intermediate layer 104. The upper interconnection structure 142 has an upper metallization line 134 located within an upper dielectric intermediate layer 138. The lower dielectric intermediate layer 104 and the upper dielectric intermediate layer 138 can, for example, consist of an oxide, a low-k dielectric (i.e.,a dielectric with a smaller dielectric constant k than silicon dioxide) or an extremely low k dielectric (a dielectric with a dielectric constant k less than about 2), and the lower metallization lines 106 and the upper metallization lines 134 can, for example, be a metal such as copper.

[0022] The lower electrode 112 of the memory cell 114 can be a conductive material, such as titanium, tantalum, titanium nitride, tantalum nitride, tungsten, ruthenium, molybdenum, cobalt, or a combination thereof. An example thickness for the lower electrode 112 can be in the range of about 10 nm to 100 nm, or preferably 10 nm to about 20 nm. This exemplary thickness, along with other example dimensions specified below, can be used for a particular fabrication node, and proportional scaling of these dimensions for other nodes is conceivable. In some embodiments, the lower electrode 112 is coupled to the lower metallization line 106 of the lower interconnect structure 140 via a lower electrode via 110, which is arranged between the lower electrode 112 and the lower metallization line 106. The lower electrode via 110 can, for example, contain titanium nitride.An exemplary thickness of the lower electrode via 110 can be in the range of approximately 40 nm to approximately 50 nm. In some embodiments, a lower dielectric layer 108 is arranged around the lower electrode via 110. The lower dielectric layer 108 can, for example, comprise silicon carbide, silicon nitride, silicon oxide, or one or more layers of dielectric composite films. An upper dielectric layer 136 is arranged above the lower dielectric layer 108. The upper dielectric layer 136 can contain silicon oxide. The upper dielectric layer 136 can have a lower surface that is in direct contact with an upper surface of the etch stop layer 126. The upper dielectric layer 136 can have an upper surface that is in direct contact with a lower surface of the upper dielectric intermediate layer 138.

[0023] In some embodiments, the memory cell 114 is a magnetoresistive random-access memory cell (MRAM cell), and the resistive switching dielectric 116 may have a magnetic tunnel junction (MTJ) structure. The MTJ structure may have a lower ferromagnetic layer and an upper ferromagnetic layer separated by a tunnel barrier layer. In some other embodiments, the memory cell 114 is a resistive random-access memory cell (RRAM cell), and the resistive switching dielectric 116 may comprise an RRAM dielectric layer. The resistive switching dielectric 116 may be a high-k layer (i.e., a layer with a dielectric constant k greater than 3.9), for example, tantalum oxide, tantalum hafnium oxide, tantalum aluminum oxide, or another material containing tantalum, oxygen, and one or more other elements. The resistive switching dielectric 116 may also include other composite layers.For example, the resistance switching dielectric 116 can have a bottom-arranged seed layer and / or a top-arranged cover layer. An exemplary thickness of the resistance switching dielectric 116 can be in the range of approximately 20 nm to approximately 50 nm.

[0024] The upper electrode 118 is arranged above the resistive switching dielectric 116. The upper electrode 118 may contain tungsten on its upper surface to ensure good contact. The upper electrode 118 or the underlying top layer of the MTJ structure may also have one or more other metal layers or metal composite layers containing, for example, titanium, titanium nitride, tantalum, tantalum nitride, or the like. An exemplary thickness of the upper electrode 118 may be in the range of approximately 30 nm to approximately 40 nm. In some embodiments, the upper electrode 118 is electrically coupled to the upper metallization line 134 of the upper interconnect structure 142 by an upper electrode via 132 located between the upper electrode 118 and the upper metallization line 134. The upper electrode via 132 may, for example, be a conductive material such as copper, aluminum, cobalt, or tungsten.A barrier lining 131 can be arranged beneath the upper electrode via 132 and act as a diffusion barrier to prevent material from diffusing between the upper electrode via 132 and the upper electrode 118. The barrier lining 131 can, for example, contain tantalum nitride. An exemplary thickness of the barrier lining 131 can be in the range of approximately 5 nm to approximately 10 nm.

[0025] Fig. Figure 5 shows a cross-sectional view 500 of a memory cell with an insulating hard mask according to some alternative embodiments. Compared to Fig. 4. The sidewall spacer 122 is arranged on an upper surface of a lower dielectric layer 108 and extends upwards along the sidewalls of the lower electrode 112, the resistive switching dielectric 116, and the upper electrode 118, and can extend to a lower portion or the entire sidewall surface of the hard mask insulator 120. The etch stop layer 126 is arranged on the upper surface of the lower dielectric layer 108, conformally lines the sidewall spacer 122, and extends over the hard mask insulator 120. The etch stop layer 126 can directly contact and cover an upper surface of the hard mask insulator 120. The upper electrode via 132 can have a lower landing on a recessed upper surface of the upper electrode 118.The etch stop layer 126 and the hard mask insulator 120 can both contact a lower side wall of the barrier lining 131 or the upper electrode via 132 and have inner side wall surfaces that are substantially aligned or coplanar.

[0026] As mentioned above, memory cell 114 can be any applicable non-volatile memory cell, such as a magnetoresistive random access memory cell (MRAM cell) and a resistive random access memory cell (RRAM cell). Fig. Figure 6 shows a cross-sectional view 600 of another example of a memory cell with an insulating hard mask according to some to Fig. 4 and Fig. 5 alternative embodiments. As in Fig. As shown in Figure 6, sometimes also referred to as SOT-MRAM (Spin-Orbit Torque-MRAM), the switching of the resistive switching dielectric 116 is achieved by injecting an in-plane current into an adjacent SOT layer 112'. This provides a three-terminal MTJ that isolates a read path 602 from a write path 604, thereby improving the lifetime and read stability of the device. Furthermore, due to the SOT spin transfer geometry, the incubation time is negligible, enabling a faster and more reliable switching operation.

[0027] Fig. Figure 7 shows a cross-sectional view of an integrated circuit 700 including the memory cell 114 according to some further embodiments. The memory cell 114 can have a similar structure to any of the ones described in Figure 7. Fig. Memory cells 114 shown and described above in Figures 4-6. Fig. As shown in Figure 7, the memory cell 114 can be arranged above the substrate 102. The substrate 102 can be, for example, a bulk substrate (such as a silicon bulk substrate) or a silicon-on-insulator (SOI) substrate. One or more STI regions 244 or oxide-filled trenches are arranged in the substrate 102. A pair of word conduction transistors 206, 208 is arranged between the STI regions 244. The word conduction transistors 206, 208 are parallel to each other and have word conduction gates 210, which are separated from the substrate 102 by word conduction dielectric layers 212, and source / drain regions 214, 216. The source / drain regions 214 and 216 are embedded in the surface of substrate 102 between the word conduction gates 210 and the STI regions 244. The word conduction gates 210 can be, for example, doped polysilicon or a metal such as titanium nitride or tantalum nitride.The word-line dielectric layers 212 can, for example, be an oxide such as silicon dioxide. A bottom ILD layer 238 is arranged over the word-line transistors 206, 208. The bottom ILD layer 238 can, for example, be an oxide.

[0028] A back-end-of-line metallization stack (BEOL metallization stack) 218 ​​is arranged over the word-line transistors 206, 208. The BEOL metallization stack 218 has several metallization layers 222, 224, 226, each arranged within the respective dielectric intermediate layer 220, 228, 230. The metallization layers 222, 224, 226 can be, for example, a metal such as copper or aluminum. The dielectric intermediate layers 220, 228, 230 can be, for example, a low-k dielectric such as porous undoped silicate glass, or an oxide such as silicon dioxide. Etch-stop layers 126, 242 can be arranged to separate the dielectric intermediate layers 220, 228, 230 from one another. The metallization layers 222, 224, 226 have a source line 232 which is coupled to a source / drain region 214 which is shared by the word line transistors 206, 208.Furthermore, the metallization layers 222, 224, and 226 have a bit line connected to the memory cell 114 and, via several metallization lines, such as metallization lines 106 and 234, and several vias, such as vias 132, 110, and 240, to a source / drain region 216 of the word line transistor 206 or the word line transistor 208. A contact 236 extends from metallization line 234 through the bottommost ILD layer 238 to reach the source / drain region 216. The vias 132, 110, and 240 and the contact 236 can be made of a metal such as copper, gold, or tungsten.

[0029] The memory cell 114 is inserted between an upper metallization line 134 and a lower metallization line 106. An upper dielectric layer 136 is arranged above the memory cell 114 between the dielectric intermediate layers 228, 230. The upper dielectric layer 136 can be an oxide. Although the memory cell 114 is in Fig. Since the memory cell 114 is shown as being inserted between the upper metallization layer 226 and the lower metallization layer 224, it is conceivable that the memory cell 114 can be inserted between any two metallization layers of the BEOL metallization stack 218.

[0030] Similar to the above with reference to Fig. As described in Figures 4-6, the storage cell 114 has a lower electrode 112 that is connected to or seamlessly contacts the lower electrode via 110. The resistive switching dielectric 116 is arranged above the lower electrode 112. The upper electrode 118 is arranged above the resistive switching dielectric 116. The hard mask insulator 120 is arranged on the upper electrode 118, and its upper surface is covered by the etch stop layer 126. The sidewall spacer 122 can be arranged on the upper surface of the lower electrode 112 and extends upward along the sidewalls of the resistive switching dielectric 116 and the upper electrode 118, as shown in Figure 4-6. Fig. 4 shown. Alternatively, the side wall spacer 122 can also be arranged on the upper surface of the lower dielectric layer 108 or other dielectric materials and extends upwards along the side walls of the lower electrode 112, the resistance switching dielectric 116 and the upper electrode 118, as shown in Fig. Figure 5 shows the etch stop layer 126 being arranged on the upper surface of the lower dielectric layer 108 or other dielectric materials and extending upwards along the sidewalls of the sidewall spacer 122. The upper electrode via 132 connects the upper metallization line 134 and the upper electrode 118. The upper electrode via 132 may have a lower surface that rests on a recessed upper surface of the upper electrode 118. The hard mask insulator 120 may be a partial remnant of the first insulating layer 1108, which is located in Fig. 2 or Fig. Figure 3 shows the process of structuring the memory cell. The first insulating layer 1108 is located at the bottom of the hard mask stack and contacts the upper electrode layer 1006, separating it from the first metal hard mask layer 1110, thus preventing the shrinkage or constriction problem in the upper electrode layer 1006 or the first metal hard mask layer 1110 (see Figure 3). Fig. 2 or Fig. 3).

[0031] Fig. Figures 8-19 illustrate some embodiments of a method for manufacturing an integrated circuit in cross-sectional views.

[0032] As shown in the cross-sectional view 800 of the Fig. As shown in Figure 8, a lower via opening 802 is formed within a lower dielectric layer 108, which lies above a lower interconnect structure 140. The lower interconnect structure 140 has a lower metallization line 106, which is laterally surrounded by a lower dielectric intermediate layer 104. The lower dielectric intermediate layer 104 can, for example, be a low-k dielectric, and the lower metallization line 106 can, for example, be a metal such as copper. The lower dielectric layer 108 is formed above the lower interconnect structure 140, with the lower via opening 802 exposing the lower metallization line 106. The lower dielectric layer 108 can, for example, have one or more layers of dielectrics such as silicon dioxide, silicon carbide, and / or silicon nitride.The process for forming the lower via hole 802 can include depositing the lower dielectric layer 108 over the lower interconnect structure 140, followed by a photolithography process. A photoresist layer can be formed over the lower dielectric layer 108, exposing areas of the lower dielectric layer 108 that correspond to the lower via hole 802 to be formed. Then, one or more etchants that are selective for the lower dielectric layer 108 can be applied according to the photoresist layer. After the application of the one or more etchants, the photoresist layer can be removed. Then, a lower electrode via 110 is formed over the lower dielectric layer 108, filling the lower via hole 802.The lower electrode via 110 can, for example, be formed from one or more layers of conductive materials such as polysilicon, titanium nitride, tantalum nitride, platinum, gold, iridium, ruthenium, tungsten, or the like. For example, the lower electrode via 110 can be a titanium nitride layer formed by an atomic layer deposition (ALD) process followed by a planarization process.

[0033] As shown in the cross-sectional view 900 of the Fig. As shown in Figure 9, a memory cell stack 204 of a memory cell is deposited over the lower dielectric layer 108 by a variety of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.). In some embodiments, a lower electrode layer 1002 is formed over the lower electrode via 110 and the lower dielectric layer 108. The lower electrode layer 1002 can contain a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or the like) and / or a metal (e.g., titanium (Ti), tantalum (Ta), or the like). In some embodiments, the lower electrode layer 1002 can be of the same material as the lower electrode via and can even be formed together with the lower electrode via 110 in a single deposition process.Subsequently, a planarization process can be performed to form a planar upper surface for the lower electrode layer 1002. Then, a resistive switching dielectric layer 1004 is formed over the lower electrode layer 1002. In some embodiments, the resistive switching dielectric layer 1004 may have a magnetic tunnel junction (MTJ) structure with a pinned magnetic layer and a free magnetic layer vertically separated by a dielectric barrier layer. In other embodiments, the resistive switching dielectric layer 1004 may have a dielectric RRAM data storage layer. In some embodiments, the resistive switching dielectric layer 1004 may contain a metal oxide composite material such as hafnium aluminum oxide (HfAlOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), nickel oxide (NiOx), tantalum oxide (TaOx), or titanium oxide (TiOx).An upper electrode layer 1006 is formed over the resistive switching dielectric layer 1004. The uppermost electrode layer 1006 may comprise one or more conductive layers. In some embodiments, the upper electrode layer 1006 may contain titanium nitride (TiN) or tantalum nitride (TaN), a metal (for example, titanium (Ti) or tantalum (Ta), copper), or the like. In some embodiments, the upper electrode layer 1006 may be formed of tungsten or at least contain tungsten on its upper surface to ensure good contact. In some embodiments, the upper electrode layer 1006 may have a thickness in the range of about 20 nm to about 70 nm.

[0034] As shown in the cross-sectional view 1000 of the Fig. 10 and the cross-sectional view 1100 of the Fig. As shown in Figure 11, a hard mask stack 202 is formed over the memory cell stack 204. The hard mask stack 202 can have a first insulating layer 1108, formed at the bottom and contacting the upper electrode layer 1006, and a first metal hard mask layer 1110, formed on top of the first insulating layer 1108. The first metal hard mask layer 1110 can contain or be formed from a second type of metal material (for example, tantalum) that is different from that of the upper electrode layer 1006 (for example, tungsten). The first insulating layer 1108 is located at the bottom of the hard mask stack and contacts the upper electrode layer 1006, separating it from the first metal hard mask layer 1110, thus preventing shrinkage or constriction problems in the first metal hard mask layer 1110 (or the upper electrode layer 1006).In some further embodiments, the hard mask stack 202 can comprise more than one set of stacked metal hard mask layers and insulating layers. The additional sets of metal hard mask layers and insulating layers provide a greater mask thickness for structuring the memory cell. For example, a second insulating layer 1112 can be formed on top of the first metal hard mask layer 1110, and a second metal hard mask layer 1114 can be formed on top of the second insulating layer 1112. The second insulating layer 1112 separates the first metal hard mask layer 1110 and the second metal hard mask layer 1114 from each other, thus preventing the shrinkage or constriction problem in either the first metal hard mask layer 1110 or the second metal hard mask layer 1114.The second metal hard mask layer 1114 can contain a third type of metal material, different from that of the first metal hard mask layer 1110 or the upper electrode layer 1006 (for example, tantalum nitride). The second insulating layer 1112 can contain the same or a different dielectric material than that of the first insulating layer 1108 (for example, silicon dioxide). The first insulating layer 1108 and the second insulating layer 1110 can be formed by deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other application methods. In some embodiments, the first insulating layer 1108 and / or the second insulating layer 1112 can each have a thickness in the range of about 3 nm to about 10 nm.The first insulating layer 1108 and / or the second insulating layer 1112 may each contain or be made of silicon dioxide, silicon nitride, silicon carbide, or a combination thereof. Other dielectric materials for the production of the first insulating layer 1108 and / or the second insulating layer 1112 are within the scope of disclosure.

[0035] As shown in the cross-sectional view 1100 of the Fig. As shown in Figure 11, a first dielectric hard mask layer 1116 can be formed over the sets of metal hard mask layers and insulating layers. In some further embodiments, the hard mask stack 202 can have more than one dielectric hard mask layer stacked on top of the other to achieve a greater mask thickness for structuring the memory cell. The dielectric hard mask layers can be separated by an amorphous carbon film and / or a diamond-like carbon film. For example, an amorphous carbon film 1118 can be formed on the first dielectric hard mask layer 1116 and a second dielectric hard mask layer 1120 can be formed on the amorphous carbon film 1118. The first dielectric hard mask layer 1116 and the second dielectric hard mask layer 1120 can contain the same or different dielectric materials, such as silicon oxynitride (SiON) or silicon carbide.

[0036] As shown in the cross-sectional view 1100 of the Fig. As further shown in Figure 11, a structuring layer 1202 is formed over the hard mask stack 202. The structuring layer 1202 can comprise a lower antireflective layer (BARC layer) 1204 and a photoresist layer 1206, which is spin-applied (spread-on coating) to the BARC layer 1204 and structured, for example by means of a double structuring technique.

[0037] As shown in the cross-sectional view 1200 of the Fig. As shown in Figure 12, the second dielectric hard mask layer 1120 and the amorphous carbon film 1118 can be patterned by a first etching series according to the patterning layer 1202. In emerging node fabrication processes, the thickness of the photoresist layer 1206 is quite limited and can only pattern an underlying layer of limited thickness. The patterned amorphous carbon film 1118 is used as a transferred mask layer to pattern the first dielectric hard mask layer 1116. The amorphous carbon film 1118 can have a thickness approximately 1.2 to 2.5 times greater than that of the photoresist layer 1206. The first dielectric hard mask layer 1116 can have a thickness that is 2 to 4 times greater than that of the second dielectric hard mask layer 1120.The structured second dielectric hard mask layer 1120 can be removed after structuring the amorphous carbon film 1118. The structured amorphous carbon film 1118 can be removed after structuring the first dielectric hard mask layer 1116.

[0038] As shown in the cross-sectional view 1300 of the Fig. As illustrated in Figure 13, the sets of metal hard mask layers and insulating layers (e.g., 1114, 1112, 1110, 1108) are structured by a second etching series according to the structured first dielectric hard mask layer 1116. The first insulating layer 1108 can be structured according to the metal hard mask layers (e.g., 1114, 1110) to form a hard mask insulator 120. The first dielectric hard mask layer 1116 can be partially consumed during the structuring process. In some embodiments, the structuring process can include a dry etching process that may have an etchant chemistry containing CF4, CH2F2, Cl2, BCl3, and / or other chemicals. The second metal hard mask layer 1114 may contain tantalum nitride and can be structured by an etchant containing SF6, CF4, CH2F2, CHF3, Cl2, BCl3, and / or other chemicals.The first metal hard mask layer 1110 may contain tantalum and may be structured by an etching agent containing SF6, CF4, CH2F2, CHF3, Cl2, BCl3 and / or other chemicals.

[0039] As shown in the cross-sectional view 1400 of the Fig. As shown in Figure 14, the upper electrode layer 1006 is structured to form an upper electrode 118 according to the structured hard mask stack 202. The hard mask stack 202 comprises the structured first metal hard mask layer 1110 and the hard mask insulator 120 and may further include some remaining mask layers above the first metal hard mask layer 1110. The upper electrode layer 1006 may contain tungsten and be structured by an etching agent containing SF6, CF4, CHF3, and / or other chemicals.

[0040] As shown in the cross-sectional view 1500 of the Fig. As shown in Figure 15, the resistive switching dielectric layer 1004 (in Fig. 14) structured to form a resistive switching dielectric 116 according to the hard mask stack 202 and the upper electrode 118. During the structuring process, the hard mask stack 202 may be partially removed or reduced. The lower electrode layer 1002 may be exposed. In some embodiments, the side walls of the resistive switching dielectric 116 and the upper electrode 118 may be inclined and flush (for example, coplanar). In some embodiments, the structuring process may include dry etching or ion beam etching, or a combined process, which may have an etchant chemistry containing CF4, CH2F2, Cl2, BCl3, CO / NH3, CH3OH, CH4, H2, Ar, Kr, Xe, and / or other chemicals.

[0041] As shown in the cross-sectional view 1600 of the Fig. As shown in Figure 16, a sidewall spacer 122 can be formed along the sidewall surfaces of the resistance switching dielectric 116, the upper electrode 118, and the hard mask insulator 120. In some embodiments, the sidewall spacer 122 can be formed by forming a dielectric spacer layer along an upper surface of the lower electrode layer 1002, extending along the sidewall surfaces of the resistance switching dielectric 116, the upper electrode 118, the hard mask insulator 120, and the hard mask stack 202, and covering an upper surface of the hard mask stack 202. The dielectric spacer layer can comprise silicon nitride, tetraethyl orthosilicate (TEOS), silicon-rich oxide (SRO), or a similar dielectric composite film.In some embodiments, the dielectric spacer layer can be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.). Anisotropic etching (e.g., vertical etching) is then performed to remove lateral extensions of the dielectric spacer layer, resulting in the sidewall spacer 122 along the sidewall surfaces of the resistive switching dielectric 116 and the upper electrode 118. As a result of removing the lateral extensions of the dielectric spacer layer, the lower electrode layer 1002 can be exposed. The hard mask stack 202 and an upper portion of the hard mask insulator 120 can be removed during the etching process.

[0042] As shown in the cross-sectional view 1700 of the Fig. As shown in Figure 17, an etching process is performed to structure the lower electrode layer 1002 and form a lower electrode 112 according to the sidewall spacer 122. The etching may involve a dry etching process, such as a plasma etching process, which may include an etchant chemistry with CF4, CH2F2, Cl2, BCl3, and / or other chemicals. As a result of the etching process, the lower electrode 112 may have sidewalls that are flush with those of the sidewall spacer 122, and a lower dielectric layer 108 may be exposed.

[0043] As shown in the cross-sectional view 1800 of the Fig. As shown in Figure 18, an etch stop layer 126 can be formed to conformally line the workpiece. The etch stop layer 126 can contain silicon nitride, tetraethyl orthosilicate (TEOS), silicon-rich oxide (SRO), or a similar dielectric composite film. In some embodiments, the etch stop layer 126 can be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.). The etch stop layer 126 is formed to provide protection of the memory cell from the top electrode via opening and the landing process, as described below. For example, the etch stop layer 126 can have a thickness in the range of about 20 nm to about 25 nm.

[0044] As shown in the cross-sectional view 1800 of the Fig. As further shown in Figure 18, an upper dielectric layer 136 is formed above and around the memory cell. The upper dielectric layer 136 can, for example, be a low-k dielectric or an extremely low-k dielectric. In some embodiments, the process for forming the upper dielectric layer 136 includes depositing a dielectric intermediate layer and performing chemical-mechanical polishing (CMP) in the dielectric intermediate layer to planarize the upper surface of the dielectric intermediate layer.

[0045] As shown in the cross-sectional view from 1900. Fig. As shown in Figure 19, an upper electrode via opening 1902 is formed through the upper dielectric layer 136 and the hard mask insulator 120, extending to the upper electrode 118. A conductive layer is then formed, filling the upper electrode via opening 1902 to create an upper electrode via 132. The conductive layer can be, for example, a metal such as copper or tungsten. The process for forming the conductive layer can include the deposition of a conductive intermediate layer that fills the upper electrode via opening 1902 and extends beyond the upper dielectric layer 136 to form the upper electrode via 132 and an upper metallization lead 134. Photolithography can then be used to pattern the conductive layer.In some embodiments, the upper electrode via 132 and the upper metallization lead 134 can be formed by a single damascus process, a double damascus process in which a trench or via is formed first, or other applicable metal filling processes. As a result of the filling, the upper electrode via 132 can have a lower surface that contacts a recessed upper surface of the upper electrode 118.

[0046] Fig. Figure 20 shows some embodiments of a flowchart of a Method 2000 for forming a storage device. Although the Method 2000 refers to Fig. As described in 8-19, it is to be understood that the procedure 2000 does not apply to the one described in Fig. the structures shown in 8-19 are limited, but are independent and separate from the structures shown in Fig. The structures shown in 8-19 can be executed. It should also be taken into account that the structures shown in Fig. The structures shown in Figures 8-19 are not limited to Procedure 2000, but can be implemented as independent structures separate from Procedure 2000. Although the procedures described herein (for example, Procedure 2000) are presented and described below as a series of operations or events, it should be noted that the sequence of these operations or events presented is not to be interpreted restrictively. For example, some operations may need to be performed in a different order and / or simultaneously with other operations or events than / as shown and / or described herein. Furthermore, it may not be necessary to implement one or more aspects or embodiments of the description contained herein, as illustrated herein.Furthermore, one or more of the processes shown here can be carried out in one or more separate processes and / or phases.

[0047] In process 2002, a memory cell stack is formed over a lower interconnect structure of a substrate. The memory cell stack can include at least a lower electrode layer, a resistive switching dielectric layer, and an upper electrode layer over the substrate. The lower interconnect structure can include a lower metallization conductor laterally surrounded by a lower dielectric intermediate layer. A lower via is formed through the lower dielectric layer to electrically couple the lower metallization conductor to the lower electrode layer. The lower electrode via can be a titanium nitride layer formed by an atomic layer deposition (ALD) process followed by a planarization process.The memory cell stack can be deposited over the lower dielectric layer by a variety of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.). In some embodiments, the lower electrode layer can contain a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or the like) and / or a metal (e.g., titanium (Ti), tantalum (Ta), or the like). In some embodiments, the resistive switching dielectric layer can have a magnetic tunnel junction (MTJ) structure with a pinned magnetic layer and a free magnetic layer vertically separated by a dielectric barrier layer. In other embodiments, the resistive switching dielectric layer can include a dielectric RRAM data storage layer.In some embodiments, the upper electrode layer may comprise titanium nitride (TiN) or tantalum nitride (TaN), a metal (for example, titanium (Ti) or tantalum (Ta), copper, etc.). Fig. Figures 8-9 show some embodiments of the cross-sectional views 800 and 900, corresponding to process 2002.

[0048] In process 2004, a hard mask stack is formed over the memory cell stack. The hard mask stack may include a first insulating layer, formed at the bottom and contacting the upper electrode layer, and a first metal hard mask layer, formed on top of the first insulating layer. The first metal hard mask layer may contain a second type of metal material (for example, tantalum) different from that of the upper electrode layer (for example, tungsten). The first insulating layer separates the upper electrode layer from the first metal hard mask layer, thus preventing the shrinkage or constriction problem in the first metal hard mask layer (or the upper electrode layer). In some further embodiments, the hard mask stack may be formed from more than one set of stacked metal hard mask layers and insulating layers.The additional sets of metal hard mask layers and insulating layers provide a greater mask thickness for structuring the memory cell. A first dielectric hard mask layer can be formed over the sets of metal hard mask and insulating layer. In some further embodiments, the hard mask stack can also include more than one dielectric hard mask layer stacked on top of each other to achieve a greater mask thickness for structuring the memory cell. The dielectric hard mask layers can be separated by an amorphous carbon film or a diamond-like carbon film. Fig. Figures 10-11 show some embodiments of the cross-sectional views 1000 and 1100 according to process 2004.

[0049] In process 2006, the hard mask stack is structured. The dielectric hard mask layers can be structured by a first etching series according to a structuring layer. The metal hard mask layers and insulating layers (for example, 1114, 1112, 1110, 1108) are structured by a second etching series according to the structured dielectric hard mask layer. The first insulating layer can be etched to form a hard mask insulator on the upper electrode layer. Fig. Figures 12-13 show some embodiments of the cross-sectional views 1200 and 1300 according to the process 2006.

[0050] In process 2008, the memory cell stack is structured. In some embodiments, the top electrode layer is structured according to the structured hard mask stack to form a top electrode. The resistance switching dielectric layer can be structured according to the top electrode to form a resistance switching dielectric. During the structuring process, the hard mask stack can be partially removed or reduced. In some embodiments, the side walls of the resistance switching dielectric and the top electrode can be inclined and arranged flush (for example, coplanarly). Fig. Figures 14-15 show some embodiments of the cross-sectional views 1400 and 1500 according to the 2008 process.

[0051] In process 2010, in some embodiments, a sidewall spacer is formed on the lower electrode layer and along the sidewalls of the resistive switching dielectric layer and the upper electrode. The sidewall spacer can be formed by depositing a dielectric spacer layer by a vapor deposition technique (e.g., chemical vapor deposition, etc.) along an upper surface of the lower electrode layer, extending along the sidewall surfaces of the resistive switching dielectric, the upper electrode, and the hard mask, and covering an upper surface of the hard mask. Then, anisotropic etching (e.g., vertical etching) is performed to create a structure and form a lower electrode corresponding to the sidewall spacer and the hard mask insulator. Fig. Figure 16 shows some embodiments of a cross-sectional view 1600 according to process 2010.

[0052] In process 2012, in some embodiments, the lower electrode layer is structured according to the sidewall spacer to form a lower electrode. In some embodiments, the sidewalls of the lower electrode and the sidewall spacer can be inclined and arranged flush (for example, coplanarly). Fig. Figure 17 shows some embodiments of a cross-sectional view 1700 according to process 2012.

[0053] In process 2014, an etch stop layer can be formed using a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.) to protect the memory cell from the top electrode via opening and the landing process. A dielectric layer is formed over and around the memory cell by depositing a dielectric intermediate and performing chemical-mechanical polishing (CMP) on the dielectric intermediate to planarize its top surface. Fig. Figure 18 shows some embodiments of a cross-sectional view 1800 according to process 2014.

[0054] In process 2016, an upper electrode via is formed through the dielectric layer, the etch stop layer, and the hard mask insulator, extending to the upper electrode. An upper metallization line is formed on the upper electrode via, and this line may extend beyond the dielectric layer. The upper electrode via may have a bottom surface that contacts a recessed top surface of the upper electrode. Fig. Figure 19 illustrates some embodiments of a cross-sectional view 1900 according to the process 2016.

[0055] It is conceivable that while exemplary structures are referenced throughout this document when discussing aspects of the principles described herein, these principles are not intended to be limited by the corresponding structures presented. Rather, the methods (and structures) are to be considered independent of one another and can stand alone and be practiced independently of the aspects depicted in the drawings. Furthermore, the layers described herein can be formed in any suitable manner, for example, by spin coating, sputtering, growth techniques, and / or deposition techniques, etc.

[0056] As can be seen from the foregoing, the present disclosure provides, in some embodiments, a method for fabricating an integrated circuit (IC). In the method, a memory cell stack is formed on a substrate comprising a lower electrode layer, a resistive switching dielectric layer above the lower electrode layer, and an upper electrode layer above the resistive switching dielectric layer. A first insulating layer is formed over the upper electrode layer. A first metal hard mask layer is formed over the first insulating layer. Then, a series of etching operations is performed to pattern the first metal hard mask layer, the first insulating layer, the upper electrode layer, and the resistive switching dielectric layer to form a first metallic hard mask, a hard mask insulator, an upper electrode, and a resistive switching dielectric.Before carrying out the etching series, a second insulating layer is formed over the first metal hard mask layer and a second metal hard mask layer is formed over the second insulating layer.

[0057] In another embodiment, the present disclosure relates to a method for manufacturing an integrated circuit (IC). In the method, a memory cell stack is formed on a substrate comprising a lower electrode layer, a resistive switching dielectric layer above the lower electrode layer, and an upper electrode layer above the resistive switching dielectric layer. A hard mask stack is formed on top of the memory cell stack. The hard mask stack comprises a first insulating layer at the bottom, which contacts the upper electrode layer, and a first metal hard mask layer containing a metal material different from that of the upper electrode layer. The hard mask stack has a second insulating layer on top of the first metal hard mask layer, separating the first metal hard mask layer from a second metal hard mask layer on top of the second insulating layer.To structure the hard mask stack, the upper electrode layer, the resistance switching dielectric layer and the lower electrode layer, a series of etching processes are carried out to form a hard mask insulator, an upper electrode, a resistance switching dielectric and a lower electrode.

[0058] In one example, a storage device has a lower electrode positioned over a substrate and a resistance switching dielectric positioned over the lower electrode, exhibiting variable resistance. An upper electrode is positioned over the resistance switching dielectric. A hard-mask insulator is placed directly on the upper electrode. The upper electrode extends through the hard-mask insulator and reaches the upper electrode. The hard-mask insulator directly contacts the upper electrode and contains an insulating material.

Claims

[1] Method for manufacturing a memory cell, comprising: Forming a memory cell stack (204) over a substrate (102), wherein the memory cell stack (204) has a lower electrode layer (1002), a resistive switching dielectric layer (1004) over the lower electrode layer (1002) and an upper electrode layer (1006) over the resistive switching dielectric layer (1004); Forming a first insulating layer (1108) over the upper electrode layer (1006); Forming a first metal hard mask layer (1110) over the first insulating layer (1108); and Performing an etching series to structure the first metal hard mask layer (1110), the first insulating layer (1108), the upper electrode layer (1006) and the resistance switching dielectric layer (1004) to form a first metal hard mask (1110), a hard mask insulator (120), an upper electrode (118) and a resistance switching dielectric (116); Furthermore, comprehensively, before carrying out the etching series: Forming a second insulating layer (1112) over the first metal hard mask layer (1110); and Forming a second metal hard mask layer (1114) over the second insulating layer (1112). [2] Method according to claim 1, wherein the upper electrode layer (1006) is made of tungsten and the first metal hard mask layer (1110) is made of tantalum nitride. [3] Method according to claim 1 or 2, wherein the first insulating layer (1108) is formed of silicon dioxide, silicon nitride, silicon carbide or a combination thereof. [4] Method according to one of the preceding claims, wherein the second insulating layer (1112) is formed from silicon dioxide and the second metal hard mask layer (1114) is formed from tantalum. [5] The method of claim 4, further comprising, prior to carrying out the etching series: Forming a first dielectric hard mask layer (1116) directly on the second metal hard mask layer (1114). [6] The method of claim 5, further comprising, prior to carrying out the etching series: Forming an amorphous carbon film (1118) over the first dielectric hard mask layer (1116) and forming a second dielectric hard mask layer (1120) over the amorphous carbon film (1118). [7] Method according to claim 6, wherein the second dielectric hard mask layer (1120) and the amorphous carbon film (1118) are removed after structuring the upper electrode layer (1006). [8] Method according to claim 7, wherein the second metal hard mask layer (1114) and the second insulating layer (1112) are removed after structuring the resistance switching dielectric layer (1004). [9] Method according to any of the preceding claims, wherein the first insulating layer (1108) has a thickness in the range of about 3 nm to about 10 nm. [10] Method according to any one of the preceding claims, further comprising: Forming a dielectric spacer layer (122) over the lower electrode layer (1002), extending along the resistance switching dielectric (116) and the upper electrode (118), and further extending over the hard mask insulator (120). [11] The method of claim 10, further comprising: Performing a first etching of the dielectric spacer layer to form a sidewall spacer (122) along the resistive switching dielectric (116), the top electrode (118) and the hard mask insulator (120); and Performing a second etching to structure the lower electrode layer (1002) according to the hard mask insulator (120) and the side wall spacer (122) to form a lower electrode (112), wherein the lower electrode (112) has a side wall that is flush with that of the side wall spacer (122). [12] The method of claim 11, further comprising: Forming an etch stop layer (126) over the substrate (102) extending along the lower electrode (112), the side wall spacer (122) and further over the hard mask insulator (120); Forming an upper dielectric layer (136) above and around the etch stop layer (126); and Forming an upper electrode via (132) extending through the upper dielectric layer (136) and the hard mask insulator (120) to reach the upper electrode (118). [13] Method according to any one of claims 10 to 12, wherein the dielectric spacer layer (122) is formed directly on the lower electrode layer (1002). [14] Method for manufacturing a memory cell, comprising: Forming a memory cell stack (204) over a substrate (102), wherein the memory cell stack (204) has a lower electrode layer (1002), a resistive switching dielectric layer (1004) over the lower electrode layer (1002) and an upper electrode layer (1006) over the resistive switching dielectric layer (1004); Forming a hard mask stack (202) over the memory cell stack (204), wherein the hard mask stack (202) has at its bottom a first insulating layer (1108) which contacts the upper electrode layer (1006) and a first metal hard mask layer (1110) formed of a metal material different from that of the upper electrode layer (1006), wherein the hard mask stack (202) has a second insulating layer (1112) on the first metal hard mask layer (1110) which separates the first metal hard mask layer (1110) from a second metal hard mask layer (1114) on the second insulating layer (1112); and Performing a series of etching operations to structure the hard mask stack (202), the upper electrode layer (1006), the resistance switching dielectric layer (1004) and the lower electrode layer (1002) to form a hard mask insulator (120), an upper electrode (118), a resistance switching dielectric (116) and a lower electrode (112). [15] The method of claim 14, further comprising: Forming a sidewall spacer (122) above the substrate (102), extending upwards along the sidewalls of the lower electrode (112), the resistance switching dielectric (116), the upper electrode (118) and the hard mask insulator (120); and Forming an etch stop layer (126) directly on the side wall spacer (122) and an upper surface of the hard mask insulator (120) conformally lining the side wall spacer (122) and the upper surface of the hard mask insulator (120). [16] Method according to claim 15, further comprising: the upper electrode via (132) is formed by: Forming an upper dielectric layer (136) above and around the etch stop layer (126); and Performing an etch through the upper dielectric layer (136) and the hard mask insulator (120) to form a via opening; and Filling the via opening with a metallic material to form an upper electrode via (132) which has a side wall that contacts the hard mask insulator (120) and the etch stop layer (126).

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