Semiconductor storage devices

Abstract

Semiconductor storage device (1) comprising: a plurality of bitline structures having bitlines (BL) extending in parallel in a first lateral direction on a substrate (110); a plurality of buried contacts (BC) and a plurality of landing pads (LP), wherein the plurality of buried contacts (BC) fill lower sections of spaces between the plurality of bitline structures on the substrate (110), wherein the plurality of landing pads (LP) fill upper sections of the spaces between the plurality of bitline structures and extend onto the plurality of bitline structures, wherein the majority of landing pads (LP) have a hexagonal array structure and the centers of the respective top surfaces of a first landing pad (LP1), a second landing pad (LP2) and a third landing pad (LP3), which are adjacent to each other from the majority of landing pads (LP), are connected by an inequal-sided triangle; and a plurality of storage nodes (SN) on the plurality of landing pads (LP), wherein the plurality of storage nodes (SN) has a hexagonal array structure and the centers of the respective top faces of a first storage node, a second storage node and a third storage node, which are adjacent to each other from the plurality of storage nodes (SN), are connected by an equilateral triangle.

Description

background

[0001] The inventive concept relates to a semiconductor storage device and in particular to a semiconductor storage device with landing pads configured to electrically connect active areas to lower electrodes.

[0002] In line with the rapid development of the electronics industry and user demands, electronic devices are being manufactured to be smaller and lighter. This also necessitates a high integration density for the semiconductor memory devices used in these electronic devices, and reduces the design constraints for semiconductor memory configurations. Consequently, the complexity of the process for interconnecting the components contained within the semiconductor memory devices increases.

[0003] US 2015 / 0132943 A1 discloses a method for manufacturing a semiconductor device. The method includes forming insulated contact fillers and an etch control section, wherein the insulated contact fillers fill contact holes defined in a support layer and spaced apart in a first direction and a second direction perpendicular to the first direction, and the etch control layer surrounds the insulated contact fillers; forming an interlinking layer on the insulated contact fillers and the etch control section; and forming interlinking patterns by photo-etching the interlinking layer, the insulated contact patterns, and the etch control section, wherein the interlinking patterns are relatively narrow in the first direction and relatively wide in the second direction.

[0004] US 2006 / 0211192A1 discloses: A semiconductor memory device comprising storage memory and resistors. A method for manufacturing the semiconductor memory device comprises forming an intermediate insulating layer on a semiconductor substrate, including a memory cell array region and a core / perimeter region; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array region; forming a first conductive layer on the resulting structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing surfaces and resistors arranged nonlinearly in at least one direction; and forming storage memory cells, the entire outer side faces of which are exposed, on the landing surfaces.

[0005] US 2019 / 0131307A1 discloses: A semiconductor device may contain a plurality of landing surfaces arranged on a substrate according to a layout, wherein a cross-sectional shape of each of the landing surfaces has a rhombic shape such that opposite interior angles of the rhombic shape are equal to each other and adjacent interior angles of the rhombic shape are unequal to each other. Summary

[0006] The invention is defined in the claims. The inventive concept provides for a semiconductor memory device that can reduce a process difficulty during the manufacturing process of the semiconductor memory device and can ensure the reliability of a connection between components.

[0007] According to one aspect of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device comprises a plurality of bitline structures, having bitlines extending parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fills lower sections of spaces between the plurality of bitline structures on the substrate, and the plurality of landing pads fills upper sections of the spaces between the plurality of bitline structures and extends across the plurality of bitline structures. The plurality of landing pads has a hexagonal array structure, and the centers of the respective top faces of a first, second, and third landing pad, which are adjacent to each other from the plurality of landing pads, are connected by an inequal-sided triangle.

[0008] According to another aspect of the inventive concept, a semiconductor storage device is specified.The semiconductor memory device comprises a substrate in which a plurality of active regions are defined, a plurality of word lines that overlap with the plurality of active regions and extend parallel in a second lateral direction, a plurality of bit line structures containing bit lines on the substrate, the bit lines extending parallel in a first lateral direction perpendicular to the second lateral direction, a plurality of buried contacts, and a plurality of landing pads, wherein the plurality of buried contacts fill lower sections of spaces between the plurality of bit line structures on the substrate, and wherein the plurality of landing pads fill upper sections of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures, and a plurality of memory nodes on the plurality of landing pads.The majority of landing pads have a hexagonal array structure, and the centers of the respective cover surfaces of three adjacent landing pads are connected by an asymmetrical triangle. The majority of storage nodes have a hexagonal array structure, and the centers of the respective cover surfaces of three adjacent storage nodes are connected by an equilateral triangle.

[0009] According to another aspect of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device comprises a substrate in which a plurality of active regions are defined by a device insulation layer, a plurality of word lines that overlap with the plurality of active regions and extend parallel in a second lateral direction, a plurality of bit line structures positioned on the substrate, wherein the plurality of bit line structures extend parallel in a first lateral direction perpendicular to the second lateral direction, a plurality of buried contacts that fill lower sections of spaces between the plurality of bit line structures on the substrate, wherein the plurality of buried contacts are connected to the plurality of active regions, and a plurality of landing pads that are connected to the plurality of buried contacts.wherein the plurality of landing pads fill upper sections of the spaces between the plurality of bitline structures and extend across the plurality of bitline structures, wherein a cover surface of each of the plurality of landing pads has a disk shape, and a plurality of memory nodes positioned on the plurality of bitline structures and connected to the plurality of landing pads. A first, second, and third side of a triangle connecting the midpoints of respective cover surfaces of three adjacent landing pads from the plurality of landing pads each have a length of 3F (F represents a structure size), a length of less than 3F, and a length of more than 3F, respectively. Each of a first, second, and third side of a triangle connecting the midpoints of respective cover surfaces of three adjacent memory nodes from the plurality of memory nodes has a length of 3F. Brief description of the drawings

[0010] The following detailed description, in conjunction with the accompanying drawings, in which the same reference numerals refer to the same elements, provides a clearer understanding of the embodiments of the inventive concept. The drawings show: Fig. 1 a schematic top view of main components of a semiconductor storage device according to an exemplary embodiment; Fig. Figures 2A to 2C are schematic top views illustrating the arrangement of landing pads contained in a semiconductor memory device according to one embodiment; Fig. 3A-3D, 4A-4D, 5A-5D and 6A-6D are cross-sectional views of a process flow of a manufacturing process of a semiconductor memory device according to an exemplary embodiment; Fig. 7A is a top view of an operation for forming mask patterns for forming landing pads contained in a semiconductor storage device according to an embodiment; Fig. 7B is a schematic top view showing the arrangement of the mask patterns. Fig. 7A represents; and Fig. 8A-8D, 9A-9D and 10A-10D are cross-sectional views of a process flow of a manufacturing process of a semiconductor memory device according to an exemplary embodiment. Detailed description of the embodiments

[0011] Fig. Figure 1 is a schematic top view of main components of a semiconductor storage device according to an exemplary embodiment.

[0012] Referring to Fig. 1. The semiconductor storage device 1 can contain a plurality of active regions ACT. In some embodiments, each of the plurality of active regions ACT can be arranged such that it has principal axes in an oblique direction to a first lateral direction (X-direction) and a second lateral direction (Y-direction), which are perpendicular to each other.

[0013] A plurality of word lines WL can overlap with the plurality of active areas ACT and extend parallel in the first lateral direction (X-direction). A plurality of bit lines BL can be arranged on the plurality of word lines WL and extend parallel in the second lateral direction (Y-direction), which overlaps with the first lateral direction (X-direction).

[0014] The majority of bit lines BL can be connected to the majority of active areas ACT via direct contacts DC.

[0015] In some embodiments, the majority of buried contacts BC can be formed between two adjacent bit lines BL. In some embodiments, the majority of buried contacts BC can be formed in a line in both the first lateral direction (X-direction) and the second lateral direction (Y-direction).

[0016] A plurality of landing pads LP can each be formed on the plurality of buried contacts BC. The plurality of landing pads LP can be arranged such that they at least partially overlap the plurality of buried contacts BC. In some embodiments, each of the plurality of landing pads LP can extend to any of the two adjacent bit lines. The plurality of landing pads LP can have a hexagonal array structure when viewed from above. For example, when viewed from above, the plurality of landing pads LP can be arranged in a line in the first lateral direction (X-direction) and in a zigzag pattern in the second lateral direction (Y-direction) to form a honeycomb structure.For example, when viewed from above, the honeycomb shape can consist of a group of six landing pads LP arranged in a hexagonal array structure, with each of the six landing pads LP on a corresponding edge of the hexagon and a seventh landing pad LP positioned inside the hexagon formed by the group of six landing pads LP.

[0017] The majority of landing pads LP can be formed using, for example, an extreme ultraviolet (EUV) lithography process. In some embodiments, the majority of landing pads LP can be formed without using a pattern density increase technique that includes a photolithographic process, such as a double pattern technology (DPT) or a quad pattern technology (QPT). A cover surface of each of the majority of landing pads LP can have a disc shape whose edges are not elliptical but essentially rounded.

[0018] A plurality of memory nodes SN can be configured on a plurality of landing pads LP. The plurality of memory nodes SN can be configured above a plurality of bit lines BL. Each of the plurality of memory nodes SN can be a lower electrode of a plurality of capacitors. The memory node SN can be connected to the active areas ACT via the landing pad LP and the buried contact BC. The plurality of memory nodes SN can have a hexagonal array structure when viewed from above. For example, when viewed from above, the plurality of memory nodes SN can be arranged in a line in the first lateral direction (X-direction) and in a zigzag pattern in the second lateral direction (Y-direction) to form a honeycomb structure.For example, when viewed from above, the honeycomb shape can consist of a group of six storage nodes NS arranged in a hexagonal array structure, with each of the six storage nodes SN at a corresponding edge of the hexagon and a seventh storage node SN positioned inside the hexagon formed by the group of six storage nodes SN.

[0019] The honeycomb pattern in which the majority of landing pads (LP) are arranged may differ slightly from the honeycomb pattern in which the majority of storage nodes (SN) are arranged. For example, the centers of three adjacent landing pads (LP) may be connected by an inequilateral triangle, while the centers of three adjacent storage nodes (SN) may be connected by an isosceles triangle or an equilateral triangle (or a regular triangle). This arrangement is referred to as Fig. 2A to 2C are described in detail. Three adjacent of the plurality of landing pads LP can contain two landing pads LP at adjacent corners of the hexagonal structure and one landing pad LP positioned inside the hexagon formed by the group of six landing pads LP; and three adjacent of the plurality of storage nodes SN can contain two storage nodes SN at adjacent corners of the hexagonal structure and one storage node SN positioned inside the hexagon formed by the group of six storage nodes SN.

[0020] When used as herein, the center point of the landing pad LP and the center point of the storage node SN can each refer to the center point of the top surface of the landing pad LP and the center point of the top surface of the storage node SN, respectively, when viewed from above (on an XY plane).

[0021] Fig. Figures 2A to 2C are schematic top views illustrating the arrangement of landing pads contained in a semiconductor memory device according to one embodiment.

[0022] Referring to Fig. 2A A plurality of landing pads LP can exhibit a hexagonal array structure when viewed from above. For example, the plurality of landing pads LP can be arranged in a line in a first lateral direction (X-direction) and in a zigzag pattern in a second lateral direction (Y-direction) to form a honeycomb shape.

[0023] The landing pads LP and imaginary reference landing pads LPR are together in Fig. Figure 2A illustrates the arrangement of the plurality of landing pads LP. In a plurality of reference landing pads LPR, the centers LPR-C of three adjacent reference landing pads LPR can be connected by an isosceles triangle or an equilateral triangle, and at least two of the three interior angles of a triangle connecting the centers LPR-C of the three adjacent reference landing pads LPR can have the same value. A diameter DI-R of the reference landing pad LPR can be equal to a diameter DI-L of the landing pad LP. In some embodiments, the plurality of reference landing pads LP can be formed using a pattern density increase technique that incorporates a photolithographic process, such as DPT or QPT.

[0024] For example, a first reference interior angle θ1-R and a second reference interior angle θ2-R can be interior angles between a base connecting the respective centers LPR-C of two reference landing pads LPR that are adjacent to each other in a first lateral direction (X-direction) of the three adjacent reference landing pads LPR, and two sides connecting the respective centers LPR-C of the two reference landing pads LPR that are adjacent to each other in the first lateral direction (X-direction) to the center LPR-C of a reference landing pad LPR that is adjacent to the two reference landing pads LPR in a second lateral direction (Y-direction). The first reference interior angle θ1-R can be equal to the second reference interior angle θ2-R.In some embodiments, a third reference interior angle θ3-R can be an interior angle between the two sides connecting the respective centers LPR-C of the two reference landing pads LPR that are adjacent to each other in the first lateral direction (X-direction), and the center LPR-C of the one reference landing pad LPR that is adjacent to the two reference landing pads LPR in the second lateral direction (Y-direction). The third reference interior angle θ3-R can be equal to both the first reference interior angle θ1-R and the second reference interior angle θ2-R. For example, the first reference interior angle θ1-R, the second reference interior angle θ2-R, and the third reference interior angle θ3-R can all be 60°.

[0025] In three adjacent datum landing pads LPR, the distance between the respective centers LPR-C of two datum landing pads LPR that are adjacent to each other in the first lateral direction (X-direction) can be called a datum base distance LB-R. Distances from the respective centers LPR-C of the two datum landing pads LPR that are adjacent to each other in the first lateral direction (X-direction) to the center LPR-C of a datum landing pad LPR that is adjacent to the two datum landing pads LPR in the second lateral direction (Y-direction) can each be called a first datum side distance LS-R1 and a second datum side distance LS-R2.

[0026] The first reference side spacing LS-R1 can be equal to the second reference side spacing LS-R2. For example, the first reference side spacing LS-R1 and the second reference side spacing LS-R2 can have a value of 3F (where F represents a feature size). For example, 3F can be approximately 25.6 nm, but is not limited to this. In some embodiments, the first reference side spacing LS-R1, the second reference side spacing LS-R2, and the reference base spacing LB-R can have the same reference spacing value. For example, the first reference side spacing LS-R1, the second reference side spacing LS-R2, and the reference base spacing LB-R, which is equal to the reference spacing, can all have a value of 3F. In some other embodiments, the reference base distance LB-R can be the reference distance, and the first reference side distance LS-R1 and the second reference side distance LS-R2 can have the same value, which may be greater or smaller than the reference distance.

[0027] For example, in the case of three adjacent landing pads LP or the majority of landing pads LP, the respective midpoints LP-C of two landing pads LP that are adjacent to each other in the first lateral direction (X-direction) and a midpoint LP-C of a landing pad LP that is adjacent to the two adjacent landing pads LP in the second lateral direction (Y-direction) can be connected by an inequal-sided triangle.

[0028] From the plurality of landing pads LP, three landing pads LP that are so close to each other that lines connecting the centers LP-C of the three landing pads LP form a triangle can, for the sake of brevity, be designated as the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3. For example, two landing pads LP that are adjacent to each other in the first lateral direction (X-direction) can be designated as the first landing pad LP1 and the second landing pad LP2, respectively, and a landing pad LP that is adjacent to the first landing pad LP1 and the second landing pad LP2 in the second direction (Y-direction) can be designated as the third landing pad LP3.

[0029] The three interior angles of a triangle connecting the respective centers LP-C of the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3 can each be different. For example, a first interior angle θ1 can be an interior angle between a base connecting the respective centers LP-C of the first landing pad LP1 and the second landing pad LP2, and a side connecting the first landing pad LP1 and the third landing pad LP3. A second interior angle θ2 can be an interior angle between a base connecting the respective centers LP-C of the first landing pad LP1 and the second landing pad LP2, and a side connecting the second landing pad LP2 and the third landing pad LP3.A third interior angle θ3 can be an interior angle between the side connecting the first landing pad LP1 and the third landing pad LP3, and the side connecting the second landing pad LP2 and the third landing pad LP3. The first interior angle θ1, the second interior angle θ2, and the third interior angle θ3 can each be different from one another. The first interior angle θ1 can differ from the second interior angle θ2. For example, the first interior angle θ1 can be greater than 60°, and the second interior angle θ2 can be less than 60°. The third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0030] A distance between the respective centers LP-C of the first landing pad LP1 and the second landing pad LP2 can be called a base distance LB, and a distance between the respective centers LP-C of the first landing pad LP1 and the third landing pad LP3 can be called a first lateral distance LS1. Furthermore, a distance between the respective centers LP-C of the second landing pad LP2 and the third landing pad LP3 can be called a second lateral distance LS2.

[0031] The base distance LB and the reference base distance LB-R can have the same value (i.e., the reference distance). For example, the base distance LB can have a value of 3F.

[0032] The first side distance LS1 can differ from the second side distance LS2. In some embodiments, the first side distance LS1 can be smaller than the base distance LB (i.e., the reference distance), and the second side distance LS2 can be larger than the base distance (i.e., the reference distance). For example, the first side distance LS1 can be less than 3F, and the second side distance LS2 can be greater than 3F.

[0033] The plurality of landing pads LP can be arranged in a line in the first lateral direction (X-direction) and in a zigzag pattern in the second lateral direction (Y-direction). Likewise, the plurality of reference landing pads LPR can be arranged in a line in the first lateral direction (X-direction) and in a zigzag pattern in the second lateral direction (Y-direction). Both the plurality of landing pads LP and the plurality of reference landing pads LPR can extend onto one of two adjacent bit lines BL corresponding to them. In some embodiments, the plurality of landing pads LP may not extend onto the bit lines BL. For example, only a portion of the plurality of landing pads LP may extend onto one of the two adjacent bit lines BL.

[0034] The midpoint LP-C of each of the plurality of landing pads LP can be moved from the midpoint LPR-C of each of the plurality of reference landing pads LPR in the first lateral direction (X-direction) or in a direction (-X-direction) opposite the first lateral direction (X-direction) in a direction away from the adjacent bit line BL.

[0035] For example, the respective centers LP-C of the landing pads LP, which are arranged in a row in the first lateral direction (X-direction), can be moved by a first movement distance CD in the first lateral direction (X-direction) relative to the respective centers LPR-C of the reference landing pads LPR, which are also arranged in a row in the first lateral direction (X-direction). Furthermore, the respective centers LP-C of the landing pads LP adjacent to the landing pads LP arranged in one row in the second lateral direction (Y-direction) and in another row in the first lateral direction (X-direction) can be moved by a second movement distance CD2 relative to the respective centers LPR-C of the reference landing pads LPR, which are also arranged in a row in the first lateral direction (X-direction), relative to the first lateral direction (X-direction).In some embodiments, the first movement distance CD1 can be equal to the second movement distance CD2. For example, both the first movement distance CD1 and the second movement distance CD2 can be greater than 0 and less than 0.75 F. In some embodiments, both the first movement distance CD1 and the second movement distance CD2 can be in a range of approximately 1 nm to approximately 6 nm.

[0036] The majority of landing pads (LP) can be formed using, for example, an EUV lithography process. In some embodiments, the majority of landing pads (LP) can be formed without using a pattern density increase technique that includes a photolithographic process such as DPT or QPT.

[0037] Accordingly, unlike the one in Fig. In the majority of reference landing pads LPR shown in 2A, the majority of landing pads LP can be designed in such a way that they have a distorted honeycomb shape.

[0038] Compared to the reference landing pad LPR, the center point LP-C of the landing pad LP can be shifted in one direction away from the adjacent bit line BL. This allows the width (in the first lateral direction (X-direction)) of the landing pad LP, extending in a vertical direction (Z-direction), to be increased along a side surface of the adjacent bit line BL. Accordingly, an overlap margin between the landing pad LP and the buried contact (e.g., the buried contact BC in) can be achieved. Fig. 1) that correspond to each other, can be increased. Thus, the reliability of an electrical connection between the corresponding landing pad LP and the corresponding buried contact BC can be improved. Additionally, the distance in the first lateral direction (X-direction) between a landing pad LP and a corresponding buried contact BC can be increased. This prevents the formation of a bridge between the landing pad LP and another corresponding buried contact BC.

[0039] If the majority of landing pads LP are formed using a mask density increase technique that includes a photolithographic process such as DPT or QPT, a cover surface of each landing pad LP can have a rhombic or parallelogram shape with unrounded edges, or a rhombic or parallelogram shape with rounded edges. However, since the majority of landing pads LP according to the present embodiment can be formed using an EUV lithography process, a cover surface of each of the majority of landing pads LP can have a disc shape with substantially rounded edges that are not elliptical.

[0040] Accordingly, the distance between the respective landing pads (LP) can be increased. This prevents the formation of a bridge between adjacent landing pads (LP) and improves the gap-filling properties of an insulating structure (e.g., insulating structures 195 in). Fig. The insulation between the majority of landing pads (LP) can be improved. This results in an enhanced reliability of electrical insulation between the respective landing pads.

[0041] Referring to Fig. 2B A plurality of storage nodes SN can be positioned on the plurality of landing pads LP. For example, when viewed from a top view, each storage node SN can completely overlap a corresponding landing pad LP. The diameter DI-S of the storage node SN can be larger than the diameter DI-L of the landing pad LP. The plurality of landing pads LP can be arranged such that they have a distorted honeycomb shape, as shown with reference to Fig. 2A described. The majority of storage nodes SN can be arranged in a complete honeycomb pattern.

[0042] The respective centers LP-C of the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3 can be connected by an inseparable triangle. For example, the first interior angle θ1 and the second interior angle θ2 of a triangle connecting the respective centers LP-C of the first landing pad LP2, the second landing pad LP2, and the third landing pad LP3 can differ. For example, the first interior angle θ1 can be greater than 60°, the second interior angle θ2 can be less than 60°, and the third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0043] The respective centers SN-C of three storage nodes SN, corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3, respectively, can be connected by an isosceles triangle or an equilateral triangle. For example, the distance between the center SN-C of storage node SN corresponding to the first landing pad LP1 and the center SN-C of storage node corresponding to the third landing pad LP3 can be equal to the distance between the center SN-C of storage node SN corresponding to the second landing pad LP2 and the center SN-C of storage node SN corresponding to the third landing pad LP3. In some embodiments, the distances between the centers SN-C of the three storage nodes corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3 can have the same value as a reference distance. For example, the reference distance can be 3F.In some other embodiments, the distance between the center point SN-C of storage node SN corresponding to the first landing pad LP1 and the center point SN-C of storage node SN corresponding to the second landing pad LP2 can be the same value as the reference distance. Similarly, the distance between the center point SN-C of storage node SN corresponding to the first landing pad LP1 and the center point SN-C of storage node SN corresponding to the third landing pad LP3, and the distance between the center point SN-C of storage node SN corresponding to the second landing pad LP2 and the center point SN-C of storage node SN corresponding to the third landing pad LP3, can be the same value, slightly larger or smaller than the reference distance.

[0044] A triangle connecting the centers SN-C of the three storage nodes SN, corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3, respectively, can have a first internal node angle θ1-S and a second internal node angle θ2-S of the same value. In some embodiments, a third internal node angle θ3-S can be equal to both the first internal node angle θ1-S and the second internal node angle θ2-S. For example, the first internal node angle θ1-S, the second internal node angle θ2-S, and the third internal node angle θ3-S can all be 60°.

[0045] Referring to Fig. 2C allows the majority of landing pads (LP) to have a hexagonal array structure. For example, the majority of landing pads (LP) can be arranged in a line in the first lateral direction (X-direction) and in a zigzag pattern in the second lateral direction (Y-direction) to form a honeycomb shape.

[0046] The respective centers LP-C of the three adjacent landing pads (i.e., the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3) can be connected by an inseparable triangle. The three interior angles of this triangle can differ from each other. The first interior angle θ1 can differ from the second interior angle θ2. For example, the first interior angle θ1 can be greater than 60°, and the second interior angle θ2 can be less than 60°. The third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0047] The first side distance LS1 can differ from the second side distance LS2. In some embodiments, the first side distance LS1 can be smaller than the base distance LB, and the second side distance LS2 can be larger than the base distance LB. For example, the first side distance LS1 can be smaller than 3F, and the second side distance LS2 can be larger than 3F.

[0048] An imaginary mean extension line HVL can extend from the center of a base connecting the respective midpoints LP-C of the first landing pad LP1 and the second landing pad LP2 in the second lateral direction (Y-direction). The imaginary mean extension line HVL can be perpendicular to the base connecting the respective midpoints LP-C of the first landing pad LP1 and the second landing pad LP2. The midpoint LP-C of the third landing pad LP3 can be spaced from the imaginary mean extension line HVL by a mean displacement distance TCD in the first lateral direction (X-direction). The midpoint LP-C of the third landing pad LP3 can be shifted away from the imaginary mean extension line BL in a direction away from the bit line BL by the mean displacement distance TCD in the first lateral direction (X-direction). The mean displacement distance TCD can be the one in Fig. The sum of the first movement distance CD1 and the second movement distance CD2 shown in Figure 2A is equal. The mean movement distance TCD can be greater than 0 and less than half the base distance LB. For example, the mean movement distance TCD can be greater than 0 and less than 1.5 F. In some embodiments, the mean movement distance TCD can be in a range of approximately 2 nm to approximately 12 nm.

[0049] As with reference to Fig. As described in section 2A, the reliability of an electrical connection between the landing pad LP according to the present embodiment and the corresponding buried contact BC can be improved, and the formation of a bridge between the landing pad LP and another buried contact BC adjacent to the corresponding buried contact BC can be prevented. Additionally, the reliability of electrical insulation between the respective landing pads LP can be improved.

[0050] Furthermore, as with regard to Fig. As described in Figure 2B, the plurality of storage nodes SN according to the present embodiment can be arranged in a honeycomb shape such that the respective centers SN-C of the three adjacent storage nodes SN are connected by an isosceles triangle or an equilateral triangle. Accordingly, each of the plurality of storage nodes SN can have a diameter DI-S that is larger than the diameter DI-L of the landing pad LP and can also prevent the formation of a bridge between adjacent storage nodes SN. Thus, a capacitance of each of a plurality of capacitor structures (e.g., capacitor structures 200 in) can be achieved. Fig. 10A and Fig. 10C) can be increased, thus improving the data archiving reliability of each of the majority of capacitor structures 200.

[0051] Fig. Figures 3A to 6D are cross-sectional views of a process flow of a manufacturing process for a semiconductor storage device according to an exemplary embodiment. Fig. 7A is a top view of an operation for forming mask patterns for the formation of landing pads contained in a semiconductor storage device according to an embodiment. Fig. 7B is a schematic top view showing the arrangement of the Fig. The mask pattern shown in 7A represents the pattern shown in 7A. Fig. Figures 8A to 10D are cross-sectional views of a process flow in a manufacturing process for a semiconductor memory device according to an exemplary embodiment. Specifically, they are Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 8A, Fig. 9A and Fig. 10A Cross-sectional views along a line AA' in Fig. 1 or Fig. 7A. Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 8B, Fig. 9B and Fig. 10B are cross-sectional views along a line BB' in Fig. 1 or Fig. 7A. Fig. 3C, Fig. 4C, Fig. 5C, Fig. 6C, Fig. 8C, Fig. 9C and Fig. 10C are cross-sectional views along a line CC' in Fig. 1 or Fig. 7A. Fig. 3D, Fig. 4D, Fig. 5D, Fig. 6D, Fig. 8D, Fig. 9D and Fig. 10D are cross-sectional views along a line DD' in Fig. 1 or Fig. 7A.

[0052] Referring to Fig. 3A to 3D, a device insulation recess 116T can be formed in a substrate 110, and device insulation layers 116 can be formed to fill the device insulation recesses 116T. A plurality of active regions 118 can be defined by the device insulation layers 116 in the substrate 110. Each of the active regions 118 can have a relatively long island shape with a minor axis and a major axis, as shown in Fig. 1 shown active areas ACT.

[0053] For example, substrate 110 can contain silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, substrate 110 can contain a semiconductor element, such as germanium (Ge), or at least one compound semiconductor selected from silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, substrate 110 can have a silicon-on-insulator (SOI) structure. For example, substrate 110 can contain a buried oxide layer (BOX). Substrate 110 can contain a conductive region, such as a doped well or a doped structure.

[0054] The device insulation layer 116 can, for example, contain a material that includes at least one silicon oxide layer, one silicon nitride layer, and one silicon oxynitride layer. The device insulation layer 116 can be a single layer containing one type of insulating layer, a double layer containing two types of insulating layers, or a multilayer structure containing a combination of at least three types of insulating layers. For example, the device insulation layer 116 can be a double layer or a multilayer structure containing an oxide layer and a nitride layer. However, according to the inventive concept, the configuration of the device insulation layer 116 is not limited to the above description.

[0055] A plurality of word-line recesses 120T can be formed in the substrate 110. The plurality of word-line recesses 120T can extend parallel in a first lateral direction (X-direction) and have line shapes that intersect the active areas 118 and are generally arranged at equal distances in a second lateral direction (Y-direction). As shown in a cross-sectional view section along line BB' in Fig. As shown in Figure 3B, steps can be formed in the bottoms of the plurality of word-line recesses 120T. For example, elevations above the substrate 110 can be formed along the bottoms of the plurality of word-line recesses 120T. In some embodiments, the device insulation layer 116 and the substrate 110 can be etched during the formation of the plurality of word-line recesses 120T using separate etching processes such that an etched depth of the device insulation layer 116 differs from an etched depth of the substrate 110. For example, in the bottoms of the plurality of word-line recesses 120T, upper surfaces of the substrate 110 can be higher than upper surfaces of the device insulation layer 116.In some embodiments, the device insulation layer 116 and the substrate 110 can be etched together during the formation of the plurality of word line recesses 120T using separate etching processes such that the etched depth of the device insulation layer 116 differs from the etched depth of the substrate 110 due to a difference in the etch rate between the device insulation layer 116 and the substrate 110.

[0056] The resulting structure, which contains the plurality of word line recesses 120T, can be cleaned, and a plurality of dielectric gate layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 can then be sequentially formed inside the plurality of word line recesses 120T. The plurality of word lines 120 can be the in Fig. 1. The plural of word lines shown forms WL.

[0057] The plurality of word lines 120 can fill the lower sections of the plurality of word line recesses 120T, and the plurality of buried insulating layers 124 can cover the plurality of word lines 120 and fill the upper sections of the plurality of word line recesses 120T. The plurality of dielectric gate layers 122 can be formed between the plurality of word lines 120 and the device insulating layer 116 and the substrate 110. Accordingly, the plurality of word lines 120 can extend parallel in the first lateral direction (X-direction) and have line shapes that intersect the active regions 118 and are generally arranged at equal distances in a second lateral direction (Y-direction).Similarly, the majority of buried insulation layers 124 can extend parallel in the first lateral direction (X-direction) and have line shapes which overlap the active areas 118 and are generally arranged at equal distances in the second lateral direction (Y-direction).

[0058] For example, the plurality of word lines 120 can contain titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. In some embodiments, each of the plurality of word lines 120 can contain a core layer and a barrier layer between the core layer and the dielectric gate layer 122. For example, the core layer can contain a metallic material or a conductive metal nitride, such as W, WN, TiSiN, or WSiN, and the barrier layer can contain a metallic material or a conductive metal nitride, such as Ti, TiN, Ta, or TaN.

[0059] The dielectric gate layer 122 can contain at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a dielectric layer with a high k-value that has a higher dielectric constant than the silicon oxide layer. For example, the dielectric gate layer 122 can have a dielectric constant of approximately 10 to approximately 25.In some embodiments, the dielectric gate layer 122 may contain at least one material selected from the following: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), sirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and conductive scandium tantalum oxide (PbScTaO). For example, the dielectric gate layer 122 can contain HfO2, Al2O3, HfAlO3, Ta2O3 or TiO2.

[0060] The cover surfaces of the majority of buried insulating layers 124 can be at substantially the same level as a cover surface of the substrate 110. The buried insulating layers 124 can contain a material layer selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0061] A top surface of each of the plurality of word lines 120 can be at a lower level than the top surface of the substrate 110. Bottom surfaces of the plurality of word lines 120 can have an uneven shape and saddle fin field-effect transistors (FinFETs) can be formed in the plurality of active regions 118.

[0062] As used herein, the term "plane" refers to a height measured in a vertical direction (Z-direction) to a major surface of the substrate 110. That is to say, it is understood that when two elements are described as being positioned on the same plane or a predetermined plane, the two elements may have the same height or a predetermined height in the vertical direction (Z-direction) to the major surface of the substrate 110. Furthermore, unless otherwise specified, it is understood that when an element is described as being positioned on a lower / higher plane, the element may have a smaller / greater height in the vertical direction (Z-direction) relative to the major surface of the substrate 110. As used herein, terms such as "same," "identical," "planar," or "coplanar" encompass near-identical implicit variations that may occur, for example, due to manufacturing processes.The term “essentially” may be used herein to emphasize this meaning unless the context or other information indicates otherwise.

[0063] In some embodiments, after the plurality of word lines 120 have been formed, impurity ions can be introduced into sections of the active regions 118 of the substrate 110 on both sides of the plurality of word lines 120, thus forming source regions and drain regions in the plurality of active regions 118. In some other embodiments, before the plurality of word lines 120 are formed, an ion insertion process can be carried out to form source regions and drain regions.

[0064] Referring to Fig. 4A to 4D can be formed with an insulating pattern 112 and 114 to cover the device insulating layer 116, the majority of active areas, and the majority of buried insulating layers 124. For example, the insulating pattern 112 and 114 can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal-based dielectric layer, or a combination thereof.

[0065] In some embodiments, the insulating pattern 112 and 114 can contain a plurality of insulating layers, comprising a first insulating pattern 112 and a second insulating pattern 114 stacked on top of each other (e.g., the second insulating pattern 114 is formed on the first insulating pattern 112). For example, the second insulating pattern 114 can have a higher dielectric constant than the first insulating pattern 112.

[0066] In some embodiments, the first insulating pattern 112 may contain a silicon oxide layer and the second insulating pattern 114 may contain a silicon oxynitride layer.

[0067] In some other embodiments, the first insulating pattern 112 can contain a non-metal-based dielectric layer and the second insulating pattern 114 can contain a metal-based dielectric layer. For example, the first insulating pattern 112 can contain a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the second insulation pattern 114 may contain at least one material selected from the following: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), sirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and leading scandium tantalum oxide (PbScTaO).

[0068] Subsequently, direct contact holes 134H can be formed to penetrate the insulating pattern 112 and 114. The direct contact holes 134H can be configured to expose the source regions in the active regions 118. In some embodiments, the direct contact holes 134H can extend into the active regions 118, that is, into the source regions.

[0069] Referring to Fig. 5A to 5D may contain a conductive direct contact layer to fill the direct contact holes 134H and cover the insulating pattern 112 and 114. The conductive direct contact layer may contain, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. In some embodiments, the conductive direct contact layer may contain an epitaxial silicon layer. In some embodiments, the conductive direct contact layer may contain doped polysilicon.

[0070] Subsequently, a metal-based conductive layer and an insulating closure layer can be sequentially formed to cover the insulating pattern 112 and 114 and the conductive direct contact layer and to cover a bit line structure 140.

[0071] In some embodiments, the metal-based conductive layer can have a stacked structure of a first metal-based conductive layer and a second metal-based conductive layer. For example, the metal-based conductive layer can have a stacked structure of two layers; however, the inventive concept is not limited to this. For example, the metal-based conductive layer can contain a single layer or a stacked structure of at least three layers.

[0072] In some embodiments, the first metal-based conductive layer may contain titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based conductive layer may contain tungsten (W) or tungsten and tungsten silicide (WSix). In some embodiments, the first metal-based conductive layer may act as a diffusion barrier. In some embodiments, the insulating closure layer may contain a silicon nitride layer.

[0073] The first metal-based conductive layer, the second metal-based conductive layer, and the insulating seal layer can be etched, forming a plurality of bitlines 147 and a plurality of insulating seal lines 148. Each of the plurality of bitlines 147 can contain a first metal-based conductive pattern 145 and a second metal-based conductive pattern 146, each exhibiting line shapes. Side surfaces of the first metal-based conductive pattern 145, the second metal-based conductive pattern 146, and the plurality of insulating seal lines 148 can align with one another. A bitline 147 and an insulating seal line 148 covering the first bitline 147 can form a bitline structure 140.

[0074] In some embodiments, the bitline structure 140 may further include a conductive semiconductor pattern 132 arranged between the insulating patterns 112 and 114 and the first metal-based conductive pattern 145. The conductive semiconductor pattern 132 may contain doped polysilicon. In some embodiments, the conductive semiconductor pattern 132 may not be formed but omitted.

[0075] The majority of bitline structures 140, which contain the majority of bitlines 147 and the majority of insulating closure lines 148, can extend parallel in the second lateral direction (Y-direction) parallel to the main surface of the substrate 110. The majority of bitlines 147 can be in Fig. The plurality of bit lines shown (BL) is formed.

[0076] During the etching process to form the plurality of bit lines 147, sections of the conductive direct contact layer that do not vertically overlap the bit lines 147 can be removed together using the etching process to form a plurality of conductive direct contact patterns 134. In this case, the insulating pattern 112 and 114 can act as an etch stop layer during an etching process to form the plurality of bit lines 147 and the plurality of conductive direct contact patterns 134. The plurality of conductive direct contact patterns 134 can be used in Fig. The plurality of direct contacts shown in 1 form DC. The plurality of bit lines 147 can be electrically connected to the plurality of active areas 118 via the plurality of conductive direct contact patterns 134.

[0077] In some embodiments, the conductive semiconductor pattern 132 can be formed together during the process of removing the sections of the conductive direct contact layer to form the conductive direct contact pattern 134. For example, from a section of the conductive direct contact layer that vertically overlaps the bit line 147, the conductive semiconductor pattern 132 can be a section positioned on the insulating pattern 112 and 114 without overlapping the direct contact hole 134H, whereas the conductive direct contact pattern 134 can be a section that vertically overlaps the direct contact hole 134H while touching the active area 118.

[0078] Both side walls of the plurality of bit-line structures 140 can be covered by a plurality of insulating spacer structures 150. Each of the plurality of insulating spacer structures 150 can contain first insulating spacers 152, second insulating spacers 154, and third insulating spacers 156. The second insulating spacers 154 can contain a material with a lower dielectric constant than the first insulating spacers 152 and the third insulating spacers 156. In some embodiments, the first insulating spacers 152 and the third insulating spacers 156 can contain a nitride layer, and the second insulating spacers 154 can contain an oxide layer.In some embodiments, the first insulating spacers 152 and the third insulating spacers 156 may contain a nitride layer, and the second insulating spacers 154 may contain a material with an etch selectivity with respect to the first insulating spacers 152 and the third insulating spacers 156. For example, if the first insulating spacers 152 and the third insulating spacers 156 contain a nitride layer, the second insulating spacers 154 may contain an oxide layer. The second insulating spacers 154 may be removed during a subsequent process to form air spacers.

[0079] A plurality of buried contact holes 170H can be formed between the plurality of bit lines 147. An interior of each of the plurality of buried contact holes 170H can be defined by the active area 118 and the insulating spacer structure 150, which covers a side wall of each of the plurality of bit lines 147 between the two adjacent bit lines 147.

[0080] The majority of buried contact holes 170H can be formed by removing sections of the insulating pattern 112 and 114 and the active area 118 by using the insulating spacer structure 150, which covers both side walls of each of the majority of insulating closure lines 148, and the majority of bit line structures 140 as an etching mask. The formation of the plurality of buried contact holes 170H can include performing an anisotropic etching process to remove sections of the insulating pattern 112 and 114 and the active area 118 by using the insulating spacer structure 150, which covers both side walls of each of the plurality of insulating closure lines 148, and the plurality of bit line structures 140 as an etching mask, and then performing an isotropic etching process to further remove other sections of the active areas 118 in order to extend spaces defined by the active areas 118.

[0081] Referring to Fig. 6A to 6D can have a plurality of buried contacts 170 and a plurality of insulating fences 180 in spaces between the plurality of insulating spacer structures 150, which cover both side walls of the respective bit line structures 140. The plurality of buried contacts 170 and the plurality of insulating fences 180 can be positioned alternately along a space between a pair of insulating spacer structures 150 from the plurality of insulating spacer structures 150, which cover both side walls of the bit line structures 140, namely in the second lateral direction (Y-direction).

[0082] For example, the majority of buried contacts may contain polysilicon 170. For example, the majority of insulating fences may contain a nitride layer 180.

[0083] In some embodiments, the plurality of buried contacts 170 can be arranged in a line in both the first lateral direction (X-direction) and the second lateral direction (Y-direction). Each of the plurality of buried contacts 170 can extend from the active areas 118 in the vertical direction (Z-direction) perpendicular to the substrate 110. The plurality of buried contacts 170 can be arranged in Fig. 1. The majority of buried contacts shown form BC.

[0084] The majority of buried contacts 170 can be arranged in spaces defined by the majority of insulating distance structures 150, which cover both side walls of the majority of insulating fences 180 and the majority of bit line structures 140.

[0085] The formation of the majority of buried contacts 170 can include the formation of a preliminary buried contact material layer to fill the majority of buried contact holes 170H and the removal of upper portions of the preliminary buried contact material layer. For example, the preliminary buried contact material layer can contain polysilicon.

[0086] The cover surfaces of the majority of buried contacts 170 can be at a lower level than the cover surfaces of the majority of insulating closure lines 148. The cover surfaces of a majority of insulating fences 180 can be at the same level as the cover surfaces of the insulating closure lines 148 in the vertical direction (Z-direction). Accordingly, the cover surfaces of the majority of buried contacts 170 can be at a lower level than the cover surfaces of the majority of insulating fences 180.

[0087] A plurality of landing pad holes 190H can be defined by the plurality of isolation spacer structures 150 and the plurality of isolation fences 180. The plurality of buried contacts 170 can be exposed on the bottoms of the plurality of landing pad holes 190H.

[0088] In some embodiments, the preliminary buried contact material layer can be formed after the majority of insulating fences 180 have been formed. In some other embodiments, the majority of insulating fences 180 can be formed after the preliminary buried contact material layer has been formed. In some other embodiments, after the majority of insulating fences 180 have been formed, the layer with reference to Fig. The majority of buried contact holes 170H described in 5A to 5D can be formed, and the preliminary buried contact material layer can be formed to fill the majority of buried contact holes 170H.

[0089] The plurality of buried contacts 170 can fill lower sections of spaces between the plurality of insulating spacer structures 150, which cover both side walls of the respective bit line structures 140. In some embodiments, the cover surfaces of the plurality of buried contacts 170 can be formed on a plane that is equal to or higher than a plane of the cover surfaces of the bit lines 147, however, the inventive concept is not limited thereto.

[0090] During the formation of the majority of buried contacts 170, upper sections of the insulating closure line 148 and the insulating spacer structure 150, which are contained in the bit line structure 140, can be removed, and thus a level of a cover surface of the bit line structure 140 can be lowered.

[0091] Referring to Fig. 7A to 8D, a landing pad material layer 190P can be formed to fill the majority of landing pad holes 190H and to cover the majority of bit line structures 140, and a majority of mask patterns MK can be formed on the landing pad material layer 190P.

[0092] In some embodiments, a metal silicide layer can be formed on the majority of buried contacts 170 before the landing pad material layer 190P is formed. The metal silicide layer can be located between the majority of buried contacts 170 and the landing pad material layer 190P. The metal silicide layer can contain, but is not limited to, cobalt silicide (CoSix), nickel silicide (NiSix), or manganese silicide (MnSix).

[0093] In some embodiments, the landing pad material layer 190P can include a conductive barrier layer and a conductive pad material layer on top of the conductive barrier layer. For example, the conductive barrier layer can contain a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer can have a Ti / TiN stacked structure. For example, the conductive pad material layer can contain a metal. In some embodiments, the conductive pad material layer can contain tungsten (W).

[0094] The plurality of mask patterns MK can be formed using, for example, EUV lithography processes. In some embodiments, the plurality of mask patterns MK can be formed without using a pattern density increase technique that includes a photolithographic process such as DPT or QPT. A cover surface of each plurality of mask patterns MK can be formed in a disk shape whose edges are not elliptical but rounded when viewed from top to bottom; however, the inventive concept is not limited to this. For example, the cover surface of each plurality of mask patterns MK can have a modified disk shape whose edges are substantially rounded by using an optical near-effect correction (OPC) method such that a cover surface of each plurality of landing pads (e.g., landing pads 190 in Fig. 9A and Fig. 9C), which are the resulting structures obtained by etching the landing pad material layer 190P using the plurality of mask patterns MK as an etching mask, have a disk shape whose edges are not elliptical but substantially rounded when viewed from top to bottom. A side surface at the edge of each of the plurality of mask patterns MK can be substantially perpendicular to a top surface of the landing pad material layer 190P.

[0095] The majority of mask patterns MK can exhibit a hexagonal array structure. For example, the majority of mask patterns MK can be arranged in a line in a first lateral direction (X-direction) and in a zigzag pattern in a second lateral direction (Y-direction) to form a honeycomb shape.

[0096] The mask patterns MK and imaginary reference mask patterns MKR are together in Fig. Figure 7B illustrates the arrangement of the plurality of mask patterns MK. In a plurality of reference mask patterns MKR, the centers MKR-C of three adjacent reference mask patterns MKR can be connected by an isosceles triangle or an equilateral triangle. A diameter DI-MR of the reference mask pattern MKR can be equal to a diameter DI-M of the mask pattern MK. In some embodiments, the plurality of reference mask patterns MKR can be formed using a pattern density increase technique that incorporates a photolithographic process, such as DPT or QPT.

[0097] For example, three interior angles of a triangle connecting the centers MKR-C of the three adjacent reference mask patterns MKR are the first reference interior angle θ1-R, the second reference interior angle θ2-R, and the third reference interior angle θ3-R, which are related to Fig. 2A is described as follows, so a detailed description is omitted. The first reference interior angle θ1-R can be equal to the second reference interior angle θ2-R. In some embodiments, the third reference interior angle θ3-R can be equal to both the first reference interior angle θ1-R and the second reference interior angle θ2-R. For example, the first reference interior angle θ1-R, the second reference interior angle θ2-R, and the third reference interior angle θ3-R can all be 60°.

[0098] Since the distances between the respective center points MKR-C of the three adjacent reference mask patterns MKR correspond to the reference base distance LB-R, the first reference side distance LS-R1 and the second reference side distance LS-R2, which are in Fig. Since the two are shown to be essentially the same, a detailed description is omitted.

[0099] For three mask patterns MK that are adjacent to each other, from the plurality of mask patterns MK, for example, respective midpoints MK-C of two mask patterns MK that are adjacent to each other in the first lateral direction (X-direction), and a midpoint MK-C of a mask pattern MK that is adjacent to the two adjacent mask patterns MK in the second lateral direction (Y-direction), can be connected by an inequal-sided triangle.

[0100] From the majority of mask patterns MK, three adjacent mask patterns MK can be selected, each corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3, which are related to Fig. 2A can be described as corresponding to a first mask pattern MK1, a second mask pattern MK2 and a third mask pattern MK3.

[0101] Three interior angles of a triangle connecting the respective centers MK-C of the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3 can each differ from one another. Since the three interior angles of the triangle connecting the respective centers MK-C of the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3 are the first interior angle θ1, the second interior angle θ2, and the third interior angle θ3, which are related to Fig. Since the interior angles θ1, θ2, and θ3 are essentially the same as described in section 2A, a detailed description is omitted. For example, the first interior angle θ1, the second interior angle θ2, and the third interior angle θ3 may each differ from one another. The first interior angle θ1 and the second interior angle θ2 may have different values. For example, the first interior angle θ1 may be greater than 60°, and the second interior angle θ2 may be less than 60°. The third interior angle θ3 may have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0102] Distances between the respective center points MK-C of the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3 can correspond to the base distance LB, the first side distance LS1, and the second side distance LS2, which are defined in Fig. The basic distance LB shown in Figure 2A can be essentially the same. The base distance LB can be equal to the reference base distance LB-R. For example, the base distance LB can have a value of 3F. The first side distance LS1 can differ from the second side distance LS2. In some embodiments, the first side distance LS1 can be smaller than the base distance LB, and the second side distance LS2 can be larger than the base distance LB. For example, the first side distance LS1 can be less than 3F, and the second side distance LS2 can be greater than 3F.

[0103] The majority of mask patterns MK can be arranged in a line in the first lateral direction (X-direction) and in a zigzag pattern in the second lateral direction (Y-direction).

[0104] The midpoint MK-C of each of the plurality of mask patterns MK can be moved from the midpoint MKR-C of each of the plurality of reference mask patterns MKR in the first lateral direction (X-direction) or in a direction (-X-direction) opposite the first lateral direction (X-direction) away from an adjacent bit line BL.

[0105] For example, the center point MK-C of each of the mask patterns MK arranged in a row in the first lateral direction (X-direction) can be moved from the center point MKR-C of each of the reference mask patterns MKR arranged in a row in the first lateral direction (X-direction) by a first movement distance CD in the first lateral direction (X-direction). The center point MK-C of each of the mask patterns that are adjacent to each other in the second lateral direction (Y-direction) and arranged in a different line in the first lateral direction (X-direction) can be moved from the center point MKR-C of each of the reference mask patterns MKR arranged in a row in the first lateral direction (X-direction) by a second movement distance CD2 in the direction (-X-direction) opposite the first lateral direction (X-direction).In some embodiments, the first movement distance CD1 can be equal to the second movement distance CD2. For example, both the first movement distance CD1 and the second movement distance CD2 can be greater than 0 and less than 0.75 F. In some embodiments, both the first movement distance CD1 and the second movement distance CD2 can be in a range of approximately 1 nm to approximately 6 nm.

[0106] The majority of mask patterns MK can be formed using, for example, an EUV lithography process. In some embodiments, the majority of mask patterns MK can be formed without using a pattern density increase technique that includes a photolithographic process such as DPT or QPT.

[0107] Accordingly, the majority of mask patterns MK, unlike the majority of reference mask patterns MKR, which are arranged in such a way that they have a complete honeycomb shape, can be designed in such a way that they have a distorted honeycomb shape.

[0108] Referring to Fig. 9A to 9D, a plurality of landing pads 190 can be formed to fill at least sections of the plurality of landing pad holes 190H and extend over the plurality of bit line structures 140. The plurality of landing pads 190 can be positioned on the plurality of buried contacts 170 and extend over the plurality of bit line structures 140. In some embodiments, the plurality of landing pads 190 can extend over the plurality of bit lines 147. The plurality of landing pads 190 can be positioned on the plurality of buried contacts 170, and thus the plurality of buried contacts 170 can be electrically connected to the corresponding plurality of landing pads 190. The majority of landing pads 190 can be connected to the active areas 118 via the majority of buried contacts 170. The majority of landing pads 190 can be connected to the active areas 118 via the majority of buried contacts 170. Fig. The plurality of landing pads shown forms LPs.

[0109] A buried contact 170 and a landing pad 190 positioned on the buried contact 170 can together be referred to as a contact structure. The buried contact 170 contained within the contact structure can be located between two adjacent bitline structures 140. The landing pad 190 can extend from a space between the two adjacent bitline structures 140, with the buried contact 170 in between, onto a bitline structure 140. That is, the landing pad 190 can be electrically connected to the buried contact 170 and extend from the space between the two adjacent bitline structures 140, with the buried contact 170 in between, onto a bitline structure 140, vertically overlapping the other bitline structure 140.

[0110] Training on the majority of landing pads 190 can facilitate the training of those in Fig. Figures 7A to 8D show the landing pad material layer 190P forming depression units 190R using the plurality of mask patterns MK as an etching mask and separating the landing pad material layer 190P into the plurality of landing pads 190 to correspond to the plurality of buried contacts 170. The plurality of landing pads 190 can be spaced apart from each other with the depression units 190R between them. An upper end of the insulating spacer structure 150, an upper end of the insulating closure line 148, and an upper end of the insulating fence 180 can be exposed inside the depression unit 190R. In some embodiments, a section of the landing pad material layer 190P, upper sections of the plurality of insulating spacer structures 150, upper sections of the plurality of insulating closure lines 148 and upper sections of the plurality of insulating fences 180 can be removed together during the formation of the recess unit 190R.

[0111] Referring to Fig. In 10A to 10D, a plurality of lower electrodes 210, a dielectric capacitor layer 220, and an upper electrode 230 can be sequentially formed on the plurality of landing pads 190, thus forming a semiconductor storage device 1 containing a plurality of capacitor structures 200. The plurality of lower electrodes 210 can be electrically connected to the plurality of landing pads 190, each corresponding to the plurality of landing pads 190. The dielectric capacitor layer 220 can conformally cover the plurality of lower electrodes 210. The upper electrode 230 can cover the dielectric capacitor layer 220. The upper electrode 230 can be formed opposite the lower electrode 210 with the dielectric capacitor layer 220 between them.Both the dielectric capacitor layer 220 and the upper electrode 230 can be integrally formed to cover the majority of lower electrodes 210 in a predetermined area, for example in a memory cell area CR. The majority of lower electrodes 210 can be the ones in . Fig. Form the plurality of storage nodes SN shown in 1.

[0112] Each of the plurality of lower electrodes 210 can, but is not limited to, have a column shape with a filled interior to form a circular, horizontal cross-section. In some embodiments, each of the plurality of lower electrodes 210 can have a cylindrical shape with a blocked base. In some embodiments, the plurality of lower electrodes 210 can be arranged in a zigzag pattern in the first lateral direction (X-direction) or the second lateral direction (Y-direction) to form a honeycomb shape. In some other embodiments, the plurality of lower electrodes 210 can be arranged in a line in both the first lateral direction (X-direction) and the second lateral direction (Y-direction) to form a matrix shape. The plurality of lower electrodes 210 can, for example, contain doped silicon, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride.Although not shown separately, the semiconductor storage device 1 may further include at least one support pattern that contacts side walls of the majority of lower electrodes 210.

[0113] The dielectric capacitor layer 220 can contain, for example: TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O or a combination thereof.

[0114] The upper electrode 230 can, for example, contain: doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO(SrRuO), BSRO((Ba,Sr)RuO), CRO(CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TaAlN, TiSiN, TaAlN, TaSiN or a combination thereof.

[0115] Before the majority of capacitor structures 200 are formed, insulating structures 195 can be formed to fill the depression units 190R. In some embodiments, the upper surfaces of the insulating structures 195 can be coplanar with the upper surfaces of the landing pads 190 and can contact the bottom surfaces of the dielectric capacitor layer 220. In some embodiments, the insulating structures 195 can include an intermediate insulating layer and an etch stop layer. For example, the intermediate insulating layer can contain an oxide layer and the etch stop layer can contain a nitride layer. Fig. 10A and Fig.While 10C represents a case in which a top surface of the insulating structure 195 is on the same plane as a bottom surface of the lower electrode 210, the inventive concept is not limited to this. For example, the top surface of the insulating structure 195 may be on a higher plane than the bottom surface of the lower electrode 210, and the lower electrode 210 may extend into the insulating structure 195 in the direction of the substrate 110.

[0116] Since the semiconductor storage device 1, according to the present embodiment, is formed by shifting the center point of each of the plurality of landing pads 190 in a direction away from the adjacent bit line structure 140, the widths (in the first lateral direction (X-direction)) of the plurality of landing pads 190, which extend in the vertical direction (Z-direction) along the side surfaces of the adjacent bit line structure 140, can be increased. Accordingly, the overlap clearance between the corresponding landing pad 190 and the corresponding buried contact 170 can be increased, thereby improving the reliability of an electrical connection between the corresponding landing pad 190 and the corresponding buried contact 170.Furthermore, since a distance (in the first lateral direction (X-direction)) between a landing pad 190 and a buried contact 170, which is connected to another landing pad 190 adjacent to the landing pad 190, is increased, the occurrence of a bridge between the landing pad 190 and the buried contact 170, which is connected to another landing pad 190 adjacent to the landing pad 190, can be prevented.

[0117] Additionally, a surface area of ​​each of the majority of landing pads 190 can have a disc shape whose edges are not elliptical but essentially rounded. Accordingly, since the distance between the respective landing pads 190 is increased, the formation of a bridge between adjacent landing pads 190 can be prevented, and the gap-filling properties of the insulating structure 195, which fills the space between the respective landing pads 190, can be improved. Thus, the reliability of electrical insulation between the respective landing pads 190 can be improved.

Claims

[1] Semiconductor storage device (1) comprising: a plurality of bitline structures having bitlines (BL) extending in parallel in a first lateral direction on a substrate (110); a plurality of buried contacts (BC) and a plurality of landing pads (LP), wherein the plurality of buried contacts (BC) fill lower sections of spaces between the plurality of bitline structures on the substrate (110), wherein the plurality of landing pads (LP) fill upper sections of the spaces between the plurality of bitline structures and extend onto the plurality of bitline structures, wherein the majority of landing pads (LP) have a hexagonal array structure and the centers of the respective top surfaces of a first landing pad (LP1), a second landing pad (LP2) and a third landing pad (LP3), which are adjacent to each other from the majority of landing pads (LP), are connected by an inequal-sided triangle; and a plurality of storage nodes (SN) on the plurality of landing pads (LP), wherein the plurality of storage nodes (SN) has a hexagonal array structure and the centers of the respective top faces of a first storage node, a second storage node and a third storage node, which are adjacent to each other from the plurality of storage nodes (SN), are connected by an equilateral triangle. [2] Semiconductor storage device (1) according to claim 1, wherein the plurality of landing pads (LP) are arranged in a line in a second lateral direction perpendicular to the first lateral direction and are arranged in a zigzag pattern in the first lateral direction. [3] Semiconductor storage device (1) according to claim 1, wherein the first landing pad (LP1) and the second landing pad (LP2) are arranged in a second lateral direction perpendicular to the first lateral direction, wherein a first interior angle (θ1) between two sides connecting the center of the top surface of the first landing pad (LP1) with the center of the top surface of the second landing pad (LP2) and the center of the top surface of the third landing pad (LP3) differs from a second interior angle (θ2) between two sides connecting the center of the top surface of the second landing pad (L2P) with the center of the top surface of the first landing pad (LP1) and the center of the top surface of the third landing pad (LP3). [4] Semiconductor storage device (1) according to claim 3, wherein the first internal angle (θ1) is greater than 60° and the second internal angle (θ2) is less than 60°. [5] Semiconductor storage device according to claim 1, wherein the center point of the top surface of the third landing pad (LP3) is positioned away from a mean extension line (HVL) in a second lateral direction perpendicular to the first lateral direction, and wherein the mean extension line (HVL) extends in the first lateral direction from a midpoint of a side which connects the midpoints of the respective top surfaces of the first landing pad (LP1) and the second landing pad (LP2). [6] Semiconductor storage device (1) according to claim 5, wherein the distance between the centers of the respective top surfaces of the first landing pad (LP1) and the second landing pad (LP2) is 3F and the center of the top surface of the third landing pad (LP3) is positioned by a distance greater than 0 and less than 1.5F from the mean extension line (HVL) in the second lateral direction, and where F is a structure size. [7] Semiconductor storage device (1) according to claim 5, wherein the center point of the cover surface of the third landing pad (LP3) is positioned by a distance of 2 nm to 12 nm in the second lateral direction from the central extension line (HVL). [8] Semiconductor storage device (1) according to claim 5, wherein a distance between the centers of the respective cover surfaces of the first landing pad (LP1) and the third landing pad (LP3) is less than 3F and a distance between the centers of the respective cover surfaces of the second landing pad (LP2) and the third landing pad (LP3) is greater than 3F. [9] Semiconductor storage device (1) according to claim 1, wherein a cover surface of each of the plurality of landing pads (LP) has a disk shape. [10] Semiconductor storage device (1) comprising: a substrate (110) in which a plurality of active regions (ACT) are defined; a plurality of word lines (WL) that overlap with the plurality of active areas (ACT) and extend parallel in a second lateral direction; a plurality of bitline structures having bitlines (BL) on the substrate (110), wherein the bitlines (BL) extend parallel in a first lateral direction perpendicular to the second lateral direction; a plurality of buried contacts (BC) and a plurality of landing pads (LP), wherein the plurality of buried contacts (BC) fill lower sections of spaces between the plurality of bitline structures on the substrate (110), and wherein the plurality of landing pads (LP) fill upper sections of the spaces between the plurality of bitline structures and extends to the majority of bitline structures; and a plurality of storage nodes (SN) on the plurality of landing pads (LP), wherein the majority of landing pads (LP) have a hexagonal array structure and the centers of respective cover surfaces of three adjacent landing pads (LP1 - LP3) from the majority of landing pads (LP) are connected by an inequal-sided triangle, and wherein the majority of storage nodes (SN) have a hexagonal array structure and the centers of the respective cover surfaces of three adjacent storage nodes (SN) from the majority of storage nodes (SN) are connected by an equilateral triangle. [11] Semiconductor storage device (1) according to claim 10, wherein the majority of landing pads (LP) are arranged in a line in the second lateral direction and in a zigzag pattern in the first lateral direction, and wherein the majority of storage nodes (SN) are arranged in a line in the second lateral direction and in a zigzag pattern in the first lateral direction. [12] Semiconductor storage device (1) according to claim 10, wherein a cover surface of each of the plurality of landing pads (LP) has rounded edges. [13] Semiconductor storage device (1) according to claim 10, wherein the distances between the centers of respective cover surfaces of three adjacent storage nodes (SN) of the plurality of storage nodes (SN) have the same value of a reference distance. [14] Semiconductor storage device (1) according to claim 13, wherein a length of a first side of three sides of a triangle that is the center point of the respective top surfaces of the three adjacent landing pads (LP1) - LP3) connects the majority of landing pads (LP), is equal to the reference distance, and wherein a second side and a third side of the three sides of the triangle each have a length that is smaller than the reference distance and a length that is larger than the reference distance. [15] Semiconductor storage device (1) comprising: a substrate (110) in which a plurality of active areas (ACT) are defined by a device isolation layer (116); a plurality of word lines (WL) that overlap with the plurality of active areas (ACT) and extend parallel in a second lateral direction; a plurality of bitline structures positioned on the substrate (110), where the majority of bit line structures extend parallel in a first lateral direction perpendicular to the second lateral direction; a plurality of buried contacts (BC) that fill lower sections of spaces between the plurality of bitline structures on the substrate (110), wherein the plurality of buried contacts (BC) are connected to the plurality of active areas (ACT); a plurality of landing pads (LP) connected to the plurality of buried contacts, wherein the plurality of landing pads (LP) fill upper sections of the spaces between the plurality of bitline structures and extends over the majority of bitline structures, with one cover surface of each of the majority of landing pads (LP) having a disk shape; and a plurality of memory nodes (SN) positioned on the plurality of bitline structures and connected to the plurality of landing pads (LP), wherein a first, second and third side of a triangle connecting the centers of respective top surfaces of three adjacent landing pads (LP1 - LP3) from the plurality of landing pads (LP) each have a length of 3F, a length of less than 3F and a length of more than 3F respectively, where F is a structure size, and Each of the first, second and third sides of a triangle connecting the centers of the respective top surfaces of three adjacent storage nodes (SN) from the plurality of storage nodes (SN) has a length of 3F. [16] Semiconductor storage device (1) according to claim 15, wherein the plurality of landing pads (LP) are arranged in a line in the second lateral direction and in a zigzag pattern in a first lateral direction perpendicular to the second lateral direction to form a hexagonal array structure, and the plurality of storage nodes (SN) are arranged in a line in the second lateral direction and in a zigzag pattern in the first lateral direction to form a hexagonal array structure. [17] Semiconductor storage device (1) according to claim 16, wherein a central extent line (HVL) extends in the first lateral direction from a center of a side, which connects the centers of respective cover surfaces of a first (LP1) and second landing pad (LP2) positioned adjacent to each other in the second lateral direction, from three adjacent landing pads (LP1 - LP3) of the plurality of landing pads (LP) to a center of a cover surface of a third landing pad (LP3) positioned remotely from the central extent line (HVL) in the second lateral direction. [18] Semiconductor storage device (1) according to claim 17, wherein the center point of the cover surface of the third landing pad (LP3) is positioned from the central extent line (HVL) by a distance which is less than half a distance between the centers of respective cover surfaces of a first (LP1) and second landing pad (LP2) which are adjacent to each other in the second lateral direction, from the three adjacent landing pads (LP1 - LP3) of the plurality of landing pads (LP). [19] Semiconductor storage device (1) according to claim 17, wherein the center point of the cover surface of the third landing pad (LP3) is positioned by a distance of 2 nm to 12 nm in the first lateral direction away from the central extension line (HVL).

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