Semiconductor device

Abstract

Semiconductor device (100, 101), exhibiting: - a semiconductor substrate of a first conductivity type, which exhibits: - a first main surface and a second main surface opposite the first main surface, - an IGBT region (10), - a diode region (20), and - a border region (50) located between the IGBT region (10) and the diode region (20), which are provided along a first direction within the plane of the semiconductor substrate; - an emitter electrode (6) which is provided on the first main surface of the semiconductor substrate; and - a collector electrode (7) which is provided on the second main surface of the semiconductor substrate, the semiconductor substrate has: - a first anode layer (25) of a second conductivity type and a first contact layer (24) of the second conductivity type with a higher concentration of defects of the second conductivity type than the first anode layer (25), which are provided on a first main surface face, which is one side of the first main surface, in the diode region (20); - a cathode layer (26) of the first conductivity type, which is provided on a second main surface side, which is one side of the second main surface, in the diode region (20); - a first charge carrier dissipation layer (27) of the second conductivity type, which is provided next to the cathode layer (26) in the first direction within the plane of the second main surface face in the diode region (20); - a second anode layer (55) of the second conductivity type and a second contact layer (54) of the second conductivity type with a higher concentration of defects of the second conductivity type than the second anode layer (55), which are provided on the first main surface face in the boundary region (50); and - a collector layer (56) of the second conductivity type, which is provided on the second main surface side in the boundary region (50), and wherein a concentration of defects of the second conductivity type of the second anode layer (55) is lower than a concentration of defects of the second conductivity type of the first anode layer (25).

Description

Background of the invention; Field of the invention

[0001] The present invention relates to a semiconductor device. Description of the state of the art

[0002] Power semiconductor devices, which are a type of semiconductor device, are used in a wide range of fields, including household appliances, automobiles, and railways. In these fields, an inverter circuit, which consists of a power device, often drives an inductive load such as an induction motor. Inverter devices for these applications are designed to use power semiconductor devices such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), and freewheeling diodes (hereafter referred to simply as "diodes").

[0003] Inverter devices require high efficiency and low power consumption, so the market demands a power semiconductor device that offers high efficiency at low cost. To meet these requirements, reverse-conducting IGBTs (RC-IGBTs) were developed. RC-IGBTs are formed by integrating an IGBT and a diode onto the same semiconductor substrate, resulting in a reduction of the component area, the number of components, the component mounting area, and thermal resistance (e.g., Japanese patent application JP 2008-053 648 A).

[0004] The RC-IGBTs each contain the IGBT and the diode, each represented by an IGBT region and a diode region, respectively. A recovery process occurs in the diode region when the diode switches from an on-state to an off-state. As the diode switches from on-state to off-state, electron and hole charge carriers accumulated in the RC-IGBT during the on-state are discharged, resulting in a recovery process in which a reverse current flows from one cathode side to one anode side. The reverse current flowing during the recovery process is called the recovery current, and the power loss that occurs corresponding to a specific value of the recovery current, an applied voltage, and a certain duration of current flow is called the recovery loss.

[0005] To achieve low recovery loss, it is generally necessary to reduce the recovery current by minimizing charge carriers that accumulate in the diode during the on-state. One possible configuration is to provide a p-type hole drain region in a portion of a back-side area within the diode region. This facilitates the draining of hole charge carriers from the back-side area during forward operation, thereby reducing charge carrier accumulation. However, even with the p-type hole drain region, a problem arises: the recovery loss cannot be effectively reduced if there is a significant influx of holes from the adjacent IGBT region to the diode region.

[0006] US patent 2019 / 0252534A1 discloses a semiconductor device in which an interface is located between an IGBT region and a diode region. In other words, the interface is located adjacent to the diode region. The interface exhibits a lower high-concentration P-type layer formation rate than the IGBT region. Consequently, hole injection from the IGBT region into the diode region can be prevented during recovery. The reduced high-concentration P-type layer formation rate in the interface also reduces the amount of hole injection from the interface's high-concentration P-type layer.This prevents an increase in the maximum reverse current during recovery and also reduces the carrier density on the cathode side to prevent an increase in the residual current, thus reducing switching losses and making the semiconductor device highly resistant to damage during recovery.

[0007] German patent application DE 10 2011 086 854 A1 describes a semiconductor device comprising a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region with an IGBT region and a diode region adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of a first conductivity type is located on the first surface surrounding the element region. An anode region of the first conductivity type is located on the second surface surrounding the element region. A third semiconductor region of the second conductivity type is located on the second surface surrounding the element region. Summary

[0008] The present disclosure was implemented in consideration of the aforementioned problems, and it is a purpose of the present disclosure to provide a technique capable of effectively reducing recovery loss.

[0009] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0010] A semiconductor device according to the present disclosure comprises: a semiconductor substrate of a first conductivity type, which has a first principal surface and a second principal surface opposite the first principal surface, an IGBT region, a diode region, and a boundary region between the IGBT region and the diode region, which is provided along a first direction within the plane in the semiconductor; an emitter electrode which is provided on the first principal surface of the semiconductor substrate;and a collector electrode, which is provided on the second main surface of the semiconductor substrate. The semiconductor substrate comprises: a first anode layer of a second conductivity type and a first contact layer of the second conductivity type, which has a higher concentration of impurities of the second conductivity type than the first anode layer, which are provided on a first main surface face, which is one side of the first main surface face, in the diode region; a cathode layer of the first conductivity type, which is provided on a second main surface face, which is one side of the second main surface, in the diode region; a first charge carrier dissipation layer of the second conductivity type, which is provided next to the cathode layer in the first direction within the plane of the second main surface face in the diode region;A second anode layer of the second conductivity type and a second contact layer of the second conductivity type, which has a higher concentration of defects of the second conductivity type than the second anode layer provided on the first main surface in the boundary region; and a collector layer of the second conductivity type, which is provided on the second main surface in the boundary region. The concentration of defects of the second conductivity type in the second anode layer is lower than the concentration of defects of the second conductivity type in the first anode layer.

[0011] This allows for an effective reduction in recovery loss.

[0012] These and other tasks, features, aspects and advantages of the present revelation will become clearer based on the following detailed description of the present revelation in conjunction with the accompanying figures. Brief description of the characters Fig. 1 is a top view illustrating the structure of a semiconductor device according to a first preferred embodiment; Fig. 2 is a top view illustrating a further structure of the semiconductor device according to the first preferred embodiment; Fig. Figure 3 is a partially enlarged top view illustrating the structure of an IGBT region of the semiconductor device according to the first preferred embodiment; Fig. 4 and Fig. Figures 5 are each a sectional view illustrating a structure of the IGBT region of the semiconductor device according to the first preferred embodiment; Fig. 6 is a partially enlarged top view illustrating the structure of a diode region of the semiconductor device according to the first preferred embodiment; Fig. 7 and Fig. Figures 8 are each a sectional view illustrating a structure of the diode region of the semiconductor device according to the first preferred embodiment; Fig. 9 and Fig. Figure 10 are each a partially enlarged top view illustrating a structure of a boundary region between the IGBT region and the diode region of the semiconductor device according to the first preferred embodiment; Fig. 11 and Fig. 12 are each a sectional view illustrating a structure of a termination region of the semiconductor device according to the first preferred embodiment; Fig. Figures 13A to 20B are each a sectional view illustrating a method for manufacturing the semiconductor device according to the first preferred embodiment; Fig. Figure 21 is a partially enlarged top view illustrating the structure of a boundary region between an IGBT region and a diode region of a semiconductor device to explain the technical background of the present invention; Fig. Figure 22 is a sectional view illustrating the structure of a boundary region between an IGBT region and a diode region of a semiconductor device according to a third preferred embodiment; Fig. 23 is a diagram illustrating a simulation result of the semiconductor device according to the third preferred embodiment; Fig. 24 is a diagram illustrating a simulation result of a semiconductor device according to a fourth preferred embodiment; Fig. Figures 25A to 25C are each a partially enlarged top view illustrating a structure in a diode region of a semiconductor device according to a fifth preferred embodiment; Fig. Figure 26 is a diagram illustrating a simulation result of a semiconductor device according to a sixth preferred embodiment; and Fig. Figure 27 is a partially enlarged top view illustrating the structure of a boundary region between an IGBT region and a diode region of a semiconductor device according to a seventh preferred embodiment. Description of preferred embodiments

[0013] Preferred embodiments are described below with reference to the accompanying figures. Features described in each of the following preferred embodiments are exemplary, and not all features are necessarily required. In the following description, similar components are identified by identical or similar reference numerals in the multitude of preferred embodiments, and predominantly different components are described. The description below shows specific positions and directions such as "top," "bottom," "left," "right," "front," and "back," which are not necessarily identical to directions at the time of actual implementation.A part with a higher concentration than another part means, for example, that the average concentration of one part is higher than the average concentration of the other part, or that the maximum concentration of one part is higher than the maximum concentration of the other part.

[0014] The following description shows n and p, each indicating a conductivity type of a semiconductor. Although the present disclosure is described such that a first conductivity type is designated as the n-type and a second conductivity type is designated as the p-type, the first conductivity type can be referred to as the p-type and the second conductivity type as the n-type. An impurity concentration less than n is referred to as n - specified, and a defect concentration higher than n is referred to as n +Similarly, an impurity concentration lower than p is referred to as p. - specified, and an impurity concentration higher than p, than p + specified. <Erste bevorzugte Ausführungsform>

[0015] Fig. Figure 1 is a top view illustrating the structure of a semiconductor device that is an RC-IGBT according to a first preferred embodiment. Fig. Figure 2 is a top view illustrating a further structure of the semiconductor device, which is the RC-IGBT according to the first preferred embodiment. Fig. Figure 1 illustrates a semiconductor device 100 which contains an IGBT region 10 and a diode region 20 which are arranged side by side in a strip shape and which can be referred to in the following description for simplicity as a “strip type”. Fig. Figure 2 illustrates a semiconductor device 101 which has several diode regions 20 provided in a vertical direction and a horizontal direction, and an IGBT region 10 which is provided around the diode regions 20, and which can be simplified to be called an “island type” in the following description. <Gesamte Ebenenstruktur des Streifentyps>

[0016] In Fig. Figure 1 of the semiconductor device 100 comprises the IGBT region 10 and the diode region 20. Both the IGBT 10 and the diode region 20 extend from one end face to the other end face of the semiconductor device 100 and are arranged alternately in a strip shape in a direction orthogonal to the respective extension direction of the IGBT region 10 and the diode region 20. Fig. Figure 1 illustrates three IGBT regions 10 and two diode regions 20, and a structure in which all diode regions 20 are inserted between the corresponding IGBT regions 10. The number of IGBT regions 10 and diode regions 20 is not limited to these; the number of IGBT regions 10 can be three or more, or three or fewer, and the number of diode regions 20 can be two or more, or two or fewer. Locations of the IGBT regions 10 and diode regions 20 in Fig. The IGBT regions 10 can be swapped, and all IGBT regions 10 can be inserted between the corresponding diode regions 20. Furthermore, the IGBT regions 10 and the diode regions 20 can be provided side-by-side, one after the other.

[0017] As in Fig. As illustrated in Figure 1, a pad region 40 is provided adjacent to the IGBT region 10 on a lower side of the figure. Pad region 40 is provided with a control pad 41 for controlling the semiconductor device 100. In the following description, the IGBT region 10 and the diode region 20 can be collectively referred to as a cell region. A termination region 30 is provided around a region containing the cell region and pad region 40 to withstand a voltage surge on the semiconductor device 100. The termination region 30 can be appropriately provided by means of a well-known voltage surge-holding structure.The voltage-holding structure can be configured such that, for example, a field-limiting ring (FLR), in which a cell region is surrounded by a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD), in which a cell region is surrounded by a p-type well layer with a concentration gradient, is provided on the first main surface, i.e., one side of a front surface of the semiconductor device 100. The number of p-type termination well layers in the form of a ring, which are used for the FLR, and a concentration distribution, which is used for the VLD, can be selected appropriately depending on a voltage-holding design of the semiconductor device 100. The p-type termination well layer can be provided over approximately the entire pad region 40, and the pad region 40 can be provided with an IGBT cell or a diode cell.

[0018] The control pad 41 includes, for example, a current sensing pad 41a and / or a Kelvin emitter pad 41b and / or a gate pad 41c and / or temperature sensing diode pads 41d, 41e.

[0019] The current sensing pad 41a is a control pad for detecting a current flowing through the cell region of the semiconductor device 100. The current sensing pad 41a is electrically connected to the cell to allow a current to flow through the cell region of the semiconductor device 100, so that a current of a fraction to a fraction of several tens of thousands, which flows through the entire cell region, flows through a part of the IGBT cell or the diode cell in the cell region.

[0020] The Kelvin emitter pad 41b and the gate pad 41c are each control pads to which a gate driver voltage is applied for switching the semiconductor device 100 on and off. The Kelvin emitter pad 41b is electrically connected to a p-type base layer of the IGBT cell. The gate pad 41c is electrically connected to a gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can be electrically connected, with a p +A contact layer of a type is inserted between the two layers. The temperature sensing diode pads 41d and 41e are control pads that are electrically connected to an anode and a cathode of the temperature sensing diode provided in the semiconductor device 100. A voltage between the anode and the cathode of the temperature sensing diode (not shown), which is provided in the cell region, is measured by the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on this voltage. <Gesamte Ebenenstruktur des Inseltyps>

[0021] In Fig. Figure 2 shows that the semiconductor device 101 comprises the IGBT region 10 and the diode region 20 within a single semiconductor device. Several diode regions 20 are arranged side by side in both the vertical and horizontal directions of the semiconductor device 101, and the periphery of each diode region 20 is surrounded by the IGBT region 10. That is, the multiple diode regions 20 are provided in an island configuration within the IGBT region 10. Fig. Figure 2 illustrates a structure in which the diode region 20 is provided in a matrix with four columns in a left-right direction and two rows in the vertical direction. However, the number and placement of the diode regions 20 are not limited to this. One or more diode regions 20 can be distributed within the IGBT region 10, as long as the periphery of each of the diode regions 20 is surrounded by the IGBT region 10.

[0022] As in Fig. As illustrated in Figure 2, pad region 40 is located adjacent to the lower side of IGBT region 10. Pad region 40 is a region in which the control pad 41 for controlling the semiconductor device 101 is provided. Even in this description, IGBT region 10 and diode region 20 are collectively referred to as the cell region. Termination region 30 is provided around a region containing the cell region and pad region 40 to withstand a voltage surge on the semiconductor device 101. Termination region 30 can be appropriately provided by a well-known voltage surge protection structure.The stress-holding structure can, for example, be designed such that an FLR, in which a region comprising the cell region and the pad region 40 is surrounded by a p-type end-trough layer of a p-type semiconductor, or that a VLD, in which the cell region is surrounded by a p-type trough layer with a concentration gradient, is provided on the first main surface side, i.e., a side of a front surface, with an FLR in which a region comprising the cell region and the pad region 40 is surrounded by a p-type end-trough layer of a p-type semiconductor, or with a VLD in which the cell region is surrounded by a p-type trough layer with a concentration gradient.The number of p-type termination well layers in the form of a ring, which are used for the FLR, and a concentration distribution, which is used for the VLD, can be selected appropriately depending on a withstand voltage design of the semiconductor device 101. The p-type termination well layer can be provided over approximately the entire pad region 40, and the pad region 40 can be provided with an IGBT cell or a diode cell.

[0023] The control pad 41 includes, for example, a current sensing pad 41a and / or a Kelvin emitter pad 41b and / or a gate pad 41c and / or temperature sensing diode pads 41d, 41e.

[0024] The current sensing pad 41a is a control pad for detecting a current flowing through the cell region of the semiconductor device 101. The current sensing pad 41a is electrically connected to the cell to allow a current to flow through the cell region of the semiconductor device 101, so that a current of a fraction to a fraction of several tens of thousands, which flows through the entire cell region, flows through a portion of the IGBT cell or diode cell in the cell region.

[0025] The Kelvin emitter pad 41b and the gate pad 41c are each control pads to which a gate driver voltage is applied to control the semiconductor device 101 on / off. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and an n + -Type emitter layer of the IGBT cell connected. The n + -Type emitter layer can n +The -type source layer is called the gate pad 41c. The gate pad 41c is electrically connected to a gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can be electrically connected, with a p + A contact layer of a type is inserted between the two layers. The temperature sensing diode pads 41d and 41e are control pads that are electrically connected to an anode and a cathode of the temperature sensing diode provided in the semiconductor device 101. A voltage between the anode and the cathode of the temperature sensing diode (not shown), which is provided in the cell region, is measured by the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 101 is measured based on this voltage. <IGBT-Region 10>

[0026] Fig. Figure 3 is a partially enlarged top view illustrating the structure of IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, Fig. 3 an enlarged view of a region, which is defined by a dashed line 82 in the Fig. 1 illustrated semiconductor device 100 or in the in Fig. 2 illustrated semiconductor device 101 is surrounded.

[0027] The Fig. 4 and Fig. Figure 5 is a sectional view illustrating the structure of IGBT region 10 of the semiconductor device, which is an RC-IGBT. Specifically, Fig. 4 a sectional view taken along a dotted-and-dashed line AA of the semiconductor device 100, 101, which is in Fig. 3 is illustrated, and Fig. Figure 5 is a sectional view taken along the dotted-and-dashed line BB of the semiconductor device 100, 101, which is shown in Fig. Figure 3 illustrates this.

[0028] As in Fig. As illustrated in Figure 3, the IGBT region 10 has an active trench gate 11 and a dummy trench gate 12, each provided in a strip form. The semiconductor device 100 is configured such that the active trench gate 11 and the dummy trench gate 12 extend in a longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to a longitudinal direction of the active trench gate 11 and the dummy trench gate 12, respectively. In contrast, the semiconductor device 101 is configured such that a longitudinal direction and a transverse direction in the IGBT region 10 are not specifically distinguished, and a left-right direction in the figure can correspond to the longitudinal direction of the active trench gate 11 and the dummy trench gate 12, or a vertical direction in the figure can correspond to the longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0029] The active trench gate 11 is formed by a gate trench electrode 11a, which is provided in a trench of a semiconductor substrate via a gate trench insulating layer 11b. The dummy trench gate 12 is formed by a dummy trench electrode 12a, which is provided in a trench of the semiconductor substrate via a dummy trench insulating layer 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode, which is provided on the first main surface of the semiconductor device 100, 101.

[0030] A + -Type emitter layer 13 is in contact with the gate trench insulation layer 11b on each side of the active trench gate 11 in its lateral direction. The n +-Type emitter layer 13 is a semiconductor layer which, for example, has arsenic or phosphorus as n-type defects, and the n-type defects have, for example, a concentration of 1.0E + 17 / cm². 3 up to 1.0E + 20 / cm 3 up. The n + -Type emitter layer 13 alternates with a p + -Type contact layer 14 is provided along one extension direction of the active trench gate 11. The p + Type contact layer 14 is provided between two adjacent dummy trench gates 12 in contact with the dummy trench insulating layer 12b. The p + -Type contact layer 14 is a semiconductor layer which, for example, has boron or aluminum as p-type defects, and the p-type defects have, for example, a concentration of 1.0E + 15 / cm². 3 up to 1.0E + 20 / cm 3 on.

[0031] As in Fig. As illustrated in Figure 3, in the IGBT region 10 of the semiconductor device 100, 101, three dummy trench gates 12 are arranged side by side adjacent to three active trench gates 11, which are arranged side by side. Furthermore, next to the three dummy trench gates 12, which are arranged side by side, three active trench gates 11 are arranged side by side, which differ from those above. As described above, the IGBT region 10 has a structure in which a set of active trench gates 11 and a set of dummy trench gates 12 are arranged alternately. Although in Fig. Since the number of active trench gates 11 contained in a set of active trench gates 11 is fixed at three, it can be one or more. The number of dummy trench gates 12 contained in a set of dummy trench gates 12 can be one or more, and the number of dummy trench gates 12 can be zero. That is, all trench gates provided in IGBT region 10 can be active trench gates 11.

[0032] Fig. Figure 4 is a sectional view of the semiconductor device 100, 101, which is shown along the dotted-and-dashed line AA in Fig. Figure 3 is taken from the diagram and is a sectional view of IGBT region 10. The semiconductor device 100, 101 has an n - -Type drift layer 1, which is formed from a semiconductor substrate. The n --Type drift layer 1 is a semiconductor layer which, for example, has arsenic or phosphorus as n-type defects, and the n-type defects have a concentration of, for example, 1.0E + 12 / cm². 3 up to 1.0E + 15 / cm 3 on. The concentration of n-type defects in the n + The concentration of -type emitter layer 13, described above, is higher than the concentration of n-type defects in the n - -Type Drift Layer 1.

[0033] In Fig. 4 the semiconductor substrate extends from the n + -Type emitter layer 13 and the p + -Type contact layer 14 up to a p-type collector layer 16. In Fig. 4 will form an upper end of the n + -Type emitter layer 13 and the p +The p-type contact layer 14 in the figure is designated as the first principal surface, which is the side of the first principal surface of the semiconductor substrate, and a lower end of the p-type collector layer 16 in the figure is designated as the second principal surface, which is the side of the second principal surface of the semiconductor substrate. The first principal surface of the semiconductor substrate is the first principal surface on one side of a front surface of the semiconductor device 100, 101, and the second principal surface of the semiconductor substrate is the principal surface on one side of a rear surface of the semiconductor device 100, 101. The semiconductor device 100, 101 has the n -A drift layer of type 1 is located between the first main surface and the second main surface, which faces the first main surface, in IGBT region 10 of the cell region. The semiconductor substrate can be structured such that it includes, for example, a wafer and / or an epitaxial growth layer. The semiconductor substrate can be a wide-bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), diamond) capable of stable operation at high temperatures.

[0034] Although not illustrated, IGBT region 10 may include an n-type charge carrier storage layer located on the first principal face of the n - -Type drift layer 1 is provided, and which has a higher concentration of n-type defects than the n --Type drift layer 1. The provision of the n-type charge carrier storage layer enables a reduction in electrical power loss when a current flows in IGBT region 10. The n-type charge carrier storage layer and the n - The n-type drift layer can be collectively referred to as the drift layer. The n-type charge carrier storage layer is formed by injecting n-type impurities into the semiconductor substrate, which contains the n - -type drift layer 1 is formed, and subsequently n-type impurities in the semiconductor substrate, which the n - -Type Drift Layer 1 is distributed through a heat treatment.

[0035] A p-type base layer 15 is located on the first main surface face of the n -The n-type drift layer 1 is provided. In the structure where the n-type charge carrier storage layer is provided, the p-type base layer 15 is provided on the first main face of the n-type charge carrier storage layer. The p-type base layer 15 is, for example, a semiconductor layer which has boron or aluminum as p-type defects, and the p-type defects have a concentration of, for example, 1.0 E + 12 / cm². 3 up to 1.0E + 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating layer 11b of the active trench gate 11. In the example of Fig. 4 the p-type base layer 15 is also in contact with the dummy trench insulating layer 12b of the dummy trench gate 12.

[0036] The n +-Type emitter layer 13, which is in contact with the gate trench insulating layer 11b of the active trench gate 11, is provided in part of a region on the first main surface side of the p-type base layer 15, and the p + The p-type contact layer 14 is selectively provided in the other region of the first main surface face of the p-type base layer 15. The n + -Type emitter layer 13 and the p + The -type contact layer 14 forms the first main surface of the semiconductor substrate. The p + The p-type contact layer 14 is a region that exhibits a higher concentration of p-type defects than the p-type base layer 15. If it is necessary to remove the p-type defects, the p-type contact layer 14 will be removed. + To distinguish between the -type contact layer 14 and the p-type base layer 15, they can be designated individually. Alternatively, the p + The -type contact layer 14 and the p-type base layer 15 are jointly referred to as a p-type base layer. The p +-Type contact layer 14 and the n + -Type emitter layer 13 are connected to an emitter electrode 6 via a barrier metal 5.

[0037] In the semiconductor device 100, 101 there is an n-type buffer layer 3 which has a higher concentration of n-type defects than the n - -Type Drift layer 1, on the second main surface side of the n - The n-type drift layer 1 is provided. The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 towards the second main surface face from propagating when the semiconductor device 100, 101 is switched off. The n-type buffer layer 3 can be formed by, for example, phosphorus (P) or a proton (H). + ) is injected, or it can be formed by injecting both phosphorus (P) and a proton (H). +) are injected. The n-type buffer layer 3 contains n-type defects, which, for example, have a concentration of 1.0 E + 12 / cm². 3 up to 1.0E + 18 / cm 3 exhibit. The semiconductor device 100, 101 can be constructed such that the n-type buffer layer 3 is not provided and that the n - -Type drift layer 1 is provided in a region of the n-type buffer layer 3, which is in Fig. Figure 4 illustrates the n-type buffer layer 3 and the n - -Type Drift Layer 1 can be collectively referred to as Drift Layer.

[0038] In the semiconductor device 100, 101, the p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. That is, the p-type collector layer 16 is located between the n - -Type drift layer 1 and the second main surface are provided. The p-type collector layer 16 can be described as p +The p-type collector layer is a semiconductor layer that contains, for example, boron or aluminum as p-type defects, and the p-type defects have a concentration of, for example, 1.0 E + 16 / cm². 3 up to 1.0E + 20 / cm 3 The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 can be located not only in the IGBT region 10 but also in the termination region 30. The p-type collector layer 16 is connected to a collector electrode 7.

[0039] As in Fig. As illustrated in Figure 4, the IGBT region 10 of the semiconductor device 100, 101 is provided with a trench which passes through the p-type base layer 15 from the first main surface of the semiconductor substrate and the n --Type drift layer 1 is reached. The active trench gate 11 is constructed from the gate trench electrode 11a, which is provided in some trenches via the gate trench insulating layer 11b. The gate trench electrode 11a is the n - -Type drift layer 1 facing, with the gate trench insulating layer 11b inserted between them. The dummy trench gate 12 is constructed from the dummy trench electrode 12a, which is provided in some trenches via the dummy trench insulating layer 12b. The dummy trench electrode 12a is the n - -Type Drift layer 1 facing, with the dummy trench insulation layer 12b inserted in between.

[0040] The gate trench insulation layer 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n +-Type emitter layer 13. When a gate driver voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15, which is in contact with the gate trench insulating layer 11b of the active trench gate 11.

[0041] As in Fig. As illustrated in Figure 4, an intermediate insulating layer 4 is provided on the gate-trench electrode 11a of the active trench gate 11. The barrier metal 5, which is capable of reducing contact resistance, is provided in a region where the intermediate insulating layer 4 is not provided on the first main surface of the semiconductor substrate and on the intermediate insulating layer 4. The barrier metal 5 can, for example, be a conductor containing titanium (Ti), specifically titanium nitride, or TiSi, which is obtained by alloying titanium and silicon (Si). The barrier metal 5 can be formed by silicideation. As shown in Fig. As illustrated in Figure 4, the barrier metal 5 is in ohmic contact with the n + -Type emitter layer 13, the p + -Type contact layer 14, and the dummy trench electrode 12a, and is electrically connected to the n + -Type emitter layer 13, the p + -Type contact layer 14 and the dummy trench electrode 12a are connected. Furthermore, the barrier metal 5 is electrically insulated from the gate trench electrode 11a by the intermediate insulating layer 4.

[0042] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can, for example, be made of an aluminum alloy such as an aluminum-silicon alloy (Al-Si-based alloy) and can be composed of several layers of metal, in which plating layers are formed on an electrode made of the aluminum alloy by electroless plating or electrolytic plating. The plating layers formed by electroless plating or electrolytic plating can, for example, each be a nickel (Ni) plating layer.If a thin region exists, such as between adjacent intermediate insulating layers 4, in which good embedding with the emitter electrode 6 cannot be achieved, a tungsten layer, which has better embedding properties than the emitter electrode 6, can be arranged in the thin region to provide the emitter electrode 6 on the tungsten layer. The emitter electrode 6 can be placed on the n. + -Type emitter layer 13, the p + -type contact layer 14, and the dummy trench electrode 12a are provided without providing the barrier metal 5. The barrier metal 5 can only be provided on an n-type semiconductor layer such as the n + -Type emitter layer 13 is provided. The barrier metal 5 and the emitter electrode 6 can be collectively referred to as the emitter electrode. As described above, the emitter electrode 6 can be provided on the first main surface of the semiconductor substrate.

[0043] Although Fig. Figure 4 illustrates a structure in which the intermediate insulating layer 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12. The intermediate insulating layer 4 can be placed on the dummy trench electrode 12a of the dummy trench gate 12 in a section of Fig. 4 be provided. If the intermediate insulating layer 4 is on the dummy trench electrode 12a of the dummy trench gate 12 in the sub-area of Fig. 4 is provided, the emitter electrode 6 and the dummy trench electrode 12a can be electrically connected in another sub-area.

[0044] A collector electrode 7 is provided on the second main face of the p-type collector layer 16. As with the emitter electrode 6, the collector electrode 7 can be made of an aluminum alloy or multiple layers of an aluminum alloy with a plating layer. The collector electrode 7 can have a different structure than the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to it. As described above, the collector electrode 7 can be provided on the second main face of the semiconductor substrate.

[0045] Fig. Figure 5 is a sectional view of the semiconductor device 100, 101, which is shown along the dotted-and-dashed line BB in Fig. Figure 3 is taken from the diagram and is a cross-sectional view of IGBT region 10. Unlike the sub-area that runs along the line in Fig. The section shown in the dotted and dashed line AA, as illustrated in Figure 4, contains the sub-area that follows the dotted and dashed line BB in Figure 4. Fig. 5 is taken from, not the n + -Type emitter layer 13, which is in contact with the active trench gate 11 and is provided on the first main face of the semiconductor substrate. That is, the one in Fig. 3 illustrated n + The p-type emitter layer 13 is selectively provided on the first main surface face of the p-type base layer. The p-type base layer referred to here includes the p-type base layer 15 and the p + -Type contact layer 14. <Diodenregion 20>

[0046] Fig. Figure 6 is a partially enlarged top view illustrating the structure of diode region 20 of the semiconductor device, which is an RC-IGBT. Specifically, Fig. 6 an enlarged view of a region surrounded by a dashed line 83 in the semiconductor device 100, 101, which is in Fig. 1 is illustrated.

[0047] The Fig. 7 and Fig. Figure 8 is a sectional view illustrating the structure of the diode region 20 of the semiconductor device, which is an RC-IGBT. Specifically, Fig. 7 a sectional view taken along a dotted-and-dashed line CC of the semiconductor device 100, 101, which is in Fig. 6 is illustrated, and Fig. Figure 8 is a sectional view taken along the dotted-and-dashed line DD of the semiconductor device 100, 101, which is shown in Fig. Figure 6 illustrates this.

[0048] Diode trench gates 21 are provided along the first main surface of the semiconductor device 100, 101, extending from one end face of the diode region 20 in the cell region towards the other end face, which faces the first end face. A diode trench gate 21 is formed from a diode trench electrode 21a, which is provided in a trench in the diode region 20 via a diode trench insulating layer 21b. The diode trench electrode 21a is the n - -Type drift layer 1 facing, with the diode trench insulating layer 21b inserted in between.

[0049] Between two adjacent diode trench gates 21, there is a p + -type contact layer 24 and a p-type anode layer 25, which has a lower concentration of p-type defects than the p + -Type contact layer 24 is provided. The p +-Type contact layer 24 is a semiconductor layer which, for example, has boron or aluminum as p-type defects, and the p-type defects have, for example, a concentration of 1.0E + 15 / cm². 3 up to 1.0E + 20 / cm 3 The p-type anode layer 25 is a semiconductor layer which, for example, contains boron or aluminum as p-type defects, and the p-type defects have, for example, a concentration of 1.0 E + 12 / cm². 3 up to 1.0E + 19 / cm 3 up. The p + The -type contact layer 24 and the p-type anode layer 25 are provided alternately in a longitudinal direction of the diode trench gate 21.

[0050] Fig. Figure 7 is a sectional view of the semiconductor device 100, 101, which is shown along the dotted-and-dashed line CC in Fig. Figure 6 is provided and is a sectional view of the diode region 20. The semiconductor device 100, 101 has the diode region 20, which also contains the n --Type drift layer 1 comprises a semiconductor substrate, as in IGBT region 10. The n - -Type drift layer 1 in the diode region 20 and the n - -Type drift layer 1 in IGBT region 10 are formed continuously and integrally in an identical semiconductor substrate.

[0051] In Fig. 7. A semiconductor substrate from the p is sufficient. + -Type contact layer 24 up to a n + -Type cathode layer 26. In Fig. 7 will be an upper end of the p + -Type contact layer 24 in the figure is designated as the first main surface of the semiconductor substrate, and a lower end of the n +The cathode layer 26 of type in the figure is designated as the second principal area of ​​the semiconductor substrate. The first principal area of ​​the diode region 20 and the first principal area of ​​the IGBT region 10 are contained in the same area, and the second principal area of ​​the diode region 20 and the second principal area of ​​the IGBT region 10 are contained in the same area.

[0052] As in Fig. Figure 7 illustrates that, as with the IGBT region 10, in the diode region 20 the n-type buffer layer 3 is located on the second main surface side of the n - -Type drift layer 1 is provided. Although not illustrated, as with IGBT region 10, in diode region 20 the n-type charge carrier storage layer can be found on the first main face of the n - -Type Drift Layer 1 must be provided.

[0053] The n-type charge carrier storage layer and the n-type buffer layer 3 provided in diode region 20 can have an identical structure to the n-type charge carrier storage layer and the n-type buffer layer 3 provided in IGBT region 10. As in IGBT region 10, the n - The -type drift layer 1, the n-type charge carrier storage layer, and the n-type buffer layer 3 are collectively referred to as the drift layer.

[0054] The p-type anode layer 25, which is a first anode layer, is located on the first main surface face of the n - -Type drift layer 1 is provided. The p-type anode layer 25 is located between the n -The p-type drift layer 1 and the first main surface are provided. The p-type anode layer 25 is connected to the emitter electrode 6 via the barrier metal 5. The p-type anode layer 25 and the p-type base layer 15 can be formed simultaneously by allowing the p-type anode layer 25 and the p-type base layer 15 in the IGBT region 10 to have an identical concentration of p-type impurities. The p-type anode layer 25 can be designed such that it has a lower concentration of p-type impurities than the concentration of p-type impurities in the p-type base layer 15 in the IGBT region 10, thus reducing the number of positive holes injected into the diode region 20 during diode operation. Reducing the amount of injected positive holes during diode operation can reduce the recovery loss of diode operation.

[0055] The p +The p-type contact layer 24, which is a first contact layer, is provided on the first main surface face of the p-type anode layer 25. The p + -Type contact layer 24 can have a concentration of p-type defects that is identical or different with respect to a concentration of p-type defects of the p + -Type contact layer 14 in IGBT region 10. The p + The -type contact layer 24 forms the first main surface of the semiconductor substrate. The p + The p-type contact layer 24 is a region where the concentration of p-type defects is higher than that of the p-type anode layer 25. If it is necessary to remove the p + To distinguish between the -type contact layer 24 and the p-type anode layer 25, they can be designated individually. Alternatively, the p + The p-type contact layer 24 and the p-type anode layer 25 are jointly referred to as the p-type anode layer.

[0056] The n +-Type cathode layer 26 and a p + The first charge carrier removal layer, a type 27, is provided on the second main surface of the semiconductor device 100, 101, which has the n-type buffer layer 3. That is, the n + -Type cathode layer 26 and the p + -Type charge carrier dissipation layer 27 are located between the n - -Type Drift layer 1 and the second main area provided.

[0057] The n + -Type cathode layer 26 is a semiconductor layer which, for example, has arsenic or phosphorus as n-type defects, and the n-type defects have, for example, a concentration of 1.0E + 16 / cm². 3 up to 1.0E + 21 / cm 3 up. The p +-Type charge carrier dissipation layer 27 is a semiconductor layer which, for example, has boron or aluminum as p-type defects, and the p-type defects have a concentration of, for example, 1.0E + 16 / cm². 3 up to 1.0E + 20 / cm 3 up. The p + -Type charge carrier dissipation layer 27 is next to the n + -Type cathode layer 26 provided in one direction within the plane of the semiconductor substrate. In the example of Fig. 7 is the p + -Type charge carrier dissipation layer 27 of the n + -Type cathode layer 26 surrounded. The n + -Type cathode layer 26 and the p + -Type charge carrier discharge layer 27 form the second main surface of the semiconductor substrate and are connected to the collector electrode 7.

[0058] The p +A p-type charge carrier dissipation layer 27 can be formed by selectively injecting p-type impurities into a back face of the diode region 20 using a photoresist or the like. Alternatively, the p + -Type charge carrier dissipation layer 27 may be partially formed in the back surface of the diode region 20, using a concentration difference between p-type impurities injected into the entire back surface of the diode region 20 and n-type impurities in the n + -Type cathode layer 26, which are subsequently injected into the rear surface thereof.

[0059] As in Fig. As illustrated in Figure 7, the diode region 20 of the semiconductor device 100, 101 is provided with a trench which leads from the first main surface of the semiconductor substrate through the p-type anode layer 25 and the n --Type drift layer 1 is reached. The diode trench gate 21 is constructed from the diode trench electrode 21a, which is provided in a trench in the diode region 20 via the diode trench insulating layer 21b. The diode trench electrode 21a is the n - -Type drift layer 1 facing, with the diode trench insulating layer 21b inserted in between.

[0060] As in Fig. Figure 7 illustrates the barrier metal 5 on the diode trench electrode 21a and the p + -Type contact layer 24 is provided. The barrier metal 5 is in ohmic contact with the diode trench electrode 21a and the p + -Type contact layer 24, and is electrically connected to the diode trench electrode 21a and the p + -Type contact layer 24 connected.

[0061] Barrier metal 5 can have an identical structure to barrier metal 5 in IGBT region 10.

[0062] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is continuously connected to the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the diode trench electrode 21a and the p + The contact layer 24 can be brought into ohmic contact with the emitter electrode 6 without providing the barrier metal 5. That is, the emitter electrode 6 can essentially be provided on the first main surface of the semiconductor substrate.

[0063] Although Fig. Figure 7 illustrates a structure in which the intermediate insulating layer 4 is as shown in Fig. If the intermediate layer 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the intermediate layer insulating layer 4 on the trench electrode 21a can be partially removed. Fig. 7 be provided. If the intermediate insulating layer 4 on the diode trench electrode 21a of the diode trench gate 21 in the sub-region of Fig. If electrode 7 is provided, the emitter electrode 6 and the diode trench electrode 21a can be electrically connected in another sub-area. The diode trench electrode 21a, which is not electrically connected to the emitter electrode 6, can be electrically connected to the gate pad 41c.

[0064] The collector electrode 7 is located on the second main surface side of the n + -Type cathode layer 26 is provided. As with the emitter electrode 6, the collector electrode 7 is continuously formed in the diode region 20 with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n + -Type cathode layer 26 and is electrically connected to the n +-Type cathode layer 26 connected. That is, the collector electrode 7 can be provided on the second main surface of the semiconductor substrate.

[0065] Fig. Figure 8 is a sectional view of the semiconductor device 100, 101, which is shown along the dotted-and-dashed line DD in Fig. 6 is taken from the diagram and is a sectional view of the diode region 20. In contrast to the section taken along the dotted-and-dashed line CC, which is shown in the diagram, the following section is shown in the diagram: Fig. As illustrated in 7, the p + -Type contact layer 24 not provided between the p-type anode layer 25 and the barrier metal 5 in the sub-area that extends along the dotted-and-dashed line DD of Fig. 8 is taken from, and the p-type anode layer 25 is the first main surface of the semiconductor substrate. That is, the one in Fig. 7 illustrated p +The p-type contact layer 24 is selectively provided on the first main surface face of the p-type anode layer 25. Fig. 8 the p-type anode layer 25 is connected to the emitter electrode 6 via the barrier metal 5. <Struktur der Grenzregion zwischen der IGBT-Region 10 und der Diodenregion 20>

[0066] The Fig. 9 and Fig. Figures 10 are a top view and a sectional view, respectively, illustrating the structure of a boundary region 50 between the IGBT region 10 and the diode region 20 of the semiconductor device according to the first preferred embodiment. Specifically, Fig. 9 a top view near the dotted-and-dashed line EE in each of the semiconductor devices 100, 101, each located in the Fig. 1 and Fig. 2 are illustrated, and Fig. Figure 10 is a sectional view taken along the dotted-and-dashed EE. To avoid duplication, the content described in IGBT region 10 and diode region 20, especially abbreviations and component names, has been appropriately removed.

[0067] The Fig. 9 and Fig. Figure 10 illustrates not only the IGBT region 10 and the diode region 20, but also the boundary region 50 between the IGBT region 10 and the diode region 20. In the present first preferred embodiment, the boundary region 50 is located between a trench gate of the IGBT region 10 and a trench gate of the diode region 20. The IGBT region 10, the diode region 20, and the boundary region 50 are provided on the semiconductor substrate in the direction in the plane of the semiconductor substrate. The boundary region 50 is provided here between a set of adjacent trench gates, but it can be provided in a region spanning several trench gates, or it can be provided only in a portion between a set of adjacent trench gates.

[0068] A p - -Type anode layer 55, which is a second anode layer, is on the first main surface side of the n - -Type Drift layer 1 provided in border region 50. The p- Type 55 anode layer is a semiconductor layer which, for example, contains boron or aluminum as p-type defects. - The p-type anode layer 55 in the boundary region 50 has a concentration of p-type defects that is lower than the concentration of p-type defects in the p-type anode layer 25 in the diode region 20.

[0069] A p + -Type contact layer 54 is a second contact layer located on the first main surface face of the p - -Type anode layer 55 is provided. The p + The -type contact layer 54 is a semiconductor layer which, for example, contains boron or aluminum as p-type defects. The p + -Type contact layer 54 can have a concentration of p-type defects that is identical or different with respect to a concentration of p-type defects of the p + -Type contact layer 14 in IGBT region 10. The p +-Type contact layer 54 is a region which has a higher concentration of p-type defects than the p - -Type anode layer 55.

[0070] The n-type drift layer 1 in boundary region 50 is provided on the second main surface side of the n-type buffer layer 3. Although not illustrated, boundary region 50, like IGBT region 10, includes the n - -Type drift layer 1, which can be provided on the first main surface side of the n-type charge carrier storage layer.

[0071] A p-type collector layer 56, which is a collector layer, is provided on the second main surface of the n-type buffer layer 3. The p-type collector layer 56 is a semiconductor layer that exhibits, for example, boron or aluminum as p-type defects. The p-type collector layer 56 can have a concentration of p-type defects that is identical or different from the concentration of p-type defects in the p-type collector layer 16 in IGBT region 10. The p-type collector layer 56 is located next to the p-type collector layer 16 in IGBT region 10 and the n + -Type cathode layer 26 in the diode region 20 in the direction within the plane of the semiconductor substrate provided.

[0072] In the section of Fig. 10 the semiconductor substrate extends in the border region 50 from the p + -Type contact layer 54 up to p-type collector layer 56. The p +The -type contact layer 54 is contained in the first main area of ​​the semiconductor substrate, and the p-type collector layer 56 is contained in the second main area of ​​the semiconductor substrate. In one of Fig. In the 10 deviating section, the semiconductor substrate extends from the p in the border region 50. - -Type anode layer 55 to the p-type collector layer 56. The p - The p-type anode layer 55 is contained in the first main component of the semiconductor substrate, and the p-type collector layer 56 is contained in the second main area of ​​the semiconductor substrate.

[0073] Even in the border region 50, the emitter electrode 6 is provided on the first main surface of the semiconductor substrate, and the p + -Type contact layer 54 and the p -The p-type anode layer 55 is connected to the emitter electrode 6 via the barrier metal 5. Even in the boundary region 50, the collector electrode 7 is located on the second main surface of the semiconductor substrate, and the p-type collector layer 56 is connected to the collector electrode 7. <Abschlussregion 30>

[0074] The Fig. 11 and Fig. Figures 12 are each a sectional view illustrating the structure of a termination region of the semiconductor device, which is an RC-IGBT. Specifically, Fig. 11 a sectional view, drawn along the dotted-and-dashed line FF in Fig. 1 or Fig. 2 is taken from, and is a cross-sectional view from IGBT region 10 to the termination region 30. Fig. Figure 12 is a sectional view drawn along the dotted-and-dashed line GG in Fig. 1 is taken from, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0075] As in the Fig. 11 and Fig. As shown in Figure 12, the termination region 30 of the semiconductor device 100 exhibits an n - -Type drift layer 1 between the first major surface and the second major surface of the semiconductor substrate. The first major surface and the second major surface in termination region 30, and the first major surface and the second major surface in IGBT region 10 and diode region 20, are contained in the same area. The n - -Type drift layer 1 in the termination region 30 exhibits an identical structure to the n - -Type drift layer 1 in each of the IGBT region 10 and the diode region 20, and it is continuous and integral with the n - -Type Drift Layer 1 formed in each of them.

[0076] On the first main surface side of the n - -Type drift layer 1, i.e., between the first main surface of the semiconductor substrate and the n -In the -type drift layer 1, a p-type termination tray layer 31 is selectively provided. The p-type termination tray layer 31 is a semiconductor layer that contains, for example, boron or aluminum as p-type defects, and the p-type defects have a concentration of, for example, 1.0 E + 14 / cm². 3 up to 1.0E + 19 / cm 3 The p-type termination tray layer 31 is provided such that it surrounds the cell region containing the IGBT region 10 and the diode region 20. Several p-type termination tray layers 31 are provided in the form of a ring, and the number of p-type termination tray layers 31 to be provided is selected appropriately depending on the withstand voltage design of the semiconductor device 100, 101. Furthermore, an n + -Type channel stop layer 32 provided on one edge side starting from the p-type end trough layers 31, and the n +-Type channel stop layer 32 surrounds the p-type end trough layers 31 in the top view.

[0077] Between the n - A p-type termination collector layer 16a is provided between the p-type drift layer 1 and the second main surface of the semiconductor substrate in termination region 30. The p-type termination collector layer 16a is continuous and integral with the p-type collector layer 16, which is provided in IGBT region 10 of the cell region. Consequently, the p-type collector layer 16, which contains the p-type termination collector layer 16a, can be referred to as the p-type collector layer.

[0078] In a structure in which the diode region 20 is located next to the termination region 30 as in the Fig. In the semiconductor device 100 illustrated in Figure 1, the p-type termination collector layer 16a is provided such that an end section is located near the diode region 20, with the end section pointing towards the diode region 20, as shown in Figure 1. Fig. Figure 12 illustrates this, protruding only by a distance U. This type of structure allows for an increase in the distance between the n + The -type cathode layer 26 and the p-type termination well layer 31 are located in the diode region 20, thus preventing the p-type termination well layer 31 from acting as the anode of a diode. The distance U can be, for example, 100 µm.

[0079] The collector electrode 7 is provided on the second main surface of the semiconductor substrate. Starting from the cell region containing the IGBT region 10 and the diode region 20, the collector electrode 7 extends continuously and integrally to the termination region 30.

[0080] In contrast, the first major surface of the semiconductor substrate in the termination region 30 is provided with the emitter electrode 6, which extends continuously from the cell region, and a termination electrode 6a is structurally separated from the emitter electrode 6. The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating layer 33. The semi-insulating layer 33 can, for example, be a semi-insulating silicon nitride (sinSiN). The termination electrode 6a and each of the p-type termination well layers 31 and the n +The channel stop layer 32 is electrically connected via a contact hole in the intermediate insulating layer 4, which is provided on the first main surface of the termination region 30. The termination region 30 is provided with a termination protective layer 34, which covers the emitter electrode 6, the termination electrode 6a, and the semi-insulating layer 33. The termination protective layer 34 is made, for example, of polyimide. <Verfahren zur Herstellung des RC-IGBT>

[0081] The Fig. Figures 13A to 20B are each a sectional view illustrating a method for manufacturing a semiconductor device that is an RC-IGBT. Fig. Figures 13A to 18B each represent a diagram illustrating a process for the main formation of one side of a front surface in the boundary region 50 of Fig. Figure 10 of the semiconductor device 100, 101 illustrates the Fig. Figures 19A to 20B each represent a diagram illustrating a process for the main formation of one side of a back surface in the boundary region 50 of Fig. 10 of the semiconductor device 100, 101 illustrated.

[0082] As in Fig. Figure 13A illustrates that a semiconductor substrate is first used, which contains the n -The semiconductor substrate is prepared to form a -type drift layer 1. The semiconductor substrate can be, for example, an FZ wafer produced by a zone melting (FZ) process, an MCZ wafer produced by a magnetic field-applying Czochralski (MCZ) process, or an n-type impurity-containing wafer. The n-type impurities contained in the semiconductor substrate have a concentration that is appropriately selected depending on the withstand voltage of the semiconductor device to be manufactured. For example, a semiconductor device with a withstand voltage of 1200 V has n-type impurities with a concentration that is adapted such that the n - The drift layer 1, which forms the semiconductor substrate, has a resistivity of approximately 40 to 120 Ω·cm. As in Fig. Figure 13A illustrates that in the semiconductor substrate preparation step, the entire semiconductor substrate is the n --Type Drift Layer 1. When p-type or n-type impurity ions are injected into a semiconductor substrate as described above from the first main surface side or the second main surface side and subsequently diffused into the semiconductor substrate by heat treatment or the like, a p-type or n-type semiconductor layer is formed in a suitable manner and the semiconductor device 100, 101 is produced.

[0083] As in Fig. As illustrated in 13A, the semiconductor substrate, which the n -A drift layer 1 of type 1 forms a region which is to become IGBT region 10, diode region 20, and boundary region 50. Although not illustrated, a region which is to become termination region 30 or the like is provided around the region which is to become IGBT region 10, diode region 20, and boundary region 50. Although mainly a method for fabricating a structure of IGBT region 10, diode region 20, and boundary region 50 of the semiconductor device 100, 101 is described below, termination region 30 and the like of the semiconductor device 100, 101 can be fabricated by a well-known fabrication method.For example, if an FLR is formed in the termination region 30, which has the p-type termination basin layer 31 as a stress-holding structure, p-type impurity ions can be injected to create the FLR prior to processing the IGBT region 10, the diode region 20, and the interface region 50 of the semiconductor device 100, 101. Alternatively, if p-type impurity ions are injected into the IGBT region 10, the diode region 20, or the interface region 50 of the semiconductor device 100, the p-type impurity ions can be injected simultaneously to form an FLR.

[0084] Although not illustrated, as needed, n-type impurities such as phosphorus (P) are next injected into the semiconductor substrate from the first main face to form an n-type charge carrier storage layer. As shown in Fig. As illustrated in Figure 13B, p-type impurities such as boron (B) are subsequently injected into the semiconductor substrate from the first main face to form the first p-type base layer 15, the p-type anode layer 25, and the p - -type anode layer 55. The n-type charge carrier storage layer (not shown), the p-type base layer 15, the p-type anode layer 25, and the p -n-type anode layer 55 is formed by injecting impurity ions into the semiconductor substrate, and subsequently, the impurity ions are diffused by heat treatment. The n-type and p-type impurity ions are injected after mask processing has been applied to the first major surface of the semiconductor substrate. The mask processing is performed to form a mask on the semiconductor substrate to allow ion injection and etching in a predefined region of the semiconductor substrate through an opening, as follows: a photoresist is applied to a semiconductor substrate; and an opening is formed in a predefined region of the photoresist using a photogravure technique.The mask processing and ion injection described above enable the n-type charge carrier storage layer (not shown), the p-type base layer 15, the p-type anode layer 25, and the p. - The p-type anode layer 55 is selectively formed in the IGBT region 10 and the diode region 20 on the first main surface face. Similarly, the p-type termination trough layer 31 is selectively formed in the termination region 30.

[0085] The p-type impurities of the p-type base layer 15 and those of the p-type anode layer 25 can be injected simultaneously. In this case, the p-type base layer 15 and the p-type anode layer 25 have an identical depth and concentration of p-type defects. Alternatively, the p-type impurity ions of the p-type base layer 15 and those of the p-type anode layer 25 can be injected separately using mask processing to allow the p-type base layer 15 and the p-type anode layer 25 to have different depths and concentrations of p-type impurities.

[0086] The p-type impurities of the p - -Type anode layer 25 and the p - Type 55 anode layers with different concentrations can be injected separately. For example, in Fig. As illustrated in Figure 14, p-type impurities such as boron are selectively injected into the boundary region 50 after p-type impurities such as boron have been selectively injected into the diode region 20 using a photoresist 58. At this point, the concentration of the p-type impurities injected into the boundary region 50 is reduced to a level lower than the concentration of the impurities injected into the diode region 20. After the photoresist 58 and the like have been removed, a subsequent heat treatment is performed to diffuse the p-type impurities, thereby removing the p-type anode layer 25 and the p - -Type anode layer 55 will be formed.

[0087] As an alternative to the above, the p-type impurity ions of the p-type anode layer 25 and the p --Type anode layer 55, which has different concentrations, are injected simultaneously using masks with different aperture ratios. For example, in Fig. As illustrated in Figure 15, masks with different aperture ratios are used to reduce the aperture ratio of the resist 58 per unit area in the boundary region 50 to a lower level than the aperture ratio of the resist 58 per unit area in the diode region 20. In this case, a grid-shaped mask can be used for one or both masks to allow them to have different aperture ratios. Even if, as described above, the p-type impurities emitted onto the diode region 20 and the boundary region 50 from above the photoresist 58 have an identical concentration, the boundary region 50 may have a lower concentration of p-type impurities than the diode region 20. After the photoresist 58 and the like have been removed, a subsequent heat treatment is carried out to eliminate the p-type impurities, as shown in Figure 15. Fig. 15 illustrates diffusing, thereby forming the p-type anode layer 25 and the p - -Type anode layer 55 is formed.

[0088] The p-type impurities of the p-type finishing trough layer 31 in the finishing region 30 (in Fig. (Figure 13B not shown) and those of the p-type anode layer 25 can be injected simultaneously. In this case, the p-type end-trough layer 31 and the p-type anode layer 25 have an identical depth and concentration of p-type defects relative to each other. Alternatively, the p-type impurities of the p-type end-trough layer 31 and those of the p-type anode layer 25 can be injected separately by mask processing to allow the p-type end-trough layer 31 and the p-type anode layer 25 to have different depths and concentrations of p-type impurities relative to each other.Alternatively, if the p-type impurity ions of the p-type end-trough layer 31 and those of the p-type anode layer 25 are injected simultaneously using masks with different open-aperture ratios, the p-type end-trough layer 31 and the p-type anode layer 25 can also exhibit different concentrations of p-type impurities relative to each other. Similarly, p-type impurity ions can be present in the p-type end-trough layer 31, the p-type base layer 15, the p-type anode layer 25, and the p-type anode layer 25, respectively. - -Type anode layer 55 can be injected simultaneously using masks with different opening ratios.

[0089] Next, the n +The p-type emitter layer 13 is selectively formed on the first main surface face of the p-type base layer 15 in the IGBT region 10 by mask processing and the injection of n-type impurities. The n-type impurities to be injected can be, for example, arsenic (As) or phosphorus (P). Subsequently, as in Fig. Figure 16A illustrates that mask processing and the injection of p-type impurities enable the p + -Type contact layer 14 on the first main surface face of the p-type base layer 15 in the IGBT region 10 is selectively formed, and that the p + The p-type contact layer 24 is selectively formed on the first main surface face of the p-type anode layer 25 in the diode region 20. Similarly, the p + -Type contact layer 54 on the first main surface side of the p -The p-type anode layer 55 is selectively formed in the boundary region 50. The p-type impurities to be injected are, for example, boron or aluminum.

[0090] As in Fig. As illustrated in Figure 16B, a trench 8 is formed next, which passes through the p-type base layer 15, the p-type anode layer 25, or the p - -Type anode layer 55 extends from the first main surface side of the semiconductor substrate and the n - -Type drift layer 1 is reached. Trench 8 is formed, for example, as follows: after an oxide layer such as SiO2 has been applied to the semiconductor substrate, an opening is formed in a section of the oxide layer by mask processing, in which trench 8 is to be formed; and the semiconductor substrate is etched using the oxide layer with the opening formed as a mask. Although the trenches 8 in Fig. If the 16B is formed with a spacing that is identical in IGBT region 10, diode region 20, and border region 50, the spacing of the trenches 8 between IGBT region 10, diode region 20, and border region 50 can differ. The spacing and pattern of the trenches 8 can be suitably modified in a top view by using a masking pattern during masking.

[0091] As in Fig. As illustrated in Figure 17A, the semiconductor substrate is next heated in an oxygen-containing atmosphere to form an oxide layer 9 on an inner wall of the trench 8 and on the first major surface of the semiconductor substrate. The oxide layer 9 formed in the trench 8 in the IGBT region 10 serves as the correspondent to the gate-trough insulating layer 11b of the active trench gate 11 and the dummy-trough insulating layer 12b of the dummy-trough gate 12. The oxide layer 9 formed in the trench 8 in the diode region 20 serves as the diode-trough insulating layer 21b. The oxide layer 9 formed on the first major surface of the semiconductor substrate is removed in a later step, except for a portion formed in the trench 8.

[0092] As in Fig. As illustrated in Figure 17B, next a polysilicon doped with n-type or p-type impurities is applied to the oxide layer 9 in the trench 8 by chemical vapor deposition (CVD) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0093] As in Fig. As illustrated in Figure 18A, the interlayer insulating layer 4 is subsequently formed on the gate-trench electrode 11a of the active-trench gate 11 in the IGBT region 10. The interlayer insulating layer 4 can, for example, be SiO2. When mask processing is performed to form a contact hole in a deposited insulating layer, which becomes the interlayer insulating layer 4, and when the oxide layer 9 formed on the first main face of the semiconductor substrate is removed, the interlayer insulating layer 4 and the like are formed in Fig. 18A formed. Contact holes of the intermediate insulating layer 4 are located in corresponding sections such as the n + -Type emitter layer 13, the p + -Type contact layer 14, the p + -Type contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0094] The following, as in Fig. As illustrated in Figure 18B, the barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating layer 4, and the emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by physical vapor deposition (PDV) or CVD.

[0095] The emitter electrode 6 can be formed by depositing an aluminum-silicon alloy (Al-Si alloy) onto the barrier metal 5, for example, by PVD processes such as sputtering or vapor deposition. Subsequently, a nickel alloy (Ni alloy) can be formed onto the aluminum-silicon alloy by electroless or electrolytic plating to create the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal layer can be easily created. This allows for an increase in the heat capacity of the emitter electrode 6, thus improving its thermal resistance.If the emitter electrode 6, formed from an aluminium-silicon alloy, is formed by PVD, and subsequently a nickel alloy is additionally formed by a plating process, the plating process to form the nickel alloy can be carried out after the second main surface side of the semiconductor substrate has been processed.

[0096] As in Fig. As illustrated in Figure 19A, the second main surface of the semiconductor substrate is subsequently ground to reduce its thickness to a predetermined value. The ground semiconductor substrate can, for example, have a thickness of 80 µm to 200 µm.

[0097] As in Fig. As illustrated in Figure 19B, n-type impurities are subsequently injected from the second main face of the semiconductor substrate to form the n-type buffer layer 3. Subsequently, p-type impurities are injected from the second main face of the semiconductor substrate to form the p-type collector layer 16. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, the termination region 30, the boundary region 50, and the like, or it can be formed exclusively in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 can be formed, for example, by injecting phosphorus (P) ions or protons (H). +The n-type buffer layer 3 can be formed by injecting both protons and phosphorus. Protons can be injected deeply from the second main face of the semiconductor substrate with a relatively low acceleration energy. By changing the acceleration energy, the depth of proton injection can be varied relatively easily. If protons are injected multiple times to form the n-type buffer layer 3 while varying the acceleration energy, the n-type buffer layer 3 can consequently be formed thicker in one thickness direction of the semiconductor substrate than the layer formed from phosphorus.

[0098] In contrast, phosphorus exhibits a higher activation rate of n-type defects than protons. Therefore, if the n-type buffer layer 3 is formed from phosphorus, even a reduced-thickness semiconductor substrate can prevent depletion from propagating through. To further reduce the thickness of the semiconductor substrate, both protons and phosphorus are preferentially injected to form the n-type buffer layer 3. In this case, the protons are injected deeper than the phosphorus, starting from the second main surface.

[0099] The p-type collector layer 16 can be formed, for example, by injecting boron (B). The p-type collector layer 16 is also formed in the interface region 50, and the p-type collector layer 16 in interface region 50 becomes the p-type collector layer 56. The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in termination region 30 becomes the p-type termination collector layer 16a. After boron ions have been injected from the second main surface of the semiconductor substrate, the second main surface is irradiated with a laser for laser heat treatment to activate the injected boron and form the p-type collector layer 16. At this time, phosphorus, which was injected from the second main surface of the semiconductor substrate at a relatively shallow position, is also activated simultaneously.The protons are then activated at a relatively low heat treatment temperature of 380 °C to 420 °C, so the temperature of the entire semiconductor substrate must be kept from exceeding 380 °C to 420 °C after the protons have been injected, except during the proton activation step. Laser heat treatment can raise the temperature only near the second major surface of the semiconductor substrate and can therefore be used to activate n-type or p-type defects even after proton injection.

[0100] As in Fig. 20 illustrates the n + The p-type cathode layer 26 is selectively formed on the second main surface face of the diode region 20. The diode region 20 on the second main surface face has the p-type collector layer 16 without the n + -Type cathode layer 26, which the p + -Type charge carrier dissipation layer 27 is used.

[0101] The n + The -type cathode layer 26 can be formed, for example, by injecting phosphorus (P). The n-type impurities for forming the n + -Type cathode layer 26 exhibits an injection rate that is greater than the injection rate of p-type impurities for forming the p-type collector layer 16. Although Fig. 20A the p-type collector layer 16 and the n + -Type cathode layer 26 illustrates which have an identical depth starting from the second main surface, can the n + The -type cathode layer 26 has a depth greater than the depth of the p-type collector layer 16. Subsequently, the n +-Type cathode layer 26 is formed in a region that must ultimately be an n-type by injecting n-type impurities into a region in which p-type impurities are injected, such that the p-type impurities have a concentration that is higher than a concentration of the p-type impurities which are injected in the entire region in which the n + -Type cathode layer 26 is formed.

[0102] As in Fig. As illustrated in Figure 20B, the collector electrode 7 is subsequently formed on the second major face of the semiconductor substrate. The collector electrode 7 is formed over the entire area of ​​the second major face, encompassing the IGBT region 10, the diode region 20, the termination region 30, the boundary region 50, and the like. The collector electrode 7 can be formed over the entire area of ​​the second major face of an n-type wafer, which is a semiconductor substrate. The collector electrode 7 can be formed by depositing an aluminum-silicon alloy (Ai-Si alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, and can be formed by layering several metals such as an aluminum-silicon alloy, titanium, nickel, or gold, and the like.The collector electrode 7 can be formed by additionally forming a metal layer on a metal layer formed by PVD using electroless plating or electrolytic plating.

[0103] The semiconductor devices 100, 101 are fabricated by the steps described above. Several semiconductor devices 100, 101 are fabricated while integrated in a matrix on the semiconductor substrate, such as an n-type wafer. Subsequently, the semiconductor devices 100, 101 are individually separated by laser cutting or blade cutting. <Zusammenfassung der ersten bevorzugten Ausführungsform>

[0104] As described above, the p +In the first preferred embodiment, a p-type charge carrier dissipation layer 27 is provided on the second main surface face in the diode region 20. During forward operation of a diode, holes from the p-type anode layer 25 on the first main surface face are dissipated from the collector electrode 7 on the second main surface face. Although the n + -Type cathode layer 26, which at this time serves as a potential barrier for the holes, exhibits the p + The charge carrier dissipation layer 27 is a p-type. This causes the holes to be dissipated more efficiently, so that the amount of accumulated holes within the n - -Type Drift Layer 1 can be reduced. Consequently, recovery loss during the recovery process can be reduced.

[0105] Here, a structure without the boundary region 50 between the diode region 20 and the IGBT region 10 allows holes to flow into the diode region 20 from the p-type base layer 15 of the IGBT during forward operation of the diode, thus making recovery loss during the recovery process less likely. In contrast, the first preferred embodiment has the boundary region 50 between the diode region 20 and the IGBT region 10, and the p - The p-type anode layer 55, which has a lower concentration of p-type defects than the p-type anode layer 25 in the diode region 20, is provided on its side of the first front face of the boundary region 50. This reduces the number of holes injected into the boundary region 50, and the influx of holes into the diode region 20 can also be reduced, thus effectively reducing the recovery loss. <Explanation of the technical background of the invention>

[0106] Fig. Figure 21 is a top view illustrating the structure of a boundary region 50 between an IGBT region 10 and a diode region 20 of a semiconductor device to explain the technical background of the present invention, and is specifically a top view which is illustrated with Fig. 9 corresponds.

[0107] Here in the structure of Fig. 9 of the first preferred embodiment, are the p + -Type contact layer 54 and the p - -Type anode layer 55 in the border region 50 is essentially identical in area to p + -type contact layer 24 and to the p-type anode layer 25 in the diode region 20. In the first preferred embodiment, therefore, an occupied area ratio of the p +-Type contact layer 54 with respect to an area in which the emitter electrode 6 is in contact with the semiconductor substrate in the boundary region 50, essentially identical to an occupied area ratio of the p + -Type contact layer 24 with respect to an area in which the emitter electrode 6 is in contact with the semiconductor substrate in the diode region 20.

[0108] In contrast, a p + -Type contact layer 54 in the border region 50 in a structure of Fig. 21 of the semiconductor device to explain the technical background of the present invention, an area smaller than a p + -Type contact layer 24 in the diode region 20. In addition, the boundary region 50 has instead of the p - -Type anode layer 55 a p-type anode layer 55a which has a higher concentration of p-type defects and a larger area in plan view than the p --type anode layer 55. The concentration of p-type defects in the p-type anode layer 55a is, for example, similar to a concentration of p-type defects in the p-type anode layer 25. Consequently, in the semiconductor device for illustrating the technical background of the present invention, an occupied area ratio of the p + -Type contact layer 54 with respect to an area in which the emitter electrode 6 is in contact with the semiconductor substrate in the boundary region 50, smaller than an occupied area ratio of the p + -Type contact layer 24 with respect to an area in which the emitter electrode 6 is in contact with the semiconductor substrate in the diode region 20. The boundary region 50 according to the semiconductor device for explaining the technical background of the present invention is, however, not limited to the structure which the p + -type contact layer 54 and the p-type anode layer 55a contain, and can the p +-Type contact layer 54 and the p - -Type anode layer 55 as included in the first preferred embodiment. Another structure is similar to that of the first preferred embodiment. <Zusammenfassung zur Halbleitervorrichtung zur Erläuterung des technischen Hintergrunds der vorliegenden Erfindung >

[0109] During forward operation of a diode, the p + -Type contact layer 24 on the first main surface face in the diode region 20 acts as a potential barrier for electrons. As soon as the occupied area ratio of the p +-Type contact layer 24 with respect to the area in which the emitter electrode 6 is in contact with the semiconductor substrate increases, the accumulation of electrons increases, and consequently, the recovery loss increases. The semiconductor device for illustrating the technical background of the present invention has the boundary region 50, which is provided between the diode region 20 and the IGBT region 10, and the occupied area ratio with respect to the p + The contact layer 54, which is the type of contact layer 54, is relatively small in relation to the area where the emitter electrode 6 is in contact with the semiconductor substrate in the interface region 50. This reduces the number of electrons injected into the interface region 50, and also reduces the influx of electrons into the diode region 20, thus effectively reducing the recovery loss. <Dritte bevorzugte Ausführungsform>

[0110] Fig. Figure 22 is a sectional view illustrating the structure of a boundary region 50 between an IGBT region 10 and a diode region 20 of a semiconductor device according to a third preferred embodiment, and is specifically a sectional view which is illustrated with Fig. 10 corresponds. The present third preferred embodiment comprises a p + A charge carrier dissipation layer 27, which has a maximum width of 10 µm or less in the in-plane direction. Another structure is similar to that of the first preferred embodiment or the semiconductor device for the purpose of explaining the technical background of the present invention.

[0111] As described in the first preferred embodiment, the p + -Type charge carrier dissipation layer 27, that holes are dissipated more efficiently during forward operation of a diode, and consequently the number of accumulated holes in an n --Type drift layer 1 is reduced. However, an electron injection from a collector electrode 7 is only reduced by one n + -Type cathode layer 26 is implemented, such that the current density within a diode region 20 becomes somewhat uneven. This causes an impact ionization current due to a local increase in current density, which is likely to occur during the recovery process, and can consequently lead to an increase in power loss.

[0112] Fig. Figure 23 is a diagram illustrating the results of a simulation effect of an increase in recovery loss due to a shock ionization current during a recovery process. The results of Fig. 23 are obtained by calculating the recovery loss, using Wp, which has a width of p + -Type charge carrier dissipation layer 27 is and a repetition distance in a structure in which the p +-Type charge carrier dissipation layer 27 and the n + -Type cathode layer 26 are repeated at regular intervals on a second main surface of the diode region 20, and are divided. The repetition distance ranges from 6 µm to 60 µm, although it is in Fig. Figure 23 is not shown. The vertical axis represents a ratio (= Err2 / Err1) of the recovery loss Err1 when shock ionization is not calculated and the recovery loss Err2 when shock ionization is calculated. A larger Err2 / Err1 represents a greater increase in recovery loss due to the shock ionization current. <Zusammenfassung der dritten bevorzugten Ausführungsform>

[0113] The present third preferred embodiment features the p +-Type charge carrier dissipation layer 27, which has a maximum width, i.e., a Wp of 10 µm or less in the in-plane direction. This type of structure allows the effect of the impact ionization current on the recovery loss to be calculated based on the result of Fig. 23 is reduced, and therefore the recovery loss can be effectively reduced. <Vierte bevorzugte Ausführungsform>

[0114] In the present fourth preferred embodiment, a p + -Type charge carrier dissipation layer 27 an area which is 20% or more of the sum of the area of ​​the p + -Type charge carrier dissipation layer 27 and an area of ​​an n + -Type cathode layer 26 in a top view corresponds to another structure similar to that of the first to third preferred embodiments.

[0115] Fig. 24 shows results of a relationship between an area ratio of p+ -Type charge carrier dissipation layer 27 with respect to the sum of the area of ​​the p + -Type charge carrier dissipation layer 27 and the area of ​​the n + -type cathode layer 26, and the recovery loss, wherein the results are calculated by a simulation in the fourth preferred embodiment. The area ratio of the p + The charge carrier dissipation layer type 27 increases, and the recovery loss decreases. If the area ratio of the p + -Type charge carrier dissipation layer 27 20% or more, a reduction in recovery loss is saturated, and therefore approximately the same loss reduction effect can be achieved. <Zusammenfassung der vierten bevorzugten Ausführungsform>

[0116] In the present fourth preferred embodiment, the p + -Type charge carrier dissipation layer 27 an area which is 20% or more than the sum of an area of ​​p +-Type charge carrier dissipation layer 27 and an area of ​​an n + -Type cathode layer 26 is used, so that recovery loss can be effectively reduced. <Fünfte bevorzugte Ausführungsform>

[0117] The Fig. Figures 25A to 25C are each an enlarged top view of a diode region 20 of a semiconductor device according to a fifth embodiment. The present fifth embodiment has a p + -Type charge carrier dissipation layer 27, comprising a long side Wp1 and a short side Wp2 with a length of 1 / 2 or less than the length of the long side Wp1 in a top view. Another structure is similar to that in each of the first to fourth embodiments. <Zusammenfassung der fünften bevorzugten Ausführungsform>

[0118] The present fifth preferred embodiment features the p +-Type charge carrier dissipation layer 27, which has the short side Wp2, which corresponds to a relatively short length, so that an area ratio of p + -Type charge carrier dissipation layer 27 can be relatively increased by increasing the long side Wp1 of the p + The charge carrier dissipation layer of type 27 is relatively extended. This not only allows for a reduction in dynamic avalanche breakthrough during the recovery process, but also in charge carrier density during forward operation, so that the recovery loss can be effectively reduced. <Sechste bevorzugte Ausführungsform>

[0119] In the present sixth embodiment, an occupied area ratio of a p is +-Type contact layer 24 with respect to an area in which the emitter electrode 6 is in contact with a semiconductor substrate in a diode region 20, 0.8 or less. Another structure is similar to that of the first to fifth preferred embodiments. Fig. 26 shows results of a relationship between the occupied area ratio of the p + -Type contact layer 24 with respect to an area in which the emitter electrode 6 is in contact with the semiconductor substrate in the diode region 20, and the recovery loss (Err), wherein the result is calculated by a simulation in the sixth preferred embodiment. The results show that the occupied area ratio of the p + -Type contact layer 24 increases, the recovery loss increases, and the occupied area ratio of the p + -Type contact layer 24, which exceeds 0.8 (80%), causes a significant increase in recovery loss. <Zusammenfassung der sechsten bevorzugten Ausführungsform>

[0120] As described above, the p serves + -Type contact layer 24 on a first main surface face in the diode region 20 during forward operation of a diode acts as a potential barrier for electrons. Consequently, an area of ​​the p + -Type contact layer 24 with respect to an area in which the emitter electrode 6 is in contact with the semiconductor substrate, an accumulation of electrons increases, and consequently the recovery loss increases. In the present sixth preferred embodiment, an area ratio of p + -Type contact layer 24 in the diode region 20 0.8 or less, so that a charge carrier accumulation in the diode region 20 can be reduced, and consequently the recovery loss can be effectively reduced. <Siebte bevorzugte Ausführungsform>

[0121] Fig. Figure 27 is a top view illustrating the structure of a boundary region 50 between an IGBT region 10 and a diode region 20 of a semiconductor device according to a seventh preferred embodiment, and is specifically a top view that includes Fig. 9 corresponds. The semiconductor substrate according to the present seventh embodiment further comprises an n + -Type charge carrier dissipation layer 28, which is a second charge carrier dissipation layer. The n + A p-type charge carrier dissipation layer 28 is provided on a first main surface face in the diode region 20, next to a p-type anode layer 25 and / or a p + -Type contact layer 24 in one direction within the plane. Fig. Figure 27 illustrates an example in which the n + -Type charge carrier dissipation layer 28 through the p-type anode layer 25 and the p + -Type contact layer 24 is surrounded. <Zusammenfassung der siebten bevorzugten Ausführungsform>

[0122] During forward operation of a diode, the n + -Type charge carrier dissipation layer 28 on the first main surface face of the semiconductor substrate does not act as a potential barrier for electrons, so that from a n + -Type cathode layer 26 on a second main surface side electrons injected through the n + -Type charge carrier dissipation layer 28 is efficiently dissipated. This reduces the accumulation of electrons in the diode region 20 during forward operation, thus effectively reducing recovery loss.

Claims

[1] Semiconductor device (100, 101), comprising: - a semiconductor substrate of a first conductivity type, which comprises: - a first main surface and a second main surface opposite the first main surface, - an IGBT region (10), - a diode region (20), and - a boundary region (50) located between the IGBT region (10) and the diode region (20) provided along a first direction within the plane of the semiconductor substrate; - an emitter electrode (6) provided on the first main surface of the semiconductor substrate; and - a collector electrode (7) provided on the second main surface of the semiconductor substrate, wherein the semiconductor substrate comprises: - a first anode layer (25) of a second conductivity type and a first contact layer (24) of the second conductivity type having a higher concentration of impurities of the second conductivity type than the first anode layer (25), which are provided on a first main surface side, which is a side of the first main surface, in the diode region (20); - a cathode layer (26) of the first conductivity type provided on a second main surface side, which is one side of the second main surface, in the diode region (20); - a first charge carrier dissipation layer (27) of the second conductivity type, which is provided adjacent to the cathode layer (26) in the first direction within the plane of the second main surface side in the diode region (20); - a second anode layer (55) of the second conductivity type and a second contact layer (54) of the second conductivity type having a higher concentration of impurities of the second conductivity type than the second anode layer (55), which are provided on the first main surface side in the boundary region (50); and - a collector layer (56) of the second conductivity type provided on the second main surface side in the boundary region (50), and wherein a concentration of impurities of the second conductivity type of the second anode layer (55) is lower than a concentration of impurities of the second conductivity type of the first anode layer (25). [2] The semiconductor device (100, 101) according to claim 1, wherein the first charge carrier dissipation layer (27) has a maximum width of 10 µm or less. [3] The semiconductor device (100, 101) according to claim 1 or 2, wherein the first charge dissipation layer (27) has an area which, in a plan view, is 20% or more of a sum of the area of ​​the first charge dissipation layer (27) and an area of ​​the cathode layer (26). [4] The semiconductor device (100, 101) according to any one of claims 1 to 3, wherein the first charge dissipation layer (27) has a long side and a short side having a length of 1 / 2 or less of a length of the long side in a plan view. [5] The semiconductor device (100, 101) according to any one of claims 1 to 4, wherein a ratio of occupied areas of the first contact layer (24) with respect to an area in which the emitter electrode (6) is in contact with the semiconductor substrate in the diode region (20) is 0.8 or less. [6] The semiconductor device (100, 101) according to any one of claims 1 to 5, wherein the semiconductor substrate further comprises a second charge carrier discharging layer (28) of the first conductivity type provided on the first main surface side in the diode region (20) adjacent to the first anode layer (25) and / or the first contact layer (24) in a second in-plane direction different from the first in-plane direction.

Images