MANUFACTURING METHOD OF A HYBRID LAYER CONFIGURATION FOR SELF-ADJUSTED CONTACT

Abstract

Method for manufacturing a semiconductor device, comprising: Forming a metal gate structure (97) over a semiconductor fin (64), wherein the metal gate structure (97) is surrounded by an ILD layer (90); selective formation of an etch stop layer (105) over an upper surface of the ILD layer (90) distal to the semiconductor fin (64); Recessing the metal gate structure (97) beneath an upper surface of gate spacers (87) extending along opposite side walls of the metal gate structure (97), forming a recess (103) between the gate spacers (87) after the recessing; Lining side walls and a bottom of the recess (103) with a semiconductor material (107), wherein a first part of the semiconductor material (107) contacts the etch stop layer (105) and extends along the etch stop layer (105); after lining, filling the recess (103) with a dielectric material (109); Forming a structured etch stop layer stack over the dielectric material (109), the semiconductor material (107) and the ILD layer (90), wherein a first opening (120) in the structured etch stop layer stack (112) is directly above the dielectric material (109), the semiconductor material (107) and a first part of the ILD layer (90) adjacent to the gate spacers (87); Forming a second opening (121) in the ILD layer (90) by etching through the first opening (120) to remove the first part of the ILD layer (90), the second opening (121) exposing a source / drain region (80) adjacent to the metal gate structure (97); and Filling the second opening (121) with a conductive material (123).

Description

BACKGROUND

[0001] Continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) have led to rapid growth in the semiconductor industry. This improvement in integration density is largely due to repeated reductions in the minimum feature size, allowing more components to be integrated into a given area.

[0002] Fin field-effect transistor (FinFET) devices are widely used in integrated circuits. FinFET devices have a three-dimensional structure with a semiconductor fin protruding from a substrate. The semiconductor fin is surrounded by a gate structure configured to control a flow of charge carriers in a conductive channel of the FinFET device. For example, in a tri-gate FinFET device, the gate structure encloses three sides of the semiconductor fin, creating conductive channels on three sides of the semiconductor fin.

[0003] Manufacturing processes for self-aligned contacts are known, for example, from DE 10 2020 119 275 A1 and US 2020 / 0 105 577 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a perspective view of a fin field effect transistor (FinFET) device according to some embodiments. Fig. 2-6, 7A-7C and 8-15 show various cross-sectional views of a FinFET device at various stages of fabrication according to one embodiment. Fig. 16 shows a flow diagram of a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0005] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.

[0006] In addition, spatially relative terms such as "under," "beneath," "below," "below," "over," "upon," "above," "above," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the drawings. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.Unless otherwise indicated, throughout the specification the same or similar reference numerals in different drawings designate the same or a similar component manufactured in the same or a similar process using the same or similar materials.

[0007] Embodiments of the present invention are discussed in the context of fabricating a FinFET device, and more particularly, in the context of fabricating self-aligned contact plugs for a FinFET device. Although the disclosed embodiment is discussed using a FinFET device as an example, the disclosed methods may also be used in other types of devices, such as planar devices.

[0008] In some embodiments, when forming a self-aligned source / drain contact, a hybrid layer structure is formed over a metal gate structure between gate spacers of the metal gate structure to reduce a chopping effect. For example, the metal gate structure, surrounded by an inter-layer dielectric (ILD) layer, is recessed to form a recess between the gate spacers that extend along sidewalls of the metal gate structure. A semiconductor deposit (e.g., a silicon deposit) is conformally formed along sidewalls and a bottom surface of the recess, and a dielectric material (e.g., silicon nitride) is then formed on the semiconductor deposit in the recess to fill the recess.The semiconductor layer and the dielectric material in the recess are collectively referred to as a hybrid layer structure. A mask layer is then formed over the ILD layer, with an opening in the mask layer located directly above the hybrid layer structure and a portion of the ILD layer disposed over a source / drain region. An etching process is then performed, using the mask layer as an etch mask to remove the portion of the ILD layer and form an opening in the ILD layer, exposing the underlying source / drain region. A conductive material is then formed in the opening to create the self-aligned source / drain contact.Due to the etch selectivity provided by the hybrid layer structure during the etching process to create the opening, an open circuit effect is reduced, which in turn reduces device defects associated with a short circuit caused by the open circuit effect.

[0009] Fig. 1 shows an exemplary FinFET 30 in a perspective view. The FinFET 30 includes a substrate 50 and a fin 64 extending beyond the substrate 50. Isolation regions 62 are formed on opposite sides of the fin 64, with the fin 64 extending beyond the isolation regions 62. A gate dielectric 66 extends along sidewalls and above a top surface of the fin 64, and a gate electrode 68 is above the gate dielectric 66. Source / drain regions 80 are formed in the fin 64 and on opposite sides of the gate dielectric 66 and the gate electrode 68. Fig. 1 further shows reference cross-sections used in subsequent figures. Cross-section BB extends along a longitudinal axis of the gate electrode 68 of the FinFET 30. Cross-section AA is perpendicular to cross-section BB and extends along a longitudinal axis of the fin 64 and in a direction, for example, of current flow between the source / drain regions 80. Cross-section CC is parallel to cross-section BB and is across the source / drain region 80. Subsequent figures refer to these reference cross-sections for clarity.

[0010] Fig. 2-6, 7A-7C, and 8-15 are cross-sectional views of a FinFET device 100 at various stages of fabrication according to one embodiment. The FinFET device 100 is similar to the FinFET 30 in Fig. 1, but it has multiple fins and multiple gate structures. Fig. 2-5 show cross-sectional views of the FinFET device 100 along cross section BB. Fig. 6, 7A and 8-15 show cross-sectional views of the FinFET device 100 along cross section AA. Fig. 7B and Fig. 7C show cross-sectional views of embodiments of the FinFET device 100 along cross section CC.

[0011] Fig. 2 shows a cross-sectional view of the substrate 50. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material fabricated on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0012] In Fig. 3 will be in Fig. 2 is patterned, for example, using photolithography and etching techniques. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed over the substrate 50. The pad oxide layer 52 may be a thin layer of silicon oxide, formed, for example, using a thermal oxidation process. The pad oxide layer 52 may act as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed from silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0013] The mask layer can be patterned using photolithographic techniques. Generally, photolithographic techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 and to create a patterned mask 58, as shown in Fig. 3 is shown.

[0014] The patterned mask 58 is then used to pattern exposed portions of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61, as shown in Fig. 3. In some embodiments, the semiconductor fins 64 are formed by etching trenches in the substrate 50 using, for example, reactive ion etching (RIE) (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process may be anisotropic. In some embodiments, the trenches 61 may be stripes (viewed from above) that are parallel to each other and closely spaced with respect to each other. In some embodiments, the trenches 61 may be contiguous and may enclose the semiconductor fins 64. The semiconductor fins 64 may also be referred to as fins 64 hereinafter.

[0015] The fins 64 may be patterned using any suitable method. For example, the fins 64 may be patterned using one or more photolithographic processes, such as double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes that can create structures having, for example, pitches smaller than those otherwise achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to structure the fins.

[0016] Fig. 4 shows the formation of an insulating material between adjacent semiconductor fins 64 to form isolation regions 62. The insulating material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-cure to convert to another material, such as an oxide), the like, or a combination thereof. Other insulating materials and / or other manufacturing processes may also be used. In the illustrated embodiment, the insulating material is silicon oxide deposited using an FCVD process. After the insulating material has been deposited, an annealing process may be performed.Using a planarization process, such as chemical mechanical polish (CMP), excess insulating material can be removed, and coplanar upper surfaces of the isolation regions 62 and upper surfaces of the semiconductor fins 64 (not shown) can be fabricated. The patterned mask 58 (see FIG. Fig. 3) can be removed with the planarization process.

[0017] In some embodiments, the isolation regions 62 include a coating, for example, an oxide coating (not shown), at the interface between the isolation region 62 and the substrate 50 / the semiconductor fins 64. In some embodiments, the oxide coating is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the oxide coating may also be used to reduce crystal defects at the interface between the semiconductor fins 64 and the isolation region 62. The oxide coating (for example, silicon oxide) may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, although other suitable methods for forming the oxide coating may also be used.

[0018] Then, the isolation regions 62 are recessed to form shallow trench isolation (STI) regions 62. The isolation regions 62 are recessed such that the upper portions of the semiconductor fins 64 protrude between adjacent STI regions 62. Furthermore, the upper surfaces of the STI regions 96 may have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The upper surfaces of the STI regions 96 may be made flat, convex, and / or concave by a suitable etch. The isolation regions 62 may be recessed using a suitable etching process, such as one that is selective for the material of the isolation regions 62. For example, a dry etch or a wet etch using dilute hydrofluoric acid (dHF) may be performed to recess the isolation regions 62.

[0019] Fig. 2 to 4 illustrate one embodiment of the fabrication of fins 64, but fins can be fabricated using a variety of different processes. For example, an upper portion of substrate 50 may be replaced with a suitable material, such as an epitaxial material suitable for fabricating an intended type of semiconductor device (e.g., n-type or p-type semiconductor). Thereafter, substrate 50, on which the epitaxial material is located, is patterned to fabricate semiconductor fins 64 comprising the epitaxial material.

[0020] In another example, a dielectric layer may be formed over a top surface of a substrate; trenches may be etched through the dielectric layer; homoepitaxial structures may be epitaxially grown in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer and form fins.

[0021] In yet another example, a dielectric layer may be formed over a top surface of a substrate; trenches may be etched through the dielectric layer; heteroepitaxial structures may be epitaxially grown in the trenches using a material different from that of the substrate; and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer and form fins.

[0022] In embodiments where one or more epitaxial materials or epitaxial structures (e.g., the heteroepitaxial structures or the homoepitaxial structures) are grown, the one or more grown materials may be doped in situ during growth, eliminating the need for prior or subsequent implantations, although in situ and implantation doping may be used together. Furthermore, it may be advantageous to epitaxially grow a material in an NMOS region that is different from the material in a PMOS region. In various embodiments, the fins 64 may comprise silicon germanium (SixGe1-x, where x may be about 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.Available materials for making the III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP and the like.

[0023] Fig. 5 illustrates the formation of a dummy gate structure 75 over the semiconductor fins 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fins 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multilayers thereof, or the like, and may be deposited or thermally grown.

[0024] A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as with CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed from polysilicon, for example, although other materials may also be used. The mask layer may be formed from silicon nitride or the like, for example.

[0025] After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) have been formed, the mask layer may be patterned using suitable photolithography and etching techniques to form the mask 70. The pattern of the mask 70 may then be transferred to the gate layer and the dielectric layer using a suitable etching technique to form the gate electrode 68 and the gate dielectric 66, respectively. The gate electrode 68 and the gate dielectric 66 cover respective channel regions of the semiconductor fins 64. The gate electrode 68 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective semiconductor fins 64.

[0026] In the example of Fig. 5 shows that the gate dielectric 66 is formed over the fins 64 (e.g., over top surfaces and sidewalls of the fins 64) and over the STI regions 62. In other embodiments, the gate dielectric 66 may be formed, for example, by thermally oxidizing a material of the fins 64, and may therefore be formed over the fins 64 but not over the STI regions 62.

[0027] Fig. 6, 7A and 8-15 show the sectional views of the further processing of the FinFET device 100 along the cross section AA (along a longitudinal axis of the fin 64). It should be noted that in the Fig. 6, Fig. 7A and Fig. 8, three dummy gate structures 75 (e.g., 75A, 75B, and 75C) may be fabricated over fin 64. Those skilled in the art will appreciate that more or fewer than three gate structures may be fabricated over fin 64.

[0028] As in Fig. 6, lightly doped drain (LDD) regions 65 are formed in the fins 64. The LDD regions 65 may be formed using a plasma doping process. The plasma doping process may include forming and patterning masks, such as a photoresist, to cover the regions of the FinFET to be protected from the plasma doping process. Using the plasma doping process, n-type or p-type dopants may be implanted into the fins 64 to form the LDD regions 65. For example, p-type dopants, such as boron, may be implanted into the fin 64 to form the LDD regions 65 for a p-type device. In another example, n-type dopants, such as phosphorus, may be implanted into the fin 64 to form the LDD regions 65 for an n-type device. In some embodiments, the LDD regions 65 are adjacent to the channel region of the FinFET device 100.Portions of the LDD regions 65 may extend below the gate electrode 68 and into the channel region of the FinFET device 100. Fig. 6 shows a non-limiting example of the LDD regions 65. Other configurations, shapes, and manufacturing methods of the LDD regions 65 are also possible. For example, the LDD regions 65 may be formed after the gate spacers 87 have been formed. In some embodiments, the LDD regions 65 are omitted. For simplicity, the LDD regions 65 are not illustrated in the subsequent figures, it being understood that the LDD regions 65 may be formed in the fin 64.

[0029] Continue in Fig. 6, after the LDD regions 65 have been formed, gate spacers 87 are formed around the dummy gate structures 75. The gate spacer 87 may include a first gate spacer 72 and a second gate spacer 86. For example, the first gate spacer 72 may be a gate sealing spacer and may be formed on opposite sidewalls of the gate electrode 68 and on opposite sidewalls of the gate dielectric 66. The second gate spacer 86 is formed on the first gate spacer 72. The first gate spacer 72 may be formed from a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof, and may be formed, for example, using thermal oxidation, CVD, or another suitable deposition process.The second gate spacer 86 may be formed from silicon nitride, silicon carbonitride, a combination thereof, or the like using a suitable deposition process. In one embodiment, the first gate spacer 72 is formed from silicon nitride, and an atomic ratio between silicon and nitride (e.g., a ratio between the atomic percentages of silicon and nitride) is between about 0.7 and about 1.3.

[0030] In one embodiment, the gate spacer 87 is formed by first conformally depositing a first gate spacer layer over the FinFET device 100 and then conformally depositing a second gate spacer layer over the deposited first gate spacer layer. An anisotropic etch process, such as a dry etch process, is then performed to remove a first portion of the second gate spacer layer disposed on upper surfaces of the FinFET device 100 (e.g., the upper surface of the mask 70), while leaving a second portion of the second gate spacer layer disposed along sidewalls of the gate structures. The second portion of the second gate spacer layer remaining after the anisotropic etch process forms the second gate spacer 86.The anisotropic etching process also removes a portion of the first gate spacer layer located outside the sidewalls of the second gate spacers 86, and the remaining portion of the first gate spacer layer forms the first gate spacer 72.

[0031] The shapes and manufacturing processes of the gate spacer 87 as shown in Fig. 6 are merely non-limiting examples; other shapes and manufacturing methods are also possible.

[0032] Then in Fig. 7A, recesses are formed in the fins 64 adjacent to the dummy gate structures 75, for example, between adjacent dummy gate structures 75 and / or adjacent to a dummy gate structure 75. Source / drain regions 80 are then formed in the recesses. The recesses are formed, for example, using an anisotropic etch process in some embodiments, using the dummy gate structures 75 and the gate spacers 87 as an etch mask. However, any other suitable etch process may also be used.

[0033] Then, as in Fig. 7A, the source / drain regions 80 are formed in the recesses. The source / drain regions 80 are formed by epitaxially growing a material in the recesses using suitable techniques such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof.

[0034] As in Fig. As shown in Figure 7A, the epitaxial source / drain regions 80 may have surfaces that are raised relative to the respective surfaces of the fins 64 (e.g., raised relative to the non-recessed top surface 64U of the fins 64), and they may have facets. The source / drain regions 80 of the adjacent fins 64 may merge to form a contiguous epitaxial source / drain region 80 (see Fig. 7B). In some embodiments, the source / drain regions 80 of the adjacent fins 64 do not merge together and remain separate source / drain regions 80 (see Fig. 7C). In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain regions 80 comprise silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), or the like. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain regions 80 comprise SiGe and a p-type dopant, such as boron or indium.

[0035] The epitaxial source / drain regions 80 may be implanted with dopants to form source / drain regions 80, followed by an annealing process. The implantation process may include fabricating and patterning masks, such as a photoresist, to cover the regions of the FinFET device 100 that are to be protected from the implantation process. The source / drain regions 80 may have a dopant concentration (e.g., dopant concentration) in a range of approximately 1E19 cm -3 up to about 1E21 cm-3 P-type dopants, such as boron or indium, may be implanted into the source / drain region 80 of a p-type transistor. N-type dopants, such as phosphorus or arsenide, may be implanted into the source / drain regions 80 of an n-type transistor. In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

[0036] Then, as in Fig. 8, a contact etch stop layer (CESL) 89 is formed over the Fig. 7A. The CESL 89 functions as an etch stop layer in a subsequent etch process and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be formed using a suitable manufacturing method such as CVD, PVD, combinations thereof, or the like.

[0037] Then, a first interlayer dielectric (ILD) 90 is formed over the CESL 89 and over the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first ILD 90 is formed from a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited using any suitable method such as CVD, PECVD, or FCVD. A planarization process such as CMP may be performed to remove the mask 70 and to remove portions of the CESL 89 disposed over the gate electrode 68. After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0038] Then in Fig. 9, a gate-last process (sometimes referred to as a replacement gate process) is performed to replace the gate electrode 68 and the gate dielectric 66 with an active gate (may also be referred to as a replacement gate or a metal gate) and one or more active gate dielectric materials, respectively. Therefore, the gate electrode 68 and the gate dielectric 66 in a gate-last process may be referred to as a dummy gate electrode and a dummy gate dielectric, respectively.

[0039] In Fig. 9, the dummy gate structures 75A, 75B and 75C (see Fig. 8) are replaced by replacement gate structures 97A, 97B, and 97C, respectively. The replacement gate structures 97 (e.g., 97A, 97B, and 97C) may also be referred to as metal gate structures. According to some embodiments, to form the replacement gate structures 97 (e.g., 97A, 97B, or 97C), the gate electrode 68 and the gate dielectric 66 directly beneath the gate electrode 68 are removed in one or more etch steps, such that recesses (not shown) are formed between the gate spacers 87. Each recess exposes the channel region of a respective fin 64. During dummy gate removal, the gate dielectric 66 may be used as an etch stop layer when the gate electrode 68 is etched. The gate dielectric 66 may then be removed after the gate electrode 68 has been removed.

[0040] Then, a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 99 are formed in the recesses for the replacement gate structures 97. The gate dielectric layer 94 is conformally deposited in the recesses, such as on the top surfaces and sidewalls of the fins 64 and on sidewalls of the gate spacers 87, and on a top surface of the first ILD 90 (not shown). According to some embodiments, the gate dielectric layer 94 comprises silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, the gate dielectric layer 94 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.The methods for forming the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.

[0041] Then, the barrier layer 96 is conformally formed over the gate dielectric layer 94. The barrier layer 96 may comprise an electrically conductive material, such as titanium nitride, although other materials, such as tantalum nitride, titanium, tantalum, or the like, may alternatively be used. The barrier layer 96 may be formed using a CVD process, such as PECVD. However, other alternative processes, such as sputtering, metal organic chemical vapor deposition (MOCVD), or ALD, may alternatively be used.

[0042] Then, in some embodiments, the work function layer 98, such as a p-type work function layer or an n-type work function layer, may be deposited in the recesses above the barrier layers 96 and before the gate electrode 99 is formed. Example p-type work function metals that may be incorporated into the gate structures for p-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may be incorporated into the gate structures for n-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.A work function value is associated with the material composition of the work function layer, and consequently, the material of the work function layer is selected to tune its work function value to achieve a desired threshold voltage Vt in the device to be fabricated. The one or more work function layers can be deposited by CVD, physical vapor deposition (PVD), and / or another suitable process.

[0043] Then, a seed layer (not shown) is conformally formed over the work function layer 98. The seed layer may comprise copper, titanium, tantalum, titanium nitride, tantalum nitride, the like, or a combination thereof, and may be deposited by ALD, sputtering, PVD, or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers of different materials. For example, the seed layer comprises a titanium layer and a copper layer over the titanium layer.

[0044] The gate electrode 99 is then deposited over the seed layer and fills the remaining portions of the recesses. The gate electrode 99 may be formed from a metal-containing material, such as Cu, Al, W, the like, combinations thereof, or multilayers thereof, and may be deposited by, for example, electroplating, electroless plating, or another suitable method. After forming the gate electrode 99, a planarization process, such as CMP, may be performed to remove the excess portions of the gate dielectric layer 94, the barrier layer 96, the work function layer 98, the seed layer, and the gate electrode 99, which excess portions are above the top surface of the first ILD 90.The resulting remaining portions of the gate dielectric layer 94, the barrier layer 96, the work function layer 98, the seed layer, and the gate electrode 99 thus form the replacement gate structure 97 of the resulting FinFET device 100.

[0045] In Fig. 10, an etch stop layer 105 is formed (e.g., selectively) on the top surface of the first ILD 90. The etch stop layer 105 may be a suitable dielectric material, such as silicon nitride or silicon oxynitride, deposited on the top surface of the first ILD 90 by, for example, CVD, ALD, combinations thereof, or the like. For example, a patterned mask layer may be formed to cover the replacement gate structures 97 and the gate spacers 87 while exposing the first ILD 90, and the etch stop layer 105 is then formed over the exposed first ILD 90. After the etch stop layer 105 is formed, the patterned mask layer is removed. In another example, a top layer of the first ILD 90 may be converted into the etch stop layer 105, for example, by a nitridation process using a nitride-containing gas or a nitride-containing plasma.

[0046] Then, the replacement gate structures 97 are recessed to form recesses 103 between respective gate spacers 87. In some embodiments, a metal gate etchback process is performed to remove upper portions of the replacement gate structures 97, thereby forming recesses 103 between the spacers 87 after the metal gate etchback process. A suitable etching process, such as dry etching, wet etching, or combinations thereof, may be performed as the metal gate etchback process.

[0047] Continue in Fig. 10, after forming the recesses 103, a cap layer 101 is formed on the recessed replacement gate structures 97. In some embodiments, the cap layer 101 is formed from an electrically conductive material, such as tungsten, using a suitable deposition process, such as ALD, CVD, PVD, or the like. In the example of Fig. 10, the cap layer 101 extends continuously along the upper surface of the replacement gate structure 97 from an inner sidewall of a gate spacer 87 to an opposite inner sidewall of a respective gate spacer 87. In other words, in the illustrated embodiment, the upper surface of the replacement gate structures 97 is completely covered by the cap layer 101. In some embodiments, the cap layer 101 is omitted.

[0048] Then in Fig. 11 the recesses 103 are filled by a hybrid layer 108. As in Fig. As shown in Figure 11, a semiconductor material 107 (also referred to as a semiconductor deposit) is conformally formed along sidewalls and bottom surfaces of the recesses 103, and along the top surface of the etch stop layer 105. Then, a dielectric material 109 is formed over the semiconductor material 107 to fill the recesses 103. The dielectric material 109 may also be formed outside the recesses 103 over portions of the semiconductor material 107 between replacement gate structures 97. The semiconductor material 107 and the dielectric material 109 are collectively referred to as a hybrid layer 108.

[0049] In an exemplary embodiment, the semiconductor material 107 is amorphous silicon (a-Si) deposited by a suitable deposition process, such as LPCVD, PECVD, ALD, or the like, using a silicon-containing process gas, such as SiH4, Si2H6, SiH2Cl2, combinations thereof, or the like. A flow rate of the process gas may be between about 50 standard cubic centimeters per minute (sccm) and about 1000 sccm. A pressure of the deposition process may be between about 13 Pa (0.1 Torr) and about 1333 Pa (10 Torr), and a temperature of the deposition process may be between about 300°C and about 500°C. A thickness T of the semiconductor material 107, in one embodiment, is between about 0.3 nm and about 5 nm (e.g., 0.3 nm < T < 5 nm). In one embodiment, an atomic percentage (atomic %) of hydrogen in the semiconductor material 107 is less than about 15 atomic % (e.g., H < 15 atomic %).In the present discussion, the conformal semiconductor material 107 may also be referred to as a silicon deposit, although it is understood that other suitable material than the semiconductor material 107 may be used.

[0050] In an exemplary embodiment, the dielectric material 109 is silicon nitride deposited by a suitable manufacturing process, such as ALD, PECVD, LPCVD, or the like. An atomic ratio between silicon and nitride (e.g., atomic ratio of Si:N) in the dielectric material 109 is between about 0.7 and about 1.3. Besides silicon nitride (e.g., SiN), other suitable dielectric materials, such as silicon carbon nitride (SiCN), silicon carbon oxide nitride (SiCON), and silicon carbon oxide (SiCO), may be used as the dielectric material 109. In some embodiments, the dielectric material 109 is selected to be different from the one or more materials of the gate spacers 87 to provide etch selectivity in subsequent etch processes, such as in the etch process for forming openings 121 (see Fig. 13).

[0051] The deposited semiconductor material 107 may (or may not) include some crystalline structures, such as polycrystalline structures, having grains therein. Some grains may be interconnected, while some other grains may be buried in amorphous structures. The copper in, for example, the gate electrode 99 may diffuse upward along the grain boundaries to overlying layers that are subsequently formed. Therefore, in order to reduce the upward diffusion of copper, after the semiconductor material 107 is deposited, a treatment process (also referred to as an amorphization process) is performed to convert the polycrystalline structures (if any) in the semiconductor material 107 into amorphous structures, so that the entire semiconductor material 107 is amorphous. Because amorphous semiconductor material 107 has no grain boundaries, it can better prevent copper from diffusing through.In some embodiments, the treatment process is performed after forming the semiconductor material 107 and before forming the dielectric material 109.

[0052] According to some embodiments, the treatment process (e.g., a plasma process) for the deposited semiconductor material 107 is performed using a process gas comprising NH3, N2, or a combination thereof. Other gases, such as argon, may also be added. In the treatment process, the semiconductor material 107 is bombarded. The bombardment destroys the crystalline structures. Furthermore, if hydrogen and nitrogen atoms are present in the process gas (e.g., NH3), hydrogen and nitrogen may be incorporated into the semiconductor material 107. Accordingly, the semiconductor material 107 may be doped with hydrogen as a result of the treatment process. According to some embodiments, the semiconductor material 107 after the amorphization process has a hydrogen atomic percentage in the range between about 0.5 atomic % and about 10 atomic %.

[0053] According to some embodiments, the treatment process is or includes a plasma treatment, which may be a direct plasma process in which the plasma is generated in the same process chamber in which the FinFET device 100 is treated. The plasma treatment process is performed using both high-frequency radio frequency (HFRF) power (e.g., at a frequency of approximately 13.56 MHz) and low-frequency radio frequency (LFRF) power (e.g., at a frequency of approximately 350 kHz). The HFRF power is used for ionization and plasma generation, and the LFRF power is used to bombard the semiconductor material 107 for amorphization. According to some embodiments of the present invention, the HFRF power is in the range between approximately 50 watts and approximately 2000 watts.

[0054] The LFRF power is selected to be within a suitable range. If the LFRF power is too low (e.g., lower than about 90 watts), the amorphization process may not be effective. If the LFRF power is too high (e.g., higher than about 135 watts), layers / structures located beneath the semiconductor material 107 may be severely damaged by the plasma. According to some embodiments of the present invention, the LFRF power is selected to be in the range between about 90 watts and about 135 watts to avoid the aforementioned problems.

[0055] Then in Fig. 12, a planarization process, such as CMP, is performed to remove excess portions of the semiconductor material 107 and excess portions of the dielectric material 109, wherein excess portions are above the top surface of the first ILD 90. As in Fig. As shown in Figure 12, the planarization process also removes the etch stop layer 105 and upper portions of the gate spacers 87. After the planarization process, the remaining portions of the semiconductor material 107 and the dielectric material 109 disposed between (remaining portions of) the respective gate spacers 87 are referred to as hybrid layer structures 108.

[0056] Then, a second ILD 111 is formed over the first ILD 90, the gate spacers 87, and the hybrid layer structures 108. The second ILD 111 may be formed from the same or similar material using the same or similar fabrication process as the first ILD 90; thus, details are not repeated. The second ILD 111 may serve as an etch stop layer in a subsequent etch process.

[0057] Then, an etch stop layer stack 112 is formed over the second ILD 111 and patterned to include an opening 120 in the etch stop layer stack 112. In some embodiments, the etch stop layer stack 112 includes a plurality of layers (also referred to as sublayers), each of the plurality of layers being formed from a different material. In the example of Fig. 12, the etch stop layer stack 112 comprises a first layer 113, a second layer 115, and a third layer 117, which are successively formed over the second ILD 111. The first layer 113 is formed of tungsten-doped carbide (WDC, also known as tungsten-doped silicon carbide), the second layer 115 is formed of an oxide (e.g., silicon oxide), and the third layer 117 is formed of silicon (e.g., Si). The various materials of the sublayers of the etch stop layer stack 112 are combined to achieve a target level of etch selectivity for, for example, the subsequent etch process for forming openings 121 in Fig. 13 to be provided.

[0058] Then, the etch stop layer stack 112 is patterned to form an opening 120 in the etch stop layer stack 112. For example, a patterned mask layer 119 (e.g., a patterned photoresist layer) is formed over the etch stop layer stack 112, and an anisotropic etching process is then performed using the patterned mask layer 119 as an etch mask to pattern the patterned mask layer 119. The number and location of the opening 120 in Fig. 12 is merely a non-limiting example. Those skilled in the art will appreciate that different numbers of openings 120 may be formed at other locations. In some embodiments, the anisotropic etch process comprises a plurality of etching steps, wherein each of the etching steps uses a different etchant to selectively remove a sublayer of the etch stop layer stack 112. The anisotropic etch process may be stopped when the second ILD 111 is exposed. The patterned mask layer 119 (e.g., a patterned photoresist layer) may be removed, for example, by a stripping process after the opening 120 has been formed.

[0059] Then in Fig. 13, an etching process is performed to remove portions of the second ILD 111 and portions of the first ILD 90 located beneath the opening 120. After the etching process, openings 121 are formed in the first ILD 90, exposing the underlying source / drain regions 80. A depth D1 of the opening 121 may, for example, be between about 20 nm and about 80 nm. The etching process may be any suitable etching process, such as a dry etch (e.g., a plasma etching process), a wet etch, combinations thereof, or the like. The etching process may use an etchant that is selective toward the material (e.g., an oxide) of the first ILD 90 and the second ILD 111 (e.g., having a higher etch rate therefor), such that the first ILD 90 and the second ILD 111 are removed without significantly attacking other layers of the FinFET device 100. For example, etching processing using C x F y, H2, Ar, combinations thereof, or the like may be performed to remove the exposed portions of the first ILD 90 and the second ILD 111. In some embodiments, after the etching process for removing the exposed portions of the first ILD 90 and the second ILD 111, another etching process using an etchant selective to the material of the CESL 89 may be performed to remove the CESL 89 exposed through the openings 121 and to expose the source / drain regions 80. It should be noted that the portions of the first ILD 90 / second ILD 111 located below the opening 120 may be removed in preparation for fabricating the self-aligned contacts (SAC) 123 (see Fig. 14) must be completely removed.

[0060] In some embodiments, the etching process for forming the openings 121 also includes upper portions of the gate spacers 87 and upper portions of the hybrid layer structure 108 located below the opening 120 in Fig. 12 are removed. The hybrid layer structure 108 with its specific structure, dimension (e.g., 0.3 nm < T < 5 nm) and material composition (e.g., atomic percentage of H < 15 atomic % and the atomic ratio of Si:N between 0.7 and 1.3) provides good etch selectivity in the etching process for forming the openings 121, so that the hybrid layer structure 108 is etched at a slower speed than the gate spacers 87. In other words, the etching process for forming the openings 121 spares the hybrid layer structure 108 less than the gate spacers 87. In the example of Fig. 13, after completion of the etching process, the upper surface 87U of the gate spacer 87 is chamfered (e.g., tilted). For example, there is an offset D2 between a top edge of the upper surface 87U (which may be level with the top surface of the hybrid layer structure 108) and a bottom edge of the upper surface 87U. The offset D2 may, for example, be 10 nm or less. The unintentional removal (e.g., etching) of the hybrid layer structure 108 and the gate spacer 87 is referred to as a chopping effect.

[0061] The embodiment of the present invention, utilizing the hybrid layer structure 108, among other structural elements, significantly reduces the discontinuity effect, which in turn reduces product defects associated with the discontinuity effect. To understand the merit of the present invention, consider a reference design in which the hybrid layer structure 108 is replaced with a single layer of a dielectric material (e.g., silicon nitride). In other words, in the reference design, a single silicon nitride layer is formed over the replacement gate structure 97 and fills the space between respective gate spacers 87. The discontinuity effect would remove substantial portions of the single silicon nitride layer and the gate spacers 87.During subsequent processing to fill the openings 121 with a conductive material to create self-aligned contacts 123, the conductive material may fill gaps left by the removed portions of the single silicon nitride layer and the gate spacers 87, which may result in a short circuit (e.g., an unintended electrical connection) between the replacement gate structure 97 and the source / drain region 80, or between the source / drain regions 80 on opposite sides of the replacement gate structure 97. The present invention prevents or reduces the short-circuit defects caused by the open-circuit effect. The structure and method of the present invention have been implemented and tested in production, and measurements have confirmed that short-circuit defects caused by the open-circuit effect have been reduced by four orders of magnitude.

[0062] Then in Fig. 14, a conductive material is deposited in the openings 121 to fill the openings 121. The conductive material may be copper, cobalt, tungsten, combinations thereof, or the like, and may be deposited by a suitable manufacturing process, such as PVD, CVD, PECVD, ALD, or the like. A planarization process, such as CMP, is then performed to remove the etch stop layer stack 112 and the second ILD 111. The remaining portions of the conductive material in the openings 121 form self-aligned contacts 123. As shown in Fig. As shown in Figure 14, the first ILD 90, the hybrid layer structure 108, the gate spacers 87, and the self-aligned contacts 123 have a coplanar top surface after the planarization process.

[0063] Then in Fig. 15, an interconnect structure 148 is fabricated over the first ILD 90 to connect the underlying electrical components (e.g., the FinFETs) and to form functional circuits. The interconnect structure 148 includes a plurality of dielectric layers (e.g., 125, 129, 133) and conductive features (e.g., 141, 143, 145, 147) fabricated within the plurality of dielectric layers. It should be noted that in the present description, unless otherwise stated, conductive features and conductive materials refer to electrically conductive features and electrically conductive materials, respectively.

[0064] The dielectric layers 125 / 129 / 133 may also be referred to as inter-metal dielectric (IMD) layers. The IMD layers 125 / 129 / 133 may be formed from one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. The IMD layers 125 / 129 / 133 may be formed using a process such as chemical vapor deposition (CVD), although any suitable process may be used. The etch stop layers 127 and 131 may be formed between adjacent IMD layers.The etch stop layers 127 and 131 may be formed from silicon nitride using PECVD, although other dielectric materials, such as nitride, carbide, boride, combinations thereof, or the like, and alternative methods for forming the etch stop layers, such as LPCVD, PVD, or the like, may alternatively be used.

[0065] In Fig. 15, gate contacts 141 are formed to extend through the IMD layer 125, the dielectric material 109, and the semiconductor material 107 and to electrically connect to the replacement gate structures 97, for example, through the cap layer 101. In the example of Fig. 15, the bottom surface of the gate contact 141 physically contacts the top surface of the underlying cap layer 101 and extends along the top surface of the underlying cap layer 101. In addition, source / drain contacts 143 are formed to extend through the IMD layer 125 and electrically connect to the self-aligned contacts 123. Fig. 15 further shows conductive lines 145 and vias 147 formed in the IMD layers 129 and 133, respectively. The gate contacts 141, source / drain contacts 143, conductive lines 145, and via 147 are formed from one or more conductive materials (e.g., copper, tungsten, cobalt) and using a suitable process, such as a damascene, dual-damascene process, or the like. It should be noted that the number and locations of the conductive features in the interconnect structure 148 are illustrative only and are not limiting. Other conductive features may be formed at other locations. Furthermore, some conductive features may not be present in the cross-section of Fig. 15 and are therefore in Fig. 15 not visible (for example not shown).

[0066] Fig. 16 shows a flow diagram of a method 1000 for manufacturing a semiconductor device according to some embodiments. It is understood that the Fig. 16 is merely one example of many possible embodiments of the method. A person skilled in the art will recognize many variations, alternatives, and modifications. For example, various Fig. 16 steps shown can be added, removed, replaced, rearranged and repeated.

[0067] In Fig.16 In block 1010, a metal gate structure is formed over a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer. In block 1020, the metal gate structure is recessed below a top surface of gate spacers extending along opposite sidewalls of the metal gate structure, wherein, after the recessing, a recess is formed between the gate spacers. In block 1030, sidewalls and a bottom surface of the recess are populated with a semiconductor material. In block 1040, after populating, the recess is filled with a dielectric material.In block 1050, a patterned etch stop layer stack is formed over the dielectric material, the semiconductor material, and the ILD layer, with a first opening in the patterned etch stop layer stack directly over the dielectric material, the semiconductor material, and a first portion of the ILD layer adjacent to the gate spacers. In block 1060, a second opening is formed in the ILD layer by etching through the first opening to remove the first portion of the ILD layer, the second opening exposing a source / drain region adjacent to the metal gate structure. In block 1070, the second opening is filled with a conductive material.

[0068] Embodiments may offer advantages. For example, the disclosed structure and method reduce an open-circuit effect, thereby preventing or reducing device defects caused by short circuits due to the open-circuit effect. Measurements have confirmed that the defect rate caused by the open-circuit effect can be reduced by four orders of magnitude in production when using the disclosed structure and method.

[0069] According to one embodiment, a method for manufacturing a semiconductor device comprises: forming a metal gate structure over a semiconductor fin, wherein the metal gate structure is surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below a top surface of gate spacers extending along opposite sidewalls of the metal gate structure, wherein after the recessing, a recess is formed between the gate spacers; lining sidewalls and a bottom surface of the recess with a semiconductor material; after the lining, filling the recess with a dielectric material; forming a patterned etch stop layer stack by forming a first sublayer, a second sublayer, and a third sublayer sequentially over the dielectric material, the semiconductor material, and the ILD layer,wherein the first sublayer is formed of tungsten-doped silicon carbide, the second sublayer is formed of silicon oxide, and the third sublayer is formed of silicon, wherein a first opening in the patterned etch stop layer stack is directly above the dielectric material, the semiconductor material, and a first portion of the ILD layer adjacent to the gate spacers; forming a second opening in the ILD layer by etching through the first opening to remove the first portion of the ILD layer,wherein the second opening exposes a source / drain region adjacent to the metal gate structure; and filling the second opening with a conductive material. In one embodiment, the semiconductor material is amorphous silicon. In one embodiment, the dielectric material is silicon nitride. In one embodiment, the method further comprises, prior to recessing the metal gate structure: selectively forming an etch stop layer over a top surface of the ILD layer distal from the semiconductor fin, wherein a first portion of the semiconductor material contacts the etch stop layer and extends along the etch stop layer. In one embodiment, the method further comprises, after filling the recess and prior to forming the patterned etch stop layer stack: performing a planarization process,wherein the planarization process removes the first portion of the semiconductor material and the etch stop layer. In one embodiment, the method further comprises, after recessing and before populating: forming a cap layer over the metal gate structure, wherein the cap layer physically contacts the metal gate structure and the semiconductor material. In one embodiment, forming the second opening comprises: performing an etch process to remove the first portion of the ILD layer, wherein the etch process recesses the gate spacers more than the dielectric material and the semiconductor material. In one embodiment, forming the patterned etch stop layer stack comprises: forming an etch stop layer stack by forming a first sublayer, a second sublayer, and a third sublayer sequentially over the ILD layer, wherein the first sublayer,the second sublayer and the third sublayer comprise different materials; forming a patterned mask layer over the etch stop layer stack; and patterning the etch stop layer stack using the patterned mask layer as an etch mask. In one embodiment, after filling the second opening, the method further comprises: removing the patterned etch stop layer stack; forming an inter-metal dielectric (IMD) layer over the ILD layer; and forming a first via and a second via extending through the IMD layer, wherein the first via extends through the dielectric material and the semiconductor material and is electrically connected to the metal gate structure, wherein the second via is electrically connected to the conductive material.

[0070] According to one embodiment, a method of manufacturing a semiconductor device comprises: forming a first metal gate structure over a fin; forming a second metal gate structure over the fin and adjacent to the first metal gate structure, wherein the first metal gate structure and the second metal gate structure are surrounded by an interlayer dielectric (ILD) layer; recessing the first metal gate structure and the second metal gate structure to form a first opening between first gate spacers and a second opening between second gate spacers, respectively, wherein the first gate spacers are on opposite sidewalls of the first metal gate structure and the second gate spacers are on opposite sidewalls of the second metal gate structure; conformally forming a semiconductor material along sidewalls and bottom surfaces of the first opening and the second opening;Filling the first opening and the second opening by forming a dielectric material on the semiconductor material; Forming an etch stop layer stack over the ILD layer by sequentially forming a first layer of tungsten-doped silicon carbide, a second layer of silicon oxide, and a third layer of silicon;and forming a self-aligned contact between the first metal gate structure and the second metal gate structure, the self-aligned contact being electrically connected to an underlying source / drain region between the first metal gate structure and the second metal gate structure. In one embodiment, forming the self-aligned contact after filling the first opening and the second opening comprises: forming an etch stop layer stack over the ILD layer, the etch stop layer stack comprising a plurality of layers, each of the plurality of layers being made of a different material; forming a first opening in the etch stop layer stack over the first metal gate structure and over a first portion of the ILD layer between the first metal gate structure and the second metal gate structure;Removing the first portion of the ILD layer to form a second opening in the ILD layer, the second opening exposing the underlying source / drain region; and filling the second opening with a conductive material, the conductive material extending continuously from the first metal gate structure to the second metal gate structure. In one embodiment, the semiconductor material is amorphous silicon, and the dielectric material is silicon nitride. In one embodiment, the method further comprises, after recessing and before conformally forming the semiconductor material: forming a conductive capping layer on the first metal gate structure and on the second metal gate structure. In one embodiment, the conductive material contacts a top surface of the conductive capping layer distal from the fin and extends along the top surface of the conductive capping layer distal from the fin.

[0071] According to one embodiment, a method of manufacturing a semiconductor device comprises: forming a fin that protrudes above a substrate; forming a metal gate over the fin, wherein the metal gate is surrounded by a dielectric layer; etching the metal gate to reduce a height of the metal gate, wherein after the etching, a recess is formed above the metal gate between gate spacers of the metal gate; lining sidewalls and a bottom surface of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming an etch stop layer stack over the ILD layer by sequentially forming a first layer of tungsten-doped silicon carbide, a second layer of silicon oxide, and a third layer of silicon;Forming a patterned mask layer over the metal gate and the dielectric layer, wherein a first opening of the patterned mask layer is directly over a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, the second opening exposing an underlying source / drain region; and filling the second opening with a conductive material. In one embodiment, the semiconductor material is amorphous silicon, and the dielectric material is silicon nitride. In one embodiment, the method further comprises, after etching the metal gate and before populating: selectively forming a cap layer on the metal gate. In one embodiment, the second opening exposes a sidewall of the gate spacers.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Forming a metal gate structure (97) over a semiconductor fin (64), wherein the metal gate structure (97) is surrounded by an ILD layer (90); selectively forming an etch stop layer (105) over a top surface of the ILD layer (90) distal from the semiconductor fin (64); recessing the metal gate structure (97) below an upper surface of gate spacers (87) extending along opposite sidewalls of the metal gate structure (97), wherein after the recessing a recess (103) is formed between the gate spacers (87); lining side walls and a bottom of the recess (103) with a semiconductor material (107), wherein a first part of the semiconductor material (107) contacts the etch stop layer (105) and extends along the etch stop layer (105); after lining, filling the recess (103) with a dielectric material (109); Forming a patterned etch stop layer stack over the dielectric material (109), the semiconductor material (107) and the ILD layer (90), wherein a first opening (120) in the patterned etch stop layer stack (112) is directly over the dielectric material (109), the semiconductor material (107) and a first portion of the ILD layer (90) adjacent to the gate spacers (87); Forming a second opening (121) in the ILD layer (90) by etching through the first opening (120) to remove the first portion of the ILD layer (90), the second opening (121) exposing a source / drain region (80) adjacent to the metal gate structure (97); and Filling the second opening (121) with a conductive material (123). [2] The method of claim 1, wherein the semiconductor material (107) is amorphous silicon. [3] The method of claim 1 or 2, wherein the dielectric material (109) is silicon nitride. [4] The method of claim 1, further comprising, after filling the recess (103) and before forming the patterned etch stop layer stack (112): Performing a planarization process, wherein the planarization process removes the first part of the semiconductor material (107) and the etch stop layer (105). [5] A method according to any one of the preceding claims, further comprising: after the recessing and before the lining: Forming a cap layer (101) over the metal gate structure (97), wherein the cap layer (101) physically contacts the metal gate structure (97) and the semiconductor material (107). [6] A method according to any one of the preceding claims, wherein forming the second opening (121) comprises: Performing an etching process to remove the first portion of the ILD layer (90), wherein the etching process spares more of the gate spacers (87) than the dielectric material (109) and the semiconductor material (107). [7] Method according to one of the preceding claims, wherein the formation of the structured etch stop layer stack (112) comprises: Forming an etch stop layer stack (112) by forming a first sublayer (113), a second sublayer (115) and a third sublayer (117) sequentially over the ILD layer (90), wherein the first sublayer (113), the second sublayer (115) and the third sublayer (117) contain different materials; Forming a patterned mask layer (119) over the etch stop layer stack (112); and Patterning the etch stop layer stack (112) using the patterned mask layer (119) as an etch mask. [8] The method of claim 7, wherein the first sublayer is formed of tungsten-doped silicon carbide, the second sublayer is formed of silicon oxide, and the third sublayer is formed of silicon. [9] A method according to any one of the preceding claims, further comprising, after filling the second opening (121): Removing the patterned etch stop layer stack (112); Forming an IMD layer (125, 129, 133) over the ILD layer (90); and Forming a first via and a second via extending through the IMD layer (125, 129, 133), the first via extending further through the dielectric material (109) and the semiconductor material (107) and being electrically connected to the metal gate structure (97), the second via being electrically connected to the conductive material (123). [10] A method of manufacturing a semiconductor device, comprising: Forming a first metal gate structure (97B) over a fin (64); Forming a second metal gate structure (97A) over the fin (64) and adjacent to the first metal gate structure (97B), wherein the first metal gate structure (97B) and the second metal gate structure (97A) are surrounded by an ILD layer (90); selectively forming an etch stop layer (105) over a top surface of the ILD layer (90) distal from the fin (64); recessing the first metal gate structure (97B) and the second metal gate structure (97A) to form a first opening (103) between first gate spacers (87) and a second opening (103) between second gate spacers (87), wherein the first gate spacers (87) are on opposite sidewalls of the first metal gate structure (97B) and the second gate spacers (87) are on opposite sidewalls of the second metal gate structure (97A); conformally forming a semiconductor material (107) along sidewalls and bottom surfaces of the first opening (103) and the second opening (103), wherein a first portion of the semiconductor material (107) contacts the etch stop layer (105) and extends along the etch stop layer (105); Filling the first opening (103) and the second opening (103) by forming a dielectric material (109) on the semiconductor material (107; and Producing a self-aligned contact (123) between the first metal gate structure (97B) and the second metal gate structure (97A), wherein the self-aligned contact (123) is electrically connected to an underlying source / drain region (80) between the first metal gate structure (97B) and the second metal gate structure (97A). [11] The method of claim 10, wherein manufacturing the self-aligned contact (123) after filling the first opening (103) and the second opening (103) further comprises: Forming an etch stop layer stack (112) over the ILD layer (90), wherein the etch stop layer stack (112) comprises a plurality of layers (113, 115, 117), each of the plurality of layers (113, 115, 117) being formed from a different material; Forming a first opening (120) in the etch stop layer stack (112) over the first metal gate structure (97B) and over a first portion of the ILD layer (90) between the first metal gate structure (97B) and the second metal gate structure (97A); Removing the first portion of the ILD layer (90) to form a second opening (121) in the ILD layer (90), the second opening (121) exposing the underlying source / drain region (80); and Filling the second opening (121) with a conductive material (123), wherein the conductive material (123) extends continuously from the first metal gate structure (97B) to the second metal gate structure (97A). [12] The method of claim 11, wherein forming the etch stop layer stack comprises: Forming a first layer of tungsten-doped silicon carbide over the ILD layer; Forming a second layer of silicon oxide over the first layer; and Forming a third layer of silicon over the second layer. [13] A method according to any one of claims 10 to 12, wherein the semiconductor material (107) is amorphous silicon and the dielectric material (109) is silicon nitride. [14] The method of any one of claims 10 to 13, further comprising, after said recessing and before said conformal forming of said semiconductor material (107): Forming a conductive cap layer (101) on the first metal gate structure (97B) and on the second metal gate structure (97A). [15] The method of claim 14, wherein the conductive material (141) contacts a top surface of the conductive cap layer (101) distal from the fin (64) and extends along the top surface of the conductive cap layer (101) distal from the fin (64). [16] A method of manufacturing a semiconductor device, comprising: forming a fin (64) projecting beyond a substrate (50); Forming a metal gate (97) over the fin (64), the metal gate (97) being surrounded by a dielectric layer (90); selectively forming an etch stop layer (105) over a top surface of the ILD layer (90) distal from the fin (64); Etching the metal gate (97) to reduce a height of the metal gate (97), wherein after the etching, a recess (103) is formed above the metal gate (97) between gate spacers (87) of the metal gate (97); lining side walls and a bottom of the recess (103) with a semiconductor material (107), wherein a first part of the semiconductor material (107) contacts the etch stop layer (105) and extends along the etch stop layer (105); Filling the recess (103) by forming a dielectric material (109) over the semiconductor material (107); Forming a patterned mask layer (119) over the metal gate (97) and the dielectric layer (109), wherein a first opening (120) of the patterned mask layer (119) is disposed directly over a portion of the dielectric layer (90) adjacent to the metal gate (97); Removing the portion of the dielectric layer (90) to form a second opening (121) in the dielectric layer (90), the second opening (121) exposing an underlying source / drain region (80); and Filling the second opening (121) with a conductive material (123). [17] The method of claim 16, wherein the semiconductor material (107) is amorphous silicon and the dielectric material (109) is silicon nitride. [18] The method of claim 16 or 17, further comprising, after etching the metal gate (97) and before lining: selectively forming a cover layer (101) on the metal gate (97). [19] The method of any one of claims 16 to 18, wherein the second opening (121) exposes a sidewall of the gate spacers (87).

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