Ferroelectric semiconductor junction field effect transistor, preparation method and application

Abstract

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new semiconductor devices, in particular to a ferroelectric semiconductor junction field effect transistor, a preparation method and application. BACKGROUND

[0002] Inspired by the working principle of human brain, neuromorphic computing technology has made important breakthroughs in recent years and has become one of the effective alternatives to make up for the shortcomings of traditional digital computing in power and delay. Neuromorphic hardware, such as field effect transistors, ferroelectric transistors and resistive random access memories, provides a platform for developing diversified neuromorphic architectures to achieve efficient computing and storage operations. In order to build an intelligent computing system that can perform multiple tasks, it is crucial to design homogeneous devices with reconfigurable functions to improve the integration level of modules.

[0003] Two-dimensional materials have atomic thickness and adjustable electrical properties, and can realize reconfigurable switching of multiple functions through material stacking, quickly respond to multi-channel signals, and meet the requirements of neuromorphic chips for low power consumption, compactness and high functional density. At present, the research on reconfigurable devices based on two-dimensional materials involves single-gate transistors (such as ferroelectric transistors, ionic transistors, gradient-doped transistors), multi-gate adjustment, semi-floating gate and other complex structures. Although these two-dimensional reconfigurable devices have made progress in integrating multiple functions to achieve neural network applications, there are still the following problems to be solved:

[0004] (1) Contradiction between functional density and structural complexity. Integrating multiple functions through multi-layer material or gate dielectric stacking will significantly affect the performance of the device due to interface effects and process, leading to unstable performance and complex preparation process, thereby limiting the improvement of functional density.

[0005] (2) Difficulty in integrating reconfigurable logic and synaptic function in a single device. Logic function requires clear 0 / 1 digital state switching, and the voltage of 0 / 1 state needs to be stable in the corresponding state; while synaptic function requires triggering multiple intermediate states by applying a pulse voltage, and the state can be temporarily retained after removing the voltage to support subsequent computing operations. The working mechanisms of the two are significantly different, and it is difficult to seamlessly integrate them in the same device.

[0006] (3) Complexity of function switching method. Devices integrating multiple functions usually require complex switching methods, such as ultraviolet or visible light irradiation, which limits the practical application of the device. SUMMARY

[0007] The present application aims to overcome the shortcomings of the prior art and provides a ferroelectric semiconductor junction field effect transistor, a preparation method and application.

[0008] The application aims to realize the above-mentioned purpose by the following technical scheme: a ferroelectric semiconductor junction field effect transistor, comprising a source electrode, a drain electrode, a control gate, a channel layer, a ferroelectric gate layer, an insulating isolation layer and a substrate.

[0009] The insulating isolation layer is covered on the surface of the substrate, the ferroelectric gate layer is arranged above the insulating isolation layer, and the channel layer and the ferroelectric gate layer are stacked to form a longitudinal heterojunction structure.

[0010] The control gate is arranged at one end of the ferroelectric gate layer and used for applying a gate voltage to regulate the polarization state of the ferroelectric layer, and the source electrode and the drain electrode are arranged at two ends of the channel layer respectively to form a path for carrier injection and collection.

[0011] Further, the channel layer adopts a two-dimensional transition metal sulfide semiconductor material, specifically one of WSe2, MoTe2, WS2 and ReS2, and the thickness is 3-10 nm.

[0012] Further, the ferroelectric gate layer adopts a two-dimensional ferroelectric semiconductor material, specifically one of In2Se3, InSe and SnSe, and the thickness is 40-80 nm.

[0013] Further, the source electrode, the drain electrode and the control gate are all metal Au electrodes, and the thickness is 40-80 nm.

[0014] The insulating isolation layer is an oxide layer, which is a SiO2 layer with a thickness of 50 nm, and the substrate is a highly doped p-type or n-type silicon substrate.

[0015] According to another aspect of the specification, the application further provides a method for preparing the transistor, comprising:

[0016] Step one: substrate cleaning: a p-type silicon (Si) substrate with a 50 nm thick silicon dioxide (SiO2) layer on the surface and a resistivity of 0.001-0.005 Ω·cm is prepared, the substrate surface is cleaned to remove impurities, and the adhesion of subsequent material transfer is ensured.

[0017] Step two: ferroelectric gate layer and channel layer material selection: a tape-assisted mechanical exfoliation method is used to exfoliate In2Se3 and MoTe2 from the bulk crystal of two-dimensional ferroelectric n-type semiconductor In2Se3 and two-dimensional p-type semiconductor MoTe2 to a polydimethylsiloxane substrate (PMDS). The long strip-shaped flakes with a thickness, size and shape meeting the requirements are selected by an optical microscope, wherein the width is 3-10 μm, the length is 15-30 μm, the thickness of the selected In2Se3 is 40-80 nm, and the thickness of the selected MoTe2 is 3-10 nm.

[0018] Step three: ferroelectric gate layer transfer: In2Se3 flakes are preferentially transferred to the surface of the p-type Si / SiO2 substrate by the transfer platform. The peeled In2Se3 flakes are smoothly transferred to the central region of the substrate by the PDMS, and the flakes are tightly attached to the substrate.

[0019] Step four: channel layer transfer: MoTe2 material is accurately transferred to the surface of the ferroelectric gate layer In2Se3 by PDMS, and the two long strip-shaped materials are stacked in a cross shape, forming a channel layer / ferroelectric gate layer heterojunction.

[0020] Step five: electrode preparation: long strip-shaped electrode patterns are patterned at both ends of the channel layer and one end of the ferroelectric gate layer by photolithography, and then metal gold electrodes are prepared by thermal evaporation and metal stripping process, forming source, drain and control gate. According to another aspect of the specification, the application also provides an application of the ferroelectric semiconductor junction field effect transistor as a light sensor, a memory, a heterosynaptic device and a self-switching logic.

[0021] Further, the application of the ferroelectric semiconductor junction field effect transistor as a light sensor specifically includes: in a completely dark environment, a scanning bias of -1 V to 1 V is applied between the source or drain and the control gate, and the heterojunction dark state current is collected; a light spot illuminator is introduced to the active area of the device, and the photocurrent signal under different light intensities is measured synchronously by adjusting the light intensity.

[0022] Further, the application of the ferroelectric semiconductor junction field effect transistor as a memory specifically includes: by applying a programming electric pulse of ±20 V to the substrate for 5 s, the polarization direction of the ferroelectric gate layer is switched; a read voltage is applied between the source and the drain, and data storage is realized according to the high and low resistance states of the channel layer current, wherein high current corresponds to low resistance state "1", and low current corresponds to high resistance state "0".

[0023] Further, the application of the ferroelectric semiconductor junction field effect transistor in a heterosynaptic device specifically includes:

[0024] The source and the drain are used as post-synaptic current reading ends, and the substrate is used as a weight modulation end; before testing, the ferroelectric gate layer is initialized to a polarization upward state, and under a fixed source-drain bias, a sequence of -10~10 V electric pulses is applied to the substrate.

[0025] Negative electric pulses induce enhancement of post-synaptic current, and positive electric pulses cause inhibition of post-synaptic current.

[0026] By adjusting the pulse parameters, the channel layer realizes continuous modulation of multiple conductance states, simulating the short-term / long-term memory conversion function of biological synapses.

[0027] Furthermore, the application of the ferroelectric semiconductor junction field effect transistor to realize self-switching logic specifically includes:

[0028] First, a ±20 V, 5 s electric pulse is applied through the substrate to pre-program the polarization direction of the ferroelectric gate layer; the substrate gate voltage is used as the INA port, the control gate voltage is used as the INB port, and the current in the channel layer is used as the output:

[0029] When the polarization direction is upward, only inputting "00" corresponds to low current outputting "0", realizing "NOR" logic;

[0030] When the polarization direction is downward, only the input "11" corresponds to the high current output "1", realizing the "NAND" logic.

[0031] The beneficial effects of the present invention are: a compact new device structure is constructed through the coupling mechanism of two-dimensional material heterojunction and ferroelectric semiconductor, avoiding the interface effects and process complexity caused by multi-layer material or gate dielectric stacking, significantly improving device performance stability and simplifying the preparation process, laying the foundation for high functional density integration;

[0032] By leveraging the synergistic effect of the unique ferroelectric polarization storage properties of ferroelectric semiconductor materials and the transport properties of semiconductors, a single device can simultaneously achieve the stable switching of the 0 / 1 digital state required for logic operations and the pulse-triggered multiple intermediate state storage required for synaptic simulation, breaking through the functional integration bottleneck caused by differences in the working mechanisms of traditional devices.

[0033] The reconfigurable function switching method based on electrical control does not rely on external stimulation conditions such as ultraviolet light. By applying different forms of voltage signals, it can realize convenient switching of logic, storage, synaptic, light detection and other functions. It can also achieve the transport characteristics of junction field-effect transistors with no hysteresis and steep subthreshold swing, significantly improving the flexibility and applicability of the device in practical applications.

[0034] The device structure combines low power consumption characteristics with multi-functional integration capabilities, which can meet the needs of neuromorphic computing systems for highly integrated, low-energy intelligent hardware, and provide core device support for the development of the next generation of reconfigurable intelligent computing chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of the structure of a two-dimensional ferroelectric semiconductor junction field effect transistor (FeJFET);

[0036] Figure 2 is an optical microscope image of a FeJFET made of In2Se3 / MoTe2;

[0037] Figure 3 shows the transfer and output electrical characteristic curves of FeJFET;

[0038] Figure 4 shows the photoresponse electrical curves of the FeJFET as a photodetector at different optical power densities under 808 nm laser, as well as the electrical curves at different laser wavelengths under the same optical power density.

[0039] Figure 5 shows the storage resistance state retention characteristic curve and fatigue resistance test curve in FeJFET storage function applications;

[0040] Figure 6 shows the characteristic curves of FeJFET synaptic function applications as the number of electric pulses changes, and the long-term potentiation-long-term depression characteristic curves;

[0041] FIG7 is a schematic diagram showing the structure of the input and output terminals of a device for applying FeJFET self-switching logic functions;

[0042] Figure 8 shows the characteristic curves of the "NOR" and "NAND" logic functions implemented in the FeJFET self-switching logic function application. DETAILED DESCRIPTION

[0043] The following are specific embodiments of the present invention, which further illustrate the present invention. It should be understood that these embodiments are intended to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content of the present invention, those skilled in the art may make various changes or modifications to the present invention, and these equivalents fall within the scope defined by the appended claims of the application.

[0044] Example 1

[0045] like Figure 1 As shown, an embodiment of the present invention provides a ferroelectric semiconductor junction field-effect transistor (FeJFET), whose core structure includes: source and drain electrodes 1, a control gate 2, a channel layer 3, a ferroelectric gate layer 4, an oxide layer 5, and a substrate 6. The spatial arrangement and functional division of each structural layer are clear: the oxide layer 5 completely covers the surface of the substrate 6, serving as an insulating isolation layer; the ferroelectric gate layer 4 is stacked above the oxide layer 5, forming the ferroelectric control core of the device; the channel layer 3 and the ferroelectric gate layer 4 are further stacked to form a longitudinal heterojunction structure, in which the channel layer 3 serves as a carrier transport channel and the ferroelectric gate layer 4 serves as a polarization control unit; the control gate 2 is only provided at one end of the ferroelectric gate layer 4, for applying a gate voltage to control the polarization state of the ferroelectric layer; the source and drain electrodes 1 are symmetrically provided at both ends of the channel layer 3, forming paths for carrier injection and collection. This structural design has the significant advantage of integrating optical signal sensing, data storage, synaptic computing, and self-switching logic functions into a single transistor, achieving multifunctional integration.

[0046] From the material selection, the channel layer 3 adopts a two-dimensional transition metal sulfide semiconductor material, which can be selected from WSe2, MoTe2, WS2, ReS2, and the thickness is controlled in the range of 3 to 10 nm, which can ensure the quantum confinement effect of the two-dimensional material and maintain good carrier mobility;

[0047] The ferroelectric gate layer 4 adopts a two-dimensional ferroelectric semiconductor material, which can be selected from In2Se3, InSe, SnSe, and the thickness is 40 to 80 nm, which can ensure stable ferroelectric polarization characteristics and facilitate voltage regulation;

[0048] The source and drain 1 and the control gate 2 both adopt a metal Au electrode with a thickness of 40 to 80 nm, which has good ohmic contact between the Au electrode and the two-dimensional material, and can reduce the contact resistance;

[0049] The oxide layer 5 is a SiO2 layer with a thickness of 50 nm, which is used as an insulating medium to effectively isolate the substrate and the upper layer structure;

[0050] The substrate 6 is a highly doped p-type or n-type silicon substrate, which not only provides structural support, but also can be used as a back gate electrode to assist in regulating the channel.

[0051] The core innovation of the present application lies in the uniqueness of the device structure and the regulation mechanism. Unlike the existing technology, the source and drain 1 of the present application are located on the same material channel layer 3, and the two-dimensional ferroelectric semiconductor material such as In2Se3 is used as the ferroelectric gate layer 4 to bear the voltage applied by the control gate 2. This design changes the regulation mechanism of the device, and through the polarization direction switching of the ferroelectric gate layer 4, the carrier depletion and accumulation state of the channel layer 3 can be dynamically regulated, rather than the single heterojunction on-off in the traditional lateral heterojunction. Further, combined with the voltage regulation of the ferroelectric gate 2 and the synergistic effect of the substrate 6 back gate, the FeJFET can realize more diversified function regulation modes, and lays a structural foundation for multifunctional integrated applications.

[0052] Example 2

[0053] The preparation method of the ferroelectric semiconductor junction field effect transistor in this embodiment includes the following steps:

[0054] Tape-assisted mechanical exfoliation was used to mechanically exfoliate bulk crystals of the two-dimensional ferroelectric n-type semiconductor In2Se3 and the two-dimensional p-type semiconductor MoTe2 onto a polydimethylsiloxane substrate. Thin strips of film with the required thickness, size, and shape were selected using optical microscopy. The selected films ranged from 3-10 μm in width and 15-30 μm in length. The selected In2Se3 films had thicknesses of 40-80 nm, and the MoTe2 films had thicknesses of 3-10 nm. A p-type silicon (Si) substrate with a 50 nm thick silicon dioxide (SiO2) layer and a resistivity of 0.001-0.005 Ω·cm was prepared. The surface was cleaned to remove impurities and ensure proper adhesion during the subsequent material transfer process. The In2Se3 film was preferentially transferred to the p-type Si / SiO2 substrate using a transfer platform. The precise positioning of the transfer platform allowed the exfoliated In2Se3 film to be smoothly transferred through the PDMS to the center of the substrate, ensuring a tight bond between the film and the substrate. The MoTe2 material was precisely transferred onto the surface of the ferroelectric gate layer, In2Se3, using PDMS. The two long strips of material were stacked in a cross-shaped pattern, forming a channel layer / ferroelectric gate layer heterojunction. Direct-write lithography was used to define the electrode pattern on the surface of the double-layer heterostructure, and then a 50 nm thick gold (Au) electrode was deposited by thermal evaporation. The specific steps involved using photoresist to form a mask in the target area, etching the electrode pattern using direct-write lithography. After removing the photoresist from the unprotected areas, gold was thermally evaporated in a vacuum environment, depositing Au in the patterned areas to form an electrode structure with uniform thickness. Figure 1 This is a schematic diagram of the structure of the ferroelectric semiconductor junction field effect transistor after preparation. The actual photo is as follows Figure 2 shown.

[0055] Based on the electrical characteristics test of the ferroelectric semiconductor junction field effect transistor mentioned above.

[0056] When a voltage of -1 to 1 V is applied to the In2Se3 ferroelectric gate layer 4 to control the channel current, the device exhibits p-channel transfer characteristics, such as Figure 3 As shown in (a), the horizontal axis is the voltage V applied to the ferroelectric gate layer 4 fg , range -1.0~0.5 V; the vertical axis is the logarithmic coordinate of the drain current I ds . Different drain bias V ds (-1 V, -0.5 V, -0.1 V, corresponding to blue, light blue, and orange curves), when V cg Negative increase (enhanced hole attraction), I ds Significantly improved, on / off current ratio exceeds 10 4 ; The light-colored curve I in the figure gs The leakage current of FeJFET is as low as 10 -11A, fully embodies excellent leakage suppression performance. The MoTe2 material thickness is most suitable when being 3-10 nm, if the thickness is less than 3 nm, the carrier concentration is low, and it is difficult to form ohmic contact between the metal of the source and the drain and the channel; if the thickness is greater than 10 nm, the carrier concentration is too high, and the material gradually changes from p-type to bipolar type or even to partial n-type, at this time, it is difficult to form a good pn junction between MoTe2 and In2Se3 to constitute a junction field effect transistor. The thickness of In2Se3 material needs to be controlled in the range of 40-80 nm, if the thickness is less than 40 nm, the insufficient carrier concentration will increase the ferroelectric gate voltage, resulting in the increase of the device opening voltage; if the thickness is greater than 80 nm, the too high carrier concentration will weaken the distinction between high and low resistance states, and cannot guarantee the synergistic effect of ferroelectricity and semiconductor characteristics. It is worth noting that the p-type transistor has a much higher difficulty in electrode contact interface preparation than the n-type device due to the hole transport characteristics, and the present application successfully constructs a p-type junction field effect transistor, which highlights the innovative advantages of the structure design.

[0057] As shown in (b) of FIG. 1, Figure 3 The horizontal coordinate V ds ranges from-1.0 to 0 V, and the vertical coordinate I ds is in units of μA, the negative current conforms to the p-channel hole transport, in the output characteristic test, different V fg , the low V ds region current changes linearly with the bias voltage, showing ohmic contact characteristics, and the high V ds region shows the saturation behavior of the junction field effect transistor; in the double scanning test, the device has a steep subthreshold swing and negligible hysteresis, which is different from the traditional MOSFET. The junction field effect transistor has no gate dielectric layer, the gate and the channel are directly coupled, and the gate-channel capacitance tends to be infinite in theory, which is the core structural advantage of the steeper subthreshold swing. At the same time, V cg In the process of scanning from-1 to 1 V, In2Se3 does not occur ferroelectric polarization reversal within the ferroelectric coercive field voltage range (-3.5 V~3 V), the device is mainly based on semiconductor carrier modulation rather than ferroelectric reversal mechanism, which further guarantees the stability and controllability of the electrical characteristics, and highlights the potential of FeJFET in low-power and high on-off ratio application scenarios.

[0058] Embodiment 3

[0059] The application method of the photodetector based on the above-mentioned ferroelectric semiconductor junction field effect transistor in this embodiment.

[0060] During the test, first, in a full dark and constant temperature environment, a scanning voltage of-1 V to 1 V is applied between the source (or drain) and the control gate 2 of the In2Se3 / MoTe2 ferroelectric semiconductor junction field effect transistor, and the dark state current-voltage (I-V) characteristic curve (correspondingFigure 4 (a), the horizontal coordinate is the voltage V between the source-drain and the control gate 2 PN , covering the reverse bias, zero bias and forward bias interval, the vertical coordinate is the heterojunction current I on a logarithmic scale PN to expand the current dynamic observation range). In the dark state, the electric field in the reverse bias region suppresses the thermal excitation of carriers, and the current is as low as 10 -12 order of magnitude, the curve is flat; in the forward bias region, carriers are injected with an exponential electric field, and the curve rises steeply. The light response test maintains the same voltage scanning conditions, and uses an 808 nm laser (photon energy 1.53 eV, higher than the In2Se3 band gap 1.35 eV and the MoTe2 multilayer band gap 1 eV, which can efficiently excite photo-generated carriers) to adjust the light intensity (3.1~4970 mW / cm², corresponding to the curve from blue to red in turn). Under reverse bias, the strong electric field quickly separates the photo-generated electron-hole pairs, and the current linearly climbs with the light intensity; near zero bias, the diffusion of photo-generated carriers dominates the transport, and the light current gradually overtakes the dark state; in the forward bias region, the electric field assists the injection of carriers, and the curve slope is steeper under high power. What is particularly key is that the intersection of the curves corresponding to different light powers and the horizontal coordinate (voltage axis) (i.e. the open circuit voltage when the current is zero) gradually shifts to the positive direction as the light power increases, indicating that the stronger the light power, the greater the open circuit voltage, directly confirming that the photovoltaic effect is enhanced with the increase of light intensity. At the same time, the photoelectric current gain in the full voltage interval is more significant as the light intensity increases, further verifying the light intensity response law of the device.

[0061] As shown in (b) of FIG. 17, Figure 4 , the horizontal coordinate is time, recording the timing of 375 nm (ultraviolet band), 532 nm (visible band), 808 nm (near-infrared band), and 1064 nm (near-infrared band) pulsed light; the vertical coordinate is the photocurrent I ph , the test fixed the drain bias voltage at 1 V, and the light power of each wavelength was 500 mW / cm². In the 375 nm band, the device has a clear light response, with a photocurrent of about 3 nA; in the 532 nm band, the matching degree of photon energy and heterojunction band gap is improved, and the light absorption efficiency is enhanced, with a current jump to 10 nA; in the 808 nm band, the photon energy matches the In2Se3 band gap, and the light absorption and carrier transport are optimal, with a response of 22 nA; in the 1064 nm band, the photon energy is lower than the In2Se3 band gap, and the light absorption is mainly performed by MoTe2, and the device also has a clear response in the infrared band.

[0062] Based on the energy band matching of In2Se3 and MoTe2, the device effectively responds to the spectral range of 400~1200 nm (corresponding to photon energy of 1.03~3.1 eV). Combined with the photocurrent gain characteristics under ferroelectric regulation, enhanced photovoltaic effect and self-powered capability, it is clear that the FeJFET can be used as a wide-spectrum photodetector to achieve efficient detection and sensitive response of optical signals in the ultraviolet, visible and near-infrared bands.

[0063] Example 4

[0064] This embodiment is based on the application method of the memory of the ferroelectric semiconductor junction field effect transistor mentioned above.

[0065] ±20 V electric pulses with a duration of 5 s are applied to the device through the Si substrate 6 to switch the polarization direction of the In2Se3 ferroelectric gate layer 4. +20 V induces the polarization of the In2Se3 ferroelectric gate layer 4 to P upward. up , -20 V induces polarization downward P down . The carrier density of the MoTe2 channel layer 3 is modulated by polarization charge. down When P is 0, the positive charge on the surface of In2Se3 repels the holes in MoTe2, forming a depletion region and a downward-bent energy band, corresponding to a high-resistance state (low current); up When the negative charge on the surface attracts holes to accumulate, the depletion region shrinks, and the state corresponds to a low resistance (high current). After programming is completed, a read voltage of -0.1 V is applied between the source and drain, and the drain current I of the MoTe2 channel layer 3 is collected by a semiconductor parameter analyzer. ds , Figure 5 The vertical axis is the logarithmic scale I ds , based on the current value, the high and low resistance states stored in the device are determined. Figure 5 The horizontal axis of (a) is time, P down (Blue line) corresponds to high current, maintained at 10 -8 A, P up (Orange line) corresponds to low current, maintained at 10 -10 A. These two resistance states can be stably maintained for more than 500 s under a drain-source bias of -0.1 V, verifying the device's memory resistance state retention behavior; Figure 5 The horizontal axis in (b) is the number of cycles. After applying a ±20 V, 100 ms pulse to switch the polarization each time, the current is read at -0.1 V. P down Always maintain high current, P up It always maintains low current and has no obvious performance degradation after 100 cycles, showing excellent fatigue resistance, thus realizing non-volatile storage function.

[0066] Example 5

[0067] This embodiment is based on the above-mentioned synapse application method of the ferroelectric semiconductor junction field effect transistor.

[0068] The source and drain 1 are used as the reading end of the postsynaptic current, and the substrate 6 is used as the modulation end of the synaptic weight to apply the programming gate voltage pulse. Before the test, the In2Se3 of the ferroelectric gate layer 4 is initialized to the polarization upward P up state, at this time, the MoTe2 channel is in a high-resistance state due to the wide heterojunction depletion region, and the channel current (postsynaptic current PSC) measured at the drain is at an initial low level. Figure 6 As shown in (a), the horizontal axis is time, the vertical axis is PSC, and the source-drain bias voltage V is fixed. ds = -0.1 V, multiple sets of -7 V, 100ms negative electric pulse sequences (pulse number 20-50, corresponding to blue, light blue, orange, and light orange curves) are applied through substrate 6: As the number of pulses increases (from 20 to 50), the peak value of PSC gradually increases (peak value exceeds 30 nA at 50 pulses), and the current decay rate slows down significantly after the pulse ends. This is because each negative pulse pushes In2Se3 from P up Gradually polarize downward down Flipping, the heterojunction depletion region continues to shrink, and the channel conductance continues to increase, causing the device to transition from short-term memory (few pulses, fast decay) to long-term memory (many pulses, slow decay), simulating the consolidation process of "repeated stimulation to strengthen memory" in biological synapses.

[0069] Figure 6 As shown in (b), the horizontal axis is the number of pulses and the vertical axis is PSC. The first 50 pulses are -7 V, 100 ms (orange mark), and PSC increases approximately linearly with the number of pulses (long-term potentiation LTP, simulating an increase in synaptic weight); after the 50th pulse, a positive pulse of 5 V, 100 ms (blue mark) is applied, and PSC drops rapidly (long-term depression LTD, simulating a decrease in synaptic weight). The mechanism is that the negative pulse drives the polarization of In2Se3 from P to up to P down Gradually reversed, the depletion region width continues to decrease, and the conductivity continues to increase; the forward pulse reverse drives the polarization from P down to P up By adjusting the polarity and number of voltage pulses, the degree of polarization reversal of In2Se3 can be continuously adjusted, achieving multi-state continuous regulation of MoTe2 channel conductance, perfectly simulating the weight plasticity of biological synapses (such as LTP strengthening connections during learning and LTD weakening connections during forgetting). At the same time, the regulation of the number of pulses from short-term to long-term memory states also conforms to the dynamic learning characteristics of biological synapses, highlighting the biomimetic application potential of this FeJFET in the field of neuromorphic computing.

[0070] Example 6

[0071] This embodiment is based on the application method of the self-switching logic of the ferroelectric semiconductor junction field effect transistor described above.

[0072] First, the ferroelectric gate layer 4 is pre-programmed by applying ±20 V pulses for 5 s on the substrate 6 to switch its polarization direction upward or downward. The gate voltage on the substrate 6 and the voltage of the control gate 2 on the ferroelectric gate layer 4 are used as the two-terminal logic input ports (INA and INB are "1" and "0" respectively at 0.5 V / 0 V, and INB is "1" and "0" respectively at 0 V / −3 V). The current in the channel layer 3 is used as the output port. The schematic diagram of the voltage application method is shown in Figure 7 When the polarization state is upward P up When only inputting "00" corresponds to low current output "0", the rest of the states are high current output "1", showing Figure 8 The NOR logic behavior shown in (a) is shown in Figure 1. When the polarization state is downward, P down When inputting "11", the high current output is "1", and the rest of the states are low current output "0". Figure 8 The NAND logic behavior shown in (b) is shown in Figure 1. The ratio of the current output in the two logic states of “0” and “1” is close to 10. 4 , ensuring reliable logic state discrimination and low-power operation. Furthermore, the small voltages applied to INA and INB are all within the coercive field range of In2Se3, preventing polarization reversal and ensuring the stability of the internal logic functions. This allows for reconfigurable logic functions such as "NAND" and "NOR" to be achieved in a single transistor by switching the polarization direction of the ferroelectric gate layer 4.

[0073] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0074] It should be understood that the above general description and the detailed description that follows are exemplary and explanatory only and do not limit the present application. The present application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope of the present application. The scope of the present application is limited only by the appended claims.

Claims

1. A ferroelectric semiconductor junction field effect transistor, characterized by, Comprise: a source electrode, a drain electrode, a control gate electrode, a channel layer, a ferroelectric gate layer, an insulating isolation layer and a substrate; the insulating isolation layer covers the surface of the substrate, the ferroelectric gate layer is arranged above the insulating isolation layer, and the channel layer and the ferroelectric gate layer are stacked to form a longitudinal heterojunction structure; the control gate electrode is arranged at one end of the ferroelectric gate layer for applying a gate voltage to regulate the polarization state of the ferroelectric layer, and the source electrode and the drain electrode are arranged at two ends of the channel layer respectively to form a path for carrier injection and collection.

2. A ferroelectric semiconductor junction field effect transistor according to claim 1, wherein, The channel layer adopts a two-dimensional transition metal sulfide semiconductor material, specifically one of WSe2, MoTe2, WS2 and ReS2, and the thickness is 3-10 nm.

3. A ferroelectric semiconductor junction field effect transistor as claimed in claim 1, characterized in that The ferroelectric gate layer adopts a two-dimensional ferroelectric semiconductor material, specifically one of In2Se3, InSe and SnSe, and the thickness is 40-80 nm.

4. A ferroelectric semiconductor junction field effect transistor as claimed in claim 1, characterized in that The source electrode, the drain electrode and the control gate electrode are all metal Au electrodes with a thickness of 40-80 nm. The insulating isolation layer is an oxide layer, which is a SiO2 layer with a thickness of 50 nm, and the substrate is a highly doped p-type or n-type silicon substrate.

5. A method for preparing the transistor according to any one of claims 1 to 4, characterized in that, Comprise: Step 1: substrate cleaning: prepare a p-type silicon substrate with a 50 nm thick silicon dioxide layer on the surface and a resistivity of 0.001-0.005 Ω·cm, clean the surface of the substrate to remove impurities and ensure the adhesion of subsequent material transfer; Step 2: ferroelectric gate layer and channel layer material selection: use tape-assisted mechanical exfoliation method to exfoliate from bulk crystals of two-dimensional ferroelectric n-type semiconductor In2Se3 and two-dimensional p-type semiconductor MoTe2 to polydimethylsiloxane substrate respectively; select long strip-shaped flakes with thickness, size and shape meeting the requirements through optical microscope, wherein the width is 3-10 μm, the length is 15-30 μm, the thickness of selected In2Se3 is 40-80 nm, and the thickness of MoTe2 is 3-10 nm; Step 3: ferroelectric gate layer transfer: transfer In2Se3 flakes to the surface of p-type Si / SiO2 substrate by transfer platform; use the precise positioning function of the transfer platform to transfer the exfoliated In2Se3 flakes to the central area of the substrate by PDMS, and ensure that the flakes are tightly attached to the substrate; Step 4: channel layer transfer: transfer MoTe2 material to the surface of the ferroelectric gate layer In2Se3 by PDMS, and the two long strip-shaped materials are stacked in a cross shape, forming a channel layer / ferroelectric gate layer heterojunction; Step 5: electrode preparation: use photolithography to pattern long strip-shaped electrode patterns at both ends of the channel layer and one end of the ferroelectric gate layer, and then use thermal evaporation and metal exfoliation process to prepare metal gold electrode, forming source electrode, drain electrode and control gate electrode.

6. Use of a ferroelectric semiconductor junction field effect transistor according to any one of claims 1 to 4, characterized in that, As a light sensor, a memory, a heterosynaptic device and a self-switching logic implementation.

7. Use according to claim 6, characterized in that, The application of the ferroelectric semiconductor junction field effect transistor as a light sensor specifically includes: in a completely dark environment, a scanning bias voltage of-1 V to 1 V is applied between the source electrode or the drain electrode and the control gate electrode, and the heterojunction dark state current is collected; introduce a light spot illuminator to the active area of the device, and measure the photocurrent signal under different light intensities by adjusting the light intensity.

8. Use according to claim 7, characterized in that, The application of the ferroelectric semiconductor junction field effect transistor as a memory specifically includes: switching the polarization direction of the ferroelectric gate layer by applying a programming electric pulse of ±20 V through the substrate for 5 s; applying a reading voltage between the source and the drain to realize data storage according to the high and low resistance states of the channel layer current value, wherein high current corresponds to a low resistance state "1", and low current corresponds to a high resistance state "0".

9. Use according to claim 6, characterized in that, The application of the ferroelectric semiconductor junction field effect transistor in a heterosynapse device specifically includes: The source and the drain are used as a postsynaptic current reading end, and the substrate is used as a weight modulation end; before testing, the ferroelectric gate layer is initialized to a polarization upward state, and under a fixed source-drain bias, a sequence of electric pulses of-10~10 V is applied through the substrate; The negative electric pulse induces the enhancement of the postsynaptic current, and the positive electric pulse causes the inhibition of the postsynaptic current; By adjusting the pulse parameters, the continuous modulation of multiple conductance states in the channel layer is realized, simulating the short-term / long-term memory conversion function of a biological synapse.

10. Use according to claim 6, characterized in that, The application of the ferroelectric semiconductor junction field effect transistor to realize self-switching logic specifically includes: First, the polarization direction of the ferroelectric gate layer is preprogrammed by applying an electric pulse of ±20 V through the substrate for 5 s; the substrate gate voltage is used as the INA port, the control gate voltage is used as the INB port, and the current of the channel layer is used as the output: When the polarization direction is upward, only input "00" corresponds to low current output "0", realizing "or non" logic; When the polarization direction is downward, only input "11" corresponds to high current output "1", realizing "and non" logic.

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