Semiconductor device structure and method for its manufacture

Abstract

Semiconductor device structure with: a semiconductor substrate (100); a first transistor that is fabricated in a first region of the semiconductor substrate, wherein the first transistor has a first gate structure on the semiconductor substrate over a junction between a p-well region (104) and an n-well region (106), wherein the first gate structure has the following: a first dielectric gate layer (131; 731; 831) on the semiconductor substrate, and a first gate layer (151; 751; 851) on the first dielectric gate layer; and a second transistor that is fabricated in a second region of the semiconductor substrate, wherein the second transistor has a second gate structure on the semiconductor substrate over a junction between a p-well region (104) and an n-well region (106), wherein the second gate structure has the following: a second dielectric gate layer (132; 732; 832) on the semiconductor substrate, and a second gate layer (152; 752; 852) on the second dielectric gate layer, wherein the first dielectric gate layer of the first transistor and the second dielectric gate layer of the second transistor have different dielectric material compositions and the transistors have different threshold voltages.

Description

Background of the inventionField of the invention

[0001] The present invention relates to a semiconductor device structure and a method of manufacturing the same, and more particularly to a semiconductor device structure including devices with gate dielectric layers having different compositions and a method of manufacturing the same. Description of the state of the art

[0002] In recent years, due to the increased demand for high-voltage devices, interest in research into high-voltage metal-oxide-semiconductor transistors (HVMOS transistors) for use in high-voltage devices has increased. HVMOS devices can be used at high voltages, including voltages higher than the voltage applied to an input / output (I / O) circuit. MOS devices such as HVMOS devices can function as switches and are widely used in audio output drivers, CPU power sources, energy-saving systems, AC-to-DC converters, LCD or plasma TV drivers, automotive electronic components, PC peripherals, small DC motor controllers, and consumer electronics devices.

[0003] Although existing semiconductor devices, such as MOS devices, and their manufacturing methods are suitable for their intended purposes, they are still not entirely satisfactory. For example, when multiple devices (such as HV devices) are fabricated on the same semiconductor substrate, threshold voltages of conventional devices are typically related to conductive materials and gate structure configurations. It is difficult to fine-tune the threshold voltage of a device incorporating the conventional gate structure. Furthermore, the manufacturing process for the conventional gate structure is complicated, resulting in a mismatch between the conductive material layers in a gate structure stack. Furthermore, structural variations between different gate structures on the semiconductor substrate also increase.Therefore, there are still some problems to be overcome in providing multiple devices of a semiconductor device structure on one and the same semiconductor substrate in semiconductor integrated circuits and technology.

[0004] US 2018 / 0019314 A1 discloses a semiconductor device comprising a first transistor comprising a first dielectric film on a substrate and a first workfunction metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second workfunction metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third workfunction metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a workfunction tuning material, and the second dielectric film does not comprise the workfunction tuning material. The first workfunction metal film has a different thickness than the third workfunction metal film. Related methods are also described.

[0005] US 2010 / 0276753 A1 discloses several types of gate stacks formed on a doped semiconductor well. A high-k gate dielectric is formed on the doped semiconductor well. A metallic gate layer is formed in one device region, while the high-k gate dielectric is exposed in other device regions. Threshold voltage matching oxide layers of varying thicknesses are formed in the other device regions. A conductive gate material layer is then formed over the threshold voltage matching oxide layers. One type of field-effect transistor comprises a gate dielectric including a high-k gate dielectric portion. Other types of field-effect transistors comprise a gate dielectric including a high-k gate dielectric portion and first threshold voltage matching oxide portions of varying thicknesses.Field effect transistors with different threshold voltages are provided by using different gate dielectric stacks and doped semiconductor wells with the same dopant concentration.

[0006] US 2013 / 0200445 A1 discloses an HVMOS transistor structure comprising: a first ion well of a first conductivity type and a second ion well of a second conductivity type different from the first conductivity type formed over a substrate, the first ion well and the second ion well having a junction at their interface; a gate overlying the first ion well and the second ion well; a drain region of the first conductivity type in the first ion well, spaced from a first sidewall of the gate by an offset distance; and a source region of the first conductivity type in the second ion well. Furthermore, a method for fabricating the above-described HVMOS transistor structure is also provided.

[0007] US 2021 / 0257258 A1 discloses a method comprising forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further comprises depositing a first lanthanum-containing layer overlapping the first gate dielectric and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. Subsequently, an annealing process is performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the annealing process, the third gate dielectric is free of lanthanum-containing layers thereon.

[0008] DE 10 2021 001 414 A1 describes a gate structure of a field-effect transistor comprising a first dielectric gate layer, a second dielectric gate layer, and one or more conductive layers arranged above the first dielectric gate layer and the second dielectric gate layer. The first dielectric gate layer is separated from the second dielectric gate layer by a gap filled with a diffusion blocking layer. Brief description of the invention

[0009] The invention is defined in the claims.

[0010] In some embodiments, semiconductor device structures are provided. According to the invention, a semiconductor device structure comprises: a semiconductor substrate; a first transistor formed in a first region of the semiconductor substrate, the first transistor having a first gate structure on the semiconductor substrate over a junction between a p-well region and an n-well region, the first gate structure comprising: a first gate dielectric layer on the semiconductor substrate, and a first gate layer on the first gate dielectric layer;and a second transistor fabricated in a second region of the semiconductor substrate, the second transistor having a second gate structure on the semiconductor substrate over a junction between a p-well region and an n-well region, the second gate structure comprising: a second gate dielectric layer on the semiconductor substrate, and a second gate layer on the second gate dielectric layer, the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor having different dielectric material compositions, and the transistors having different threshold voltages;

[0011] In some embodiments, a method of manufacturing a semiconductor device structure is provided. The method of manufacturing a semiconductor device structure comprises: providing a semiconductor substrate having a first and a second region; and forming a first transistor in the first region above a junction between a p-well region and an n-well region and a second transistor in the second region above a junction between a p-well region and an n-well region, wherein the first transistor has a first gate structure on the semiconductor substrate and the second transistor has a second gate structure on the semiconductor substrate, wherein forming the first gate structure comprises: forming a first gate dielectric layer on the semiconductor substrate, and forming a first gate layer on the first gate dielectric layer,and forming the second gate structure comprises: forming a second gate dielectric layer on the semiconductor substrate, and forming a second gate layer on the second gate dielectric layer, wherein the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor have different dielectric material compositions and are formed with different threshold voltages.

[0012] A detailed description is given below using embodiments with reference to the accompanying drawings. Short description of the drawings

[0013] The present invention can be better understood by reading the following detailed description and examples with reference to the accompanying drawings. Fig. 1 is a top view of a semiconductor device structure according to some embodiments of the present disclosure. The Fig. 2A to 2D are cross-sectional views of intermediate stages of a method of manufacturing a semiconductor device structure according to some embodiments of the present disclosure. Fig. 3 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. Fig. 4 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. Fig. 5 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. Fig. 6 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. Fig. 7A shows cross-sectional views of different gate structures of the devices on a semiconductor substrate according to some embodiments of the present disclosure. Fig. Figure 7B shows cross-sectional views of different gate structures of conventional devices on a semiconductor substrate. Fig. Figure 8 shows a trade-off between the lifetime of hot carrier injection (HCI) and the device resistance of a HV semiconductor device. Detailed description of the invention

[0014] The following description is of the best mode contemplated for carrying out the invention. This description is intended to explain the general principles of the invention. The scope of the invention is determined by the appended claims.

[0015] The inventive concept will now be fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept, as well as methods of achieving them, will be apparent from the following exemplary embodiments, which are further described with reference to the accompanying drawings. It should be noted, however, that the invention may be implemented in various forms. Therefore, the exemplary embodiments are provided only to disclose the inventive concept and to demonstrate the category of the inventive concept to those skilled in the art. Furthermore, the drawings are only schematic. In the drawings, some elements may be enlarged for illustrative purposes and not drawn to scale. The dimensions and relative dimensions do not correspond to the actual dimensions when the invention is used.

[0016] The terms used herein are for the purpose of describing specific embodiments. The singular forms "a" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. The term "and / or" as used herein includes any combination of one or more of the associated terms. It is understood that when an element is referred to as being "connected" to or "contacting" another element, the element may be directly connected to or contacting the other element, or intervening elements may be present.

[0017] Likewise, it should be understood that when an element, such as a layer, region, or substrate, is referred to as being disposed "on" another element, the element may be disposed directly on the other element, or there may be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should be understood that the terms "comprising," "including," and / or "having" as used herein specify the presence of stated structural elements, units, steps, operations, elements, and / or components, but do not preclude the presence or additional use of one or more other structural elements, units, steps, operations, elements, components, and / or groups thereof.

[0018] In addition, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to simply describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. It should be understood that the terms "first," "second," "third," etc., may be used herein to describe various elements. These terms are merely used to distinguish one element from another.Thus, a first element in some embodiments could be referred to as a second element in other embodiments without departing from the principles of the present invention. Exemplary embodiments of aspects of the present inventive concept explained and illustrated herein also include their complementary counterparts. Throughout the specification, the same or similar reference numbers and letters refer to the same or similar elements.

[0019] Some embodiments of the disclosure are described below. It should be noted that additional steps may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or omitted in other embodiments. Other elements may be used for the semiconductor device structure. Some of the elements described below may be replaced or omitted in other embodiments. While some embodiments are discussed with operations performed in a particular order, these operations may also be performed in a different logical order.

[0020] According to some embodiments of the present disclosure, a semiconductor device structure and a method of fabricating the same are described below, wherein the semiconductor device structure includes devices with gate dielectric layers of different compositions. In some embodiments, a gate dielectric layer comprising one or more suitable dielectric materials (such as one or more high-k dielectric materials) is implemented in each of the gate structures of the devices to avoid the HCI (hot carrier injection) effect, thereby improving the electrical properties of the devices.Furthermore, in some embodiments, by adjusting the material composition and dielectric constant of each of the gate dielectric layers, different threshold voltages (Vt) of devices (such as high-voltage devices) fabricated on the same semiconductor substrate 100 can be fine-tuned. In some embodiments of the present disclosure, each of the devices can be operated within a suitable window of HCI lifetime and device resistance by providing flexible threshold voltages (Vt). Furthermore, in some embodiments, the semiconductor device structure and the method for its fabrication reduce the process complexity in fabricating the gate structure, thereby addressing the existing problem of misalignment of the structural elements (e.g.,the offset between the conductive material layers in a stack of the gate structure) is solved and the electrical properties of the devices are improved.

[0021] Some of the methods for manufacturing the semiconductor device structure according to some embodiments of the present disclosure are provided below. The steps and structures described below are intended to provide only examples of the manufacturing and configuration of the semiconductor device.

[0022] Fig. 1 is a top view of a semiconductor device structure according to some embodiments of the present disclosure. In Fig. 1, a semiconductor device structure includes multiple devices, such as MOS transistors (metal oxide semiconductor transistors), fabricated in different regions of a semiconductor substrate (such as a wafer). For example, a first device 10-1 (e.g., a first MOS transistor) is fabricated in a first region 10A, a second device 10-2 (e.g., a second MOS transistor) is fabricated in a second region 10B, and a third device 10-3 (e.g., a third MOS transistor) is fabricated in a third region 10C. Furthermore, in some embodiments of the present disclosure, the devices (such as the first, second, and third devices) are high-voltage metal oxide semiconductor (HVMOS) transistors.

[0023] The Fig. 2A to 2D are cross-sectional views of intermediate stages of a method of fabricating a semiconductor device structure according to some embodiments of the present disclosure. In some embodiments, a semiconductor device structure is provided that includes at least two devices, wherein the gate dielectric layers of the two devices have different material compositions.

[0024] To simplify the illustration, only two devices are shown. Fig. Figures 2A to 2D illustrate side-diffused MOS (LDMOS) devices. Other device types may also be used. Furthermore, the planar LDMOS device is merely an example to illustrate fabrication. The semiconductor device structure may include planar transistors or three-dimensional transistors, such as fin field-effect transistors (FinFETs).

[0025] In this example, a semiconductor device structure includes a first device 10-1 (e.g., a first MOS transistor) fabricated in a first region 10A and a second device 10-2 (e.g., a second MOS transistor) fabricated in a second region 10B, as shown in Fig. 1. See Fig. 1 and Fig. 2A.

[0026] In Fig. 2A are, in some embodiments, part of the first device 10-1 ( Fig. 1) and a part of the second device 10-2 ( Fig. 1). First, a semiconductor substrate 100 is provided, which includes well regions and isolation regions 108 adjacent to the well regions. The semiconductor substrate 100 may include well regions 104 having a first conductivity type, such as p (also referred to as p-well regions 104). The semiconductor substrate 100 may also include well regions 106 having a second conductivity type, such as n (also referred to as n-well regions 106).

[0027] The semiconductor substrate 100 may be a semiconductor wafer, such as a silicon wafer. Alternatively, the semiconductor substrate 100 may be another elemental semiconductor, such as silicon. The semiconductor substrate 100 may also be a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The semiconductor substrate 100 may also be an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the semiconductor substrate 100 comprises an epitaxial layer over a bulk semiconductor. In one embodiment, the semiconductor substrate 100 comprises a semiconductor-on-insulator (SOI) structure.In some embodiments, the semiconductor substrate 100 may include a buried layer, such as a buried n-type layer (NBL) or a buried p-type layer (PBL), and / or a buried dielectric layer, such as a buried oxide layer (BOX layer). In the present embodiment, n-type high-voltage MOS transistor (HVNMOS) structures are used as examples for the first device 10-1 and the second device 10-2, and the semiconductor substrate 100 has a first conductivity type and is, for example, a p-type silicon substrate. To fabricate a complementary HVMOS (HVCMOS), a buried n-type layer, ie, a deep n-well (DNW), may be implanted deep beneath active regions (such as beneath the p-well regions 104 and the n-well regions 106) of the p-HVMOS in the p-type silicon substrate (not shown).

[0028] Furthermore, the p-well regions 104 and the n-well regions 106 may be parts of the semiconductor substrate 100 and may be formed using various implantation processes. Alternatively, the p-well regions 104 and the n-well regions 106 may be parts of an epitaxial layer, such as a silicon epitaxial layer formed using an epitaxial process. The p-well regions 104 may contain a p-dopant such as boron, and the n-well regions 106 may contain an n-dopant such as phosphorus.

[0029] Additionally, isolation regions 108, such as shallow trench isolation (STI) elements or other suitable isolation elements, may be formed in the semiconductor substrate 100 to define and electrically isolate various active regions, such as p-well regions 104 and n-well regions 106. In some embodiments, the isolation regions 108, which extend downward from the top of the semiconductor substrate 100, are embedded in the semiconductor substrate 100. The isolation regions 108 may comprise silicon oxide, another suitable isolation material, or a combination thereof. In one example, the STI elements may be formed by dry etching trenches in a substrate and filling the trenches with isolation materials such as silicon oxide, silicon nitride, or silicon oxynitride.Each of the filled trenches may have a multi-layer structure, such as a thermal oxide coating layer and a fill material of silicon nitride or silicon oxide.

[0030] In some embodiments, each device includes a gate structure on top of the semiconductor substrate 100. As shown in the Fig. 1 and Fig. As shown in Figure 2A, a first gate structure GS-1 of the first device 10-1 and a second gate structure GS-2 of the second device 10-2 are formed on top of the semiconductor substrate 100. In this example, the first gate structure GS-1 is formed over the junction between the p-well region 104 and the n-well region 106 of the first device 10-1. Likewise, the second gate structure GS-2 is formed over the junction between the p-well region 104 and the n-well region 106 of the second device 10-2.

[0031] In some embodiments, the first gate structure GS-1 of the first device 10-1 includes a first gate dielectric layer 131 and a first gate layer 151 on the first gate dielectric layer 131. The second gate structure GS-2 of the second device 10-2 includes a second gate dielectric layer 132 and a second gate layer 152 on the second gate dielectric layer 132. The first gate structure GS-1 of the first device 10-1 may be formed using a photolithography process to pattern the material layers of the first gate dielectric layer 131 and the first gate layer 151. Similarly, the second gate structure GS-2 of the second device 10-2 may be formed using a photolithography process to pattern the material layers of the second gate dielectric layer 132 and the second gate layer 152.The first gate structure GS-1 in the first region 10A and the second gate structure GS-2 in the second region 10B may be spaced apart from each other in a first direction D1 (such as the x-direction). Furthermore, in some embodiments, the first gate structure GS-1 and the second gate structure GS-2 extend in a second direction D2 (such as the y-direction). The first direction D1 is different from the second direction D2.

[0032] In the present embodiments, the first gate dielectric layer 131 of the first gate structure GS-1 and the second gate dielectric layer 132 of the second gate structure GS-2 have different dielectric material compositions. In some embodiments, the first gate dielectric layer 131 has a first dielectric constant k1, and the second gate dielectric layer 132 has a second dielectric constant k2. The first dielectric constant k1 is different from the second dielectric constant k2. In one embodiment, the second dielectric constant k2 of the second gate dielectric layer 132 is greater than the first dielectric constant k1 of the first gate dielectric layer 131.

[0033] In some embodiments, the first gate dielectric layer 131 of the first gate structure GS-1 and the second gate dielectric layer 132 of the second gate structure GS-2 are high-k dielectric layers. The first dielectric constant k1 of the first gate dielectric layer 131 may be equal to or greater than 20. The second dielectric constant k2 of the second gate dielectric layer 132 may also be equal to or greater than 20. In one example, the second dielectric constant k2 of the second gate dielectric layer 132 is greater than the first dielectric constant k1 of the first gate dielectric layer 131. In the embodiment, the first high-k gate dielectric layer 131 of the first gate structure GS-1 prevents charge carriers from passing through the high-k gate dielectric layer 131 and reaching the first gate layer 151.The second high-k gate dielectric layer 132 of the second gate structure GS-2 prevents charge carriers from passing through the second high-k gate dielectric layer 132 and reaching the second gate layer 152. In some embodiments, different chips on a wafer may include multiple devices having gate dielectric layers made of different high-k dielectric materials to achieve their required threshold voltages (Vt) for the devices.

[0034] Exemplary materials for the first gate dielectric layer 131 and the second gate dielectric layer 132 may be hafnium oxide (HfO x ), lanthanum oxide (LaO x ) or a combination thereof. In one example, the first gate dielectric layer 131 and the second gate dielectric layer 132 comprise (among other things) hafnium oxide (HfO x ), lanthanum oxide (LaO x), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or combinations thereof. It should be noted that the first gate dielectric layer 131 and the second gate dielectric layer 132 of the present disclosure are not limited to the aforementioned materials.

[0035] In addition, the first gate dielectric layer 131 and the second gate dielectric layer 132 may each include an interface layer (not shown) and a high-k dielectric layer formed on the interface layer. The interface layer (not shown), the high-k dielectric layer (e.g., the first gate dielectric layer 131 or the second gate dielectric layer 132), and the gate layer (e.g., the first gate layer 151 or the second gate layer 152) are stacked on top of each other in a third direction D3 (e.g., the z-direction). In one example, the interface layer is formed on the semiconductor substrate 100 and includes a silicon oxide layer. The high-k dielectric layer (e.g., the first gate dielectric layer 131 or the second gate dielectric layer 132) may be formed on the interface layer by atomic layer deposition (ALD) or another suitable method. The gate layer (e.g.,the first gate layer 151 or the second gate layer 152) is formed on the high-k dielectric layer.

[0036] Furthermore, the first gate dielectric layer 131 of the first gate structure GS-1 may be a single layer or a multi-layer structure. Likewise, the second gate dielectric layer 132 of the second gate structure GS-2 may be a single layer or a multi-layer structure. In this example, which is shown in the Fig. 2A to 2D, for illustrating this embodiment, the first gate dielectric layer 131 is a single dielectric material layer, and the second gate dielectric layer 132 is also a single dielectric material layer. However, the present disclosure is not limited to the configurations of the first gate dielectric layer 131 and the second gate dielectric layer 132 in the Fig. 2A to 2D. In some other embodiments, the first gate dielectric layer 131 is a single dielectric material layer, and the second gate dielectric layer 132 comprises multiple dielectric material layers (e.g., a second gate dielectric layer 132-1 comprises two dielectric material layers 132a and 132b, as in Fig. 3, which will be described later). In some further embodiments, the first gate dielectric layer 131 and the second gate dielectric layer 132 each comprise multiple dielectric material layers.

[0037] Furthermore, in some embodiments, the first gate dielectric layer 131 and the second gate dielectric layer 132 have different numbers of dielectric material layers. In some further embodiments, the first gate dielectric layer 131 and the second gate dielectric layer 132 include the same number of dielectric material layers. The numbers of dielectric material layers in the first gate dielectric layer 131 and the second gate dielectric layer 132 are not limited in the present disclosure.

[0038] In addition, as in Fig. 2A, the first gate dielectric layer 131 of the first gate structure GS-1 has a first thickness t1, and the second gate dielectric layer 132 of the second gate structure GS-2 has a second thickness t2. In some embodiments, the first thickness t1 is equal to the second thickness t2. In some further embodiments, the first thickness t1 is different from the second thickness t2. The first thickness t1 of the first gate dielectric layer 131 may be about 0.1 nm to about 5 nm. The second thickness t2 of the second gate dielectric layer 132 may also be about 0.1 nm to about 5 nm. It should be noted that these numerical values ​​for the first gate dielectric layer 131 and the second gate dielectric layer 132 are only exemplary. Depending on the design requirements, any suitable numerical values ​​for the first thickness t1 of the first gate dielectric layer 131 and for the second thickness t2 of the second gate dielectric layer 132 may be used.

[0039] In some embodiments, the first gate layer 151 of the first gate structure GS-1 and the second gate layer 152 of the second gate structure GS-2 comprise one or more conductive materials. The first gate layer 151 may be referred to as a first gate electrode, and the second gate layer 152 may be referred to as a second gate electrode. The first gate layer 151 and the second gate layer 152 may independently include polysilicon, metal, metal silicide, metal nitride, another suitable material, or a combination thereof. Example metallic materials for the first gate layer 151 and the second gate layer 152 are TiN, TaN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, or other suitable metallic materials.

[0040] In some embodiments, the first gate layer 151 and the second gate layer 152 are made of polysilicon or metal, such as polysilicon or a metal doped with a p-type or n-type dopant. For example, the first gate layer 151 may be a single metallic n-type material layer, or it may be a combination of a metallic n-type material layer and one or more metallic p-type material layers. The second gate layer 152 may also be a single metallic n-type material layer, or it may be a combination of a metallic n-type material layer and one or more metallic p-type material layers.

[0041] In addition, the first gate layer 151 of the first gate structure GS-1 and the second gate layer 152 of the second gate structure GS-2 may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, or any other suitable process.

[0042] In some embodiments, the first gate layer 151 of the first gate structure GS-1 may be a single layer or a multi-layer structure. Likewise, the second gate layer 152 of the second gate structure GS-2 may be a single layer or a multi-layer structure. In this example, which is shown in the Fig. 2A to 2D, for the purpose of illustrating this embodiment, the first gate layer 151 is depicted as a single conductive material layer, and the second gate layer 132 is also depicted as a single conductive material layer. However, the present disclosure is not limited to the configurations of the first gate layer 151 and the second gate layer 152 in the Fig. 2A to 2D. In some other embodiments, the first gate layer 151 is a single conductive material layer, and the second gate layer 152 comprises multiple conductive material layers (e.g., a second gate layer 154 comprises two conductive material layers 154a and 154b, as in Fig. 4, which will be described later). In some further embodiments, the first gate layer 151 and the second gate layer 152 each comprise a plurality of conductive material layers.

[0043] Furthermore, in some embodiments, the first gate layer 151 and the second gate layer 152 have different numbers of conductive material layers (e.g., metallic material layers). In some further embodiments, the first gate layer 151 and the second gate layer 152 have the same number of conductive material layers. The number of conductive material layers in the first gate layer 151 and the second gate layer 152 is not limited in the present disclosure. Fig. 2A to 2D, the first gate layer 151 and the second gate layer 152 are each shown as a single conductive material layer to illustrate this embodiment.

[0044] In some embodiments, the first gate structure GS-1 of the first device 10-1 further comprises a first hard mask (not shown) formed over the first gate layer 151, and the second gate structure GS-2 of the second device 10-2 further comprises a second hard mask (not shown) formed over the second gate layer 152. The first and second hard masks may be formed using a deposition process or other suitable method. The first and second hard masks may comprise silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. To simplify the illustration of the first gate structure GS-1 and the second gate structure GS-2, only one gate dielectric layer and one gate layer are shown herein, respectively.

[0045] The first gate structure GS-1 of the first device 10-1 may be arranged asymmetrically on the p-well region 104 and the n-well region 106 of the first device 10-1. For example, the first gate structure GS-1 may have a first overlap distance with the p-well region 104 and a second overlap distance with the n-well region 106, respectively. The first overlap distance may be defined from a pn junction of the p-well region 104 and the n-well region 106 to a sidewall of the first gate dielectric layer 131 located on the p-well region 104. The second overlap distance may be defined from a pn junction of the p-well region 104 and the n-well region 106 to an opposite sidewall of the first gate dielectric layer 131 located on the n-well region 106.In the configuration of the first gate structure GS-1, the p-well region 104, and the n-well region 106, the first overlap distance is greater than the second overlap distance. The first overlap distance may be equal to or less than the second overlap distance. In some embodiments, the second gate structure GS-2 may be arranged asymmetrically or symmetrically on the p-well region 104 and the n-well region 106 of the second device 10-2. In the configuration of the second gate structure GS-2, the p-well region 104, and the n-well region 106 below the second gate structure GS-2, the first and second overlap distances between the second gate structure GS-2 and the pn junction are similar to those described above for the first gate structure GS-1, and the details are not repeated here.

[0046] In Fig. 2B, in some embodiments, lightly doped regions (LDD regions) 160 are further formed in the semiconductor substrate 100. The lightly doped regions 160 include first lightly doped regions 161 formed in the first region 10A of the semiconductor substrate 100 and second lightly doped regions 162 formed in the second region 10B of the semiconductor substrate 100. The first lightly doped regions 161 are adjacent to sidewalls of the first gate structure GS-1. In particular, in this example, the first lightly doped regions 161 are substantially aligned with sidewalls 131S of the first gate dielectric layer 131 and with sidewalls 151S of the first gate layer 151. The second lightly doped regions 162 are adjacent to sidewalls of the second gate structure GS-2.In particular, in this example, the second lightly doped regions 162 are substantially aligned with sidewalls 132S of the second gate dielectric layer 132 and with sidewalls 152S of the second gate layer 152. In some embodiments, the first lightly doped regions 161 may be formed using the first gate structure GS-1 as an implantation mask, and the second lightly doped regions 162 may be formed using the second gate structure GS-2 as an implantation mask. Accordingly, the first lightly doped regions 161 and the second lightly doped regions 162 may be formed without requiring an additional photomask for the patterning and / or implantation process.Thus, the first lightly doped regions 161 may have an edge that is substantially self-aligned to an edge of the first gate structure GS-1, and the second lightly doped regions 162 may have an edge that is substantially self-aligned to an edge of the second gate structure GS-2.

[0047] Now let’s come to Fig. 2C. Here, gate spacers 170 are formed on the sidewalls of the gate structures, and then source and drain regions are formed adjacent to the gate spacers 170.

[0048] In some embodiments, the gate spacers 170 include first gate spacers 171 formed on the sidewalls of the first gate structure GS-1 and second gate spacers 172 formed on the sidewalls of the second gate structure GS-2. The first gate spacers 171 are formed on the first lightly doped regions 161. Specifically, in this example, the first gate spacers 171 are formed on the sidewalls 131S of the first gate dielectric layer 131 and the sidewalls 151S of the first gate layer 151. The second gate spacers 172 are formed on the second lightly doped regions 162. Specifically, in this example, the second gate spacers 172 are formed on the sidewalls 132S of the second gate dielectric layer 132 and the sidewalls 152S of the second gate layer 152.

[0049] In some embodiments, the first gate spacers 171 of the first device 10-1 and the second gate spacers 172 of the second device 10-2 each comprise a dielectric material such as silicon oxide. In some further embodiments, the first gate spacers 171 and the second gate spacers 172 may optionally comprise silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. In some embodiments, the first gate spacers 171 are formed from a single spacer material layer, or they are a multi-layer structure including multiple spacer materials. The second gate spacers 172 are also formed from a single spacer material layer, or they are a multi-layer structure including multiple spacer materials.

[0050] In some embodiments, each of the first gate spacers 171 and the second gate spacers 172 includes four spacer material layers. For example, the first spacer material layer (not shown) is a silicon nitride layer with boron, carbon, fluorine, or combinations thereof as dopant atoms. A silicon-containing gas such as SiH2Cl2, Si2H6, SiH4, Si2Cl6, or BTBAS and a nitrogen-containing gas such as NH3, N2, or N2O are used as a precursor to a deposition process for forming the silicon nitride layer. In addition, the second spacer material layer, the third spacer material layer, and the fourth spacer material layer (not shown) are, for example, dielectric layers with a low dielectric constant (low-k dielectric layers). The k values ​​for the second, third, and fourth spacer material layers may each be about 4.2 to about 5.5.In some embodiments, the second, third, and fourth spacer material layers are low-k dielectrics with dopant atoms. A boron-containing gas, such as BCl3, BH3, or B2H6, or a carbon-containing gas, such as C2H4 or C2H6, may be used as a precursor to the deposition process of the low-k dielectrics with dopant atoms. In some embodiments, the spacer materials are an oxide, a nitride, an oxide-nitride with boron, carbon, or fluorine, or combinations thereof. In some embodiments, the spacer materials are silicon carbide with boron, nitrogen, fluorine, or combinations thereof.

[0051] In some embodiments, the first gate spacers 171 of the first device 10-1 and the second gate spacers 172 of the second device 10-2 may be formed in the same deposition and etching process. In one example, an initial spacer material layer may be conformally deposited over the semiconductor substrate 100 to cover the first gate structure GS-1 and the second gate structure GS-2. The initial spacer material layer is then patterned to form the first gate spacers 171 and the second gate spacers 172, as shown in Fig. 2C. The patterning step may be performed using a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the initial spacer material layer is patterned using a dry etching process. In some embodiments, the initial spacer material layer is patterned using an anisotropic dry etching process.

[0052] In some embodiments, after forming the first gate spacers 171 and the second gate spacers 172, heavily doped regions comprising the source regions and the drain regions are formed in the semiconductor substrate 100 adjacent to the gate spacers. In this example, a first source region 180 and a first drain region 181 are formed in the semiconductor substrate 100 adjacent to the first gate spacers 171 of the first device 10-1. Furthermore, a second source region 182 and a second drain region 183 are formed in the semiconductor substrate 100 adjacent to the second gate spacers 172 of the second device 10-2.

[0053] In some embodiments, the first source region 180 and the first drain region 181 are formed using the first gate structure GS-1 and the first gate spacers 171 as an implantation mask. The second source region 182 and the second drain region 183 are formed using the second gate structure GS-2 and the second gate spacers 172 as an implantation mask. Therefore, in some embodiments of the present disclosure, no additional mask is required to form the source region 180, the first drain region 181, the second source region 182, and the second drain region 183.

[0054] In this exemplary embodiment, the first source region 180 and the first drain region 181 may be self-aligned with outer edges of the first gate spacers 171 of the first gate structure GS-1. The second source region 181 and the second drain region 182 may be self-aligned with outer edges of the second gate spacers 172 of the second gate structure GS-2. As shown in Fig. 2C, the inner edge of the first source region 180 is aligned with an outer edge OE1-1 of the left portion of the first gate spacers 171, and the inner edge of the first drain region 181 is aligned with an outer edge OE1-2 of the right portion of the first gate spacers 171. The inner edge of the second source region 182 is aligned with an outer edge OE2-1 of the left portion of the second gate spacers 172, and the inner edge of the second drain region 183 is aligned with an outer edge OE2-2 of the right portion of the second gate spacers 172.

[0055] Furthermore, in some embodiments of the present disclosure, no spacer material covers a top surface 180a of the first source region 180 and a top surface 181a of the first drain region 181. Therefore, the entire top surface 180a of the first source region 180 and the top surface 181a of the first drain region 181 provide large areas for creating silicide regions (not shown) on the first source region 180 and the first drain region 181 in the later process. Furthermore, in some embodiments of the present disclosure, no spacer material covers a top surface 182a of the second source region 182 and a top surface 183a of the second drain region 183. Therefore, the entire top surface 182a of the second source region 182 and the top surface 183a of the second drain region 183 provide large areas for creating silicide regions (not shown) on the second source region 182 and the second drain region 183 in the later process.

[0056] Furthermore, in some embodiments, after creating the first source region 180 and the first drain region 181, a left portion of the first lightly doped region 161 is located between the first source region 180 and the first gate structure GS-1, and a right portion of the first lightly doped region 161 is located between the first drain region 181 and the first gate structure GS-1. After creating the second source region 182 and the second drain region 183, a left portion of the second lightly doped region 162 is located between the second source region 182 and the second gate structure GS-2, and a right portion of the second lightly doped region 162 is located between the second drain region 183 and the second gate structure GS-2.

[0057] As in Fig. 2C, in some embodiments, the left portion of the first lightly doped region 161 is located under the left portion of the first gate spacer 171 and is adjacent to the left sidewall of the first gate structure GS-1. The right portion of the first lightly doped region 161 is located under the right portion of the first gate spacer 171 and is adjacent to the right sidewall of the first gate structure GS-1. In some embodiments, the left portion of the second lightly doped region 162 is located under the left portion of the second gate spacer 172 and is adjacent to the left sidewall of the second gate structure GS-2. The right portion of the second lightly doped region 162 is located under the right portion of the second gate spacer 172 and is adjacent to the right sidewall of the second gate structure GS-2.

[0058] Since the first source region 180 and the first drain region 181 are formed using the first gate structure GS-1 and the first gate spacers 171 as an implantation mask, after the first source region 180 and the first drain region 181 are formed, the outer edges of the first lightly doped regions 161 that contact the first source region 180 and the first drain region 181 are each aligned with the outer edges of the opposite parts of the first gate spacers 171. For example, the outer edge of the left part of the first lightly doped region 161 is aligned with the outer edge OE1-1 of the left part of the first gate spacers 171, and the outer edge of the right part of the first lightly doped region 161 is aligned with the outer edge OE1-2 of the right part of the first gate spacers 171.

[0059] Similarly, since the second source region 182 and the second drain region 183 are formed using the second gate structure GS-2 and the second gate spacer 172 as an implantation mask, after forming the second source region 182 and the second drain region 183, the outer edges of the second lightly doped regions 162 that contact the second source region 182 and the second drain region 183 are each aligned with the outer edges of the opposite portions of the second gate spacers 172. For example, the outer edge of the left portion of the second lightly doped region 162 is aligned with the outer edge OE2-1 of the left portion of the second gate spacers 172, and the outer edge of the right portion of the second lightly doped region 162 is aligned with the outer edge OE2-2 of the right portion of the second gate spacers 172.

[0060] In Fig. 2D, in some embodiments, an interlayer dielectric (ILD) layer 190 is formed over the semiconductor substrate 100. Then, contact pins are formed by filling contact openings (not shown) in the ILD layer 190 with conductive materials. As shown in Fig. As shown in Figure 2D, first contact pins 210, 211, and 215 contact the first source region 180, the first drain region 181, and the first gate structure GS-1, respectively. Second contact pins 212, 213, and 216 contact the second source region 182, the second drain region 183, and the second gate structure GS-2, respectively. In particular, the first contact pins 215 and 216 contact the first gate layer 151 of the first gate structure GS-1 and the second gate layer 152 of the second gate structure GS-2, respectively.

[0061] In some embodiments, prior to deposition of the ILD layer 190, silicide regions (not shown) may also be formed on the first source region 180, the first drain region 181, and the first gate layer 151 of the first gate structure GS-1, as well as on the second source region 182, the second drain region 183, and the second gate layer 152 of the second gate structure GS-2, in order to reduce the gate contact resistance and the source / drain contact resistance. In some embodiments, the silicide regions may be formed by protective deposition of a metal layer (not shown) on the previously fabricated structure formed in Fig. 2C, and then an annealing process is performed. During annealing, the metal layer reacts with the underlying silicon, and silicide regions are formed on the first source region 180, the first drain region 181, and the first gate layer 151 of the first gate structure GS-1, as well as on the second source region 182, the second drain region 183, and the second gate layer 152 of the second gate structure GS-2. After the annealing process, the unreacted metal layer is removed.

[0062] Furthermore, in some embodiments, after creating the silicide regions, a contact etch stop layer (not shown) is formed by a protective deposition to protect the entire structure from Fig. 2C. The contact etch stop layer can act as an etch stop layer during the creation of contact openings, thereby protecting deeper areas from overetching. Furthermore, the contact etch stop layer applies stress, particularly tensile stress for an NMOS transistor, to the semiconductor device, increasing carrier mobility. Then, the ILD layer 190 is deposited on the contact etch stop layer. Subsequently, contact openings are created through the ILD layer 190, which are then filled with a conductive material layer.A planarization process, such as chemical mechanical planarization, another suitable planarization method, or a combination thereof, is then performed to planarize the conductive material layer and the interlayer dielectric material, thereby forming the contact pins 210, 211, 212, 213, 215, and 216 in the ILD layer 190 with planarized top surfaces, as shown in FIG. Fig. 2D. In some embodiments, contact pins 210, 211, and 215 contact the silicide regions (not shown) on the first source region 180, the first drain region 181, and the first gate layer 151, respectively, of the first gate structure GS-1. In some embodiments, contact pins 212, 213, and 216 contact the silicide regions (not shown) on the second source region 182, the second drain region 183, and the second gate layer 152, respectively, of the second gate structure GS-2.

[0063] In a conventional semiconductor device, a larger distance between the drain and gate or an STI interlayer between the drain and gate is implemented to avoid the HCI effect. However, these conventional modifications also reduce the device resistance (such as the on-resistance R on ) of the semiconductor device. In general, the HCI lifetime decreases with increasing threshold voltage (Vt) of the semiconductor device (as in Fig. 8). However, the device resistance (such as the on-resistance R on ) with increasing threshold voltage (Vt) of the semiconductor device (as in Fig. 8). Therefore, it is important for a semiconductor device with a suitable threshold voltage (Vt) to not only meet the design requirements but also achieve the optimal HCI lifetime and device resistance.

[0064] In some embodiments, a semiconductor device structure includes two or more devices on the semiconductor substrate, and the gate dielectric layers of the devices, made from different dielectric material compositions, have their own dielectric constants. By fabricating the gate dielectric layers with different dielectric material compositions and their own dielectric constants, in some embodiments of the present disclosure, the HV devices fabricated on the same semiconductor substrate 100 could have specific threshold voltages (Vt) that not only meet the design requirements (i.e., provide good electrical properties) but also achieve the optimal HCI lifetime and device resistance.

[0065] The configurations of the gate dielectric layers of the gate structures of the different devices in the above embodiment, such as the first gate dielectric layer 131 of the first gate structure GS-1 and the second gate dielectric layer 132 of the second gate structure GS-2 each comprising a single dielectric material layer in the Fig. 2A to 2D are merely illustrative of some possible types. According to the present disclosure, one or more devices may include a gate dielectric layer comprising multiple dielectric material layers.

[0066] Fig. 3 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. The intermediate structure of Fig. 3 is identical to the intermediate structure of Fig. 2C. The same or similar structural elements of the structures in the Fig. 2C and Fig. 3 are designated the same or similarly for the sake of simplicity and clarity.

[0067] The configurations of the same or similar elements in the Fig. 2C and Fig. 3 have already been described in the above embodiments and will not be repeated here. In addition, the method for manufacturing the structure of Fig. 3, which includes the p-well regions 104, the n-well regions 106, and the isolation regions 108 in the semiconductor substrate 100, the first gate structure GS-1, the first lightly doped regions 161, the first gate spacers 171, the first source region 180, and the first drain region 181 of the first device 10-1, the second gate structure GS-2, the second lightly doped regions 162, the second gate spacers 172, the second source region 182, and the second drain region 183 of the second device 10-2, is similar to the method of manufacturing the structure in the above-described embodiment, and the process details will not be repeated here.

[0068] In Fig. 3, in some embodiments, the first gate dielectric layer 131 is a single dielectric material layer, and the second gate dielectric layer 132 comprises two dielectric material layers 132a and 132b. The two dielectric material layers 132a and 132b together form a second gate dielectric layer 132-1 of the second gate structure GS-2. The first gate dielectric layer 131 and the dielectric material layer 132a may comprise the same dielectric material and may be formed using the same deposition process on the semiconductor substrate 100. The dielectric material layers 132a and 132b may include different dielectric materials. The dielectric material layer 132b is formed on the dielectric material layer 132a after the first gate dielectric layer 131 and the dielectric material layer 132a have been formed on the semiconductor substrate 100.Thus, the first gate dielectric layer 131 and the second gate dielectric layer 132-1 have different dielectric material compositions.

[0069] In some embodiments, the first gate dielectric layer 131 of the first gate structure GS-1 has a first thickness t1, and the second gate dielectric layer 132-1 of the second gate structure GS-2 has a second thickness t2. In some embodiments, the first thickness t1 is equal to the second thickness t2. In some further embodiments, the first thickness t1 is different from the second thickness t2. In this exemplary embodiment, the dielectric material layers 132a and 132b have a thickness t-2a and a thickness t-2b, respectively. In some embodiments, the first thickness t1 of the first gate dielectric layer 131 is equal to the thickness t-2a of the dielectric material layer 132a of the second gate dielectric layer 132-1. In some further embodiments, the first thickness t1 of the first gate dielectric layer 131 is different from the thickness t-2a of the dielectric material layer 132a of the second gate dielectric layer 132-1.

[0070] In some embodiments, the first thickness t1 of the first gate dielectric layer 131 may be about 0.1 nm to about 5 nm. The second thickness t2 of the second gate dielectric layer 132-1 may also be about 0.1 nm to about 5 nm. It should be noted that these numerical values ​​for the first gate dielectric layer 131 and the second gate dielectric layer 132-1 are only exemplary. Depending on the design requirements, any suitable numerical values ​​for the first thickness t1 of the first gate dielectric layer 131 and the second thickness t2 of the second gate dielectric layer 132-1 may be used.

[0071] In the devices exemplified in the semiconductor device structure of Fig. 3, the gate dielectric layers of the high-voltage devices made of different dielectric material compositions have different dielectric constants. In some embodiments, the first gate dielectric layer 131 of the first gate structure GS-1 and the second gate dielectric layer 132-1 of the second gate structure GS-2 are high-k dielectric layers. The dielectric constant of the first gate dielectric layer 131 may be equal to or greater than 20. The dielectric constant of the second gate dielectric layer 132-1 may also be equal to or greater than 20. In one example, the dielectric constant of the second gate dielectric layer 132-1 is greater than the dielectric constant of the first gate dielectric layer 131.In embodiments, different threshold voltages (Vt) for the high-voltage devices fabricated on the same semiconductor substrate 100 can be achieved by adjusting the material composition and dielectric constant for the first gate dielectric layer 131 and the second gate dielectric layer 132-1, respectively. By fabricating the gate dielectric layers with different dielectric material compositions and distinct dielectric constants, in some embodiments of the present disclosure, the HV devices fabricated on the same semiconductor substrate 100 could have specific threshold voltages (Vt) that not only meet the design requirements (i.e., provide good electrical properties) but also achieve the optimal HCI lifetime and device resistance.

[0072] The configurations of the gate structures of different devices in the above embodiments, such as the first gate layer 151 of the first gate structure GS-1 and the second gate layer 152 of the second gate structure GS-2 each comprising a single dielectric material layer in the Fig. 2A to 2D and 3 are merely illustrative of some possible types. According to the present disclosure, depending on the design requirements, one or more devices may have a gate layer comprising multiple conductive material layers (e.g., metallic material layers).

[0073] Fig. 4 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. The main difference between the intermediate structures in the Fig. 4 and 2A to 2D is the number of conductive material layers in the second gate layers 153 and 154. The second gate layer 153 in the Fig. 2A to 2D comprises only one conductive material layer, and the second gate layer 154 in Fig. 4 comprises two conductive material layers. The same or similar structural elements of the structures in the Fig. 2A to 2D and 4 are designated the same or similarly for the sake of simplicity and clarity. Furthermore, the structures and methods for their manufacture or similar elements are described in the Fig. 2A to 2D and 4 have already been described in the above embodiments, and the details will not be repeated here.

[0074] In Fig. 4, in some embodiments, the first gate layer 153 is a single conductive material layer, and the second gate layer 154 includes two conductive material layers 154a and 154b. The two conductive material layers 154a and 154b together form the second conductive gate layer 154 of the second gate structure GS-2. The conductive material layers 154a and 154b may include different conductive materials. In some embodiments, the conductive material layer 154a includes one or more metallic p-type materials, and the conductive material layer 154b includes one or more metallic n-type materials. Furthermore, the first gate layer 153 and the conductive material layer 154b of the second gate layer 154 may include the same conductive material and may be formed in the same deposition process.In some embodiments, the first gate layer 153 and the conductive material layer 154b are formed after the conductive material layer 154a is formed on the second gate dielectric layer 132. Furthermore, the first gate dielectric layer 131 under the first gate layer 153 and the second gate dielectric layer 132-1 under the second gate layer 154 have different dielectric material compositions.

[0075] In some embodiments, the first gate layer 153 of the first gate structure GS-1 has a first gate thickness T1, and the second gate layer 154 of the second gate structure GS-2 has a second gate thickness T2. In some embodiments, the first gate thickness T1 is different from the second gate thickness T2. In this exemplary embodiment, the conductive material layers 154a and 154b have a gate thickness T-2a and a gate thickness T-2b, respectively. The gate thickness T-2a may be the same as or different from the gate thickness T-2b. The first gate thickness T1 of the first gate layer 153 may be the same as or different from the gate thickness T-2b of the conductive material layer 154b of the second gate layer 154.

[0076] In some embodiments, the first gate layer 153 is a metallic n-type material layer, the conductive material layer 154a of the second gate layer 154 is a metallic p-type material layer, and the conductive material layer 154b of the second gate layer 154 is a metallic n-type material layer. In some embodiments, the thickness of the metallic p-type material layer is about 0.1 nm to about 5 nm. In some embodiments, the thickness of the metallic n-type material layer is about 0.1 nm to about 50 nm. It should be noted that these numerical values ​​for the first gate layer 153 and the second gate layer 154 are only exemplary. Depending on the design requirements, any suitable numerical values ​​for the gate thickness T1 of the first gate layer 153 and the gate thicknesses T-2a and T-2b of the second gate layer 154 may be used.

[0077] In the devices used in the semiconductor device structure of Fig. 4, the gate dielectric layer of one high-voltage device has a dielectric material composition that is different from that of the gate dielectric layer of the other high-voltage device. Furthermore, the high-voltage devices have different gate heights. Accordingly, the high-voltage devices fabricated on the same semiconductor substrate 100 have different specific threshold voltages (Vt), as exemplified in Fig. 4. That is, the specific threshold voltages of the high-voltage devices can be fine-tuned in some embodiments. Therefore, these high-voltage devices with specific threshold voltages can meet the electrical property requirements and also achieve the optimal HCI lifetime and device resistance (such as on-resistance).

[0078] Fig. 5 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. The difference between the intermediate structures in the Fig. 5 and 2A to 2D consists in the configurations of the gate structures. In Fig. 5, the first gate dielectric layer 131 is a single dielectric material layer, and the second gate dielectric layer 132-1 comprises two dielectric material layers 132a and 132b. The materials and configurations for the first gate dielectric layer 131 and the second gate dielectric layer 132-1 have already been described in the previous embodiments, and the details will not be repeated here.

[0079] In this exemplary embodiment, a first gate layer 155 comprises two conductive material layers 155a and 155b, and a second gate layer 156 comprises three conductive material layers 156a, 156b, and 156c, as shown in Fig. 5. The same or similar structural elements of the structures in the Fig. 2A to 2D, 3 and 5 are designated the same or similarly for the sake of simplicity and clarity. Furthermore, the structures and methods for their manufacture or similar elements are described in the Fig. 2A to 2D, 3 and 5 have already been described in the previous embodiments, and the details will not be repeated here.

[0080] In some embodiments, the conductive material layer 155a of the first gate layer 155 is a metallic p-type material layer, and the conductive material layer 155b of the first gate layer 155 is a metallic n-type material layer. In some embodiments, the conductive material layers 156a and 156b of the second gate layer 156 are metallic p-type material layers, and the conductive material layer 156c of the second gate layer 156 is a metallic n-type material layer. In some embodiments, the thickness of the metallic p-type material layer is about 0.1 nm to about 5 nm. In some embodiments, the thickness of the metallic n-type material layer is about 0.1 nm to about 50 nm. Note that these numerical values ​​for the first gate layer 155 and the second gate layer 156 are only exemplary.Depending on the design requirements, any suitable numerical values ​​for the gate thicknesses of the first gate layer 155 and the second gate layer 156 may be used.

[0081] In the devices used in the semiconductor device structure of Fig. 5, the gate dielectric layer of one high-voltage device has a dielectric material composition that is different from that of the gate dielectric layer of the other high-voltage device. Furthermore, the high-voltage devices have different gate heights. Accordingly, the high-voltage devices fabricated on the same semiconductor substrate 100 have different specific threshold voltages (Vt), as exemplified in Fig. 5. That is, the specific threshold voltages of the high-voltage devices can be fine-tuned in some embodiments. Therefore, these high-voltage devices with specific threshold voltages can meet the electrical property requirements, and the specific threshold voltages also achieve the optimal HCI lifetime and device resistance (such as on-resistance).

[0082] While the previous embodiments provide two high voltage devices fabricated on the same semiconductor substrate 100 and having different threshold voltages, three or more devices having different threshold voltages may be fabricated on the semiconductor substrate 100, and in some embodiments of the present disclosure, these threshold voltages may be fine-tuned.

[0083] As an example to explain one of the embodiments, three devices are fabricated on the semiconductor substrate 100. See the Fig. 1 and Fig. 6. Fig. 6 is a cross-sectional view of an intermediate stage of a semiconductor device structure according to some embodiments of the present disclosure. The same or similar structural elements of the structures in the Fig. 2A to 2D, 3, 4, 5 and 6 are designated the same or similarly for the sake of simplicity and clarity. Furthermore, the structures and methods for their manufacture or similar elements are described in the Fig. 2A to 2D, 3, 4, 5 and 6 have already been described in the previous embodiments, and the details will not be repeated here.

[0084] In this exemplary embodiment, the first device 10-1 (e.g., the first HVMOS transistor) is fabricated in the first region 10A, the second device 10-2 (e.g., the second HVMOS transistor) is fabricated in the second region 10B, and the third device 10-3 (e.g., the third HVMOS transistor) is fabricated in the third region 10C. In Fig. 6, the first device 10-1, the second device 10-2, and the third device 10-3 include the first gate structure GS-1, the second gate structure GS-2, and the third gate structure GS-3, respectively. In some embodiments, a third gate dielectric layer 733 of the third gate structure GS-3 and a first gate dielectric layer 731 of the first gate structure GS-1 have different dielectric material compositions. In some embodiments, the third gate dielectric layer 733 of the third gate structure GS-3 and a second gate dielectric layer 732 of the second gate structure GS-2 have different dielectric material compositions.

[0085] In these exemplary embodiments, the first gate structure GS-1 of the first device 10-1 includes a first gate dielectric layer 731 and a first gate layer 751 on the first gate dielectric layer 731. The second gate structure GS-2 of the second device 10-2 includes a second gate dielectric layer 732 and a second gate layer 752 on the second gate dielectric layer 732. The second gate dielectric layer 732 includes a plurality of dielectric material layers, such as two dielectric material layers 732a and 732b. The third gate structure GS-3 of the third device 10-3 includes a third gate dielectric layer 733 and a third gate layer 753 on the third gate dielectric layer 733. The third gate dielectric layer 733 also includes a plurality of dielectric material layers, such as three dielectric material layers 733a, 733b, and 733c.

[0086] The first gate dielectric layer 731 of the first gate structure GS-1, the dielectric material layer 732a of the second gate structure GS-2, and the dielectric material layer 733a of the third gate structure GS-3 may comprise the same dielectric material and may be formed on the semiconductor substrate 100 using the same deposition process. The dielectric material layers 732a and 732b of the second gate structure GS-2 may comprise different dielectric materials. The dielectric material layers 733a and 733b of the third gate structure GS-3 may also comprise different dielectric materials. The dielectric material layers 733b and 733c of the third gate structure GS-3 may comprise the same dielectric material or different dielectric materials.In one example, the dielectric material layer 732b is formed on the dielectric material layer 732a, and the dielectric material layers 733b and 733c are formed on the dielectric material layer 733a after the first gate dielectric layer 731 and the dielectric material layer 732a have been formed on the semiconductor substrate 100.

[0087] In some embodiments, the first gate dielectric layer 731 of the first gate structure GS-1, the second gate dielectric layer 732 of the second gate structure GS-2, and the third gate dielectric layer 733 of the third gate structure GS-3 are high-k dielectric layers. The first gate dielectric layer 731, the second gate dielectric layer 732, and the third gate dielectric layer 733 may each have a dielectric constant equal to or greater than 20.

[0088] In some embodiments, the dielectric constant of the second gate dielectric layer 732 is greater than the dielectric constant of the first gate dielectric layer 731, and the dielectric constant of the third gate dielectric layer 733 is greater than the dielectric constant of the second gate dielectric layer 732. In one example, the dielectric constant of the first gate dielectric layer 731 is about 20 to about 25, the dielectric constant of the second gate dielectric layer 732 is about 23 to about 28, and the dielectric constant of the third gate dielectric layer 733 is about 25 to about 30.

[0089] According to the embodiments, a wafer may include multiple high-voltage devices, and the gate dielectric layers of the respective high-voltage devices are formed from different high-k dielectric materials, thereby achieving the required threshold voltages (Vt) of the devices. Examples of the materials from which the first gate dielectric layer 731, the second gate dielectric layer 732, and the third gate dielectric layer 733 are formed are hafnium oxide (HfO x ), lanthanum oxide (LaO x ), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof. In one example, the first gate dielectric layer 731 and the dielectric material layers 732a and 733a are formed of hafnium oxide (HfO x), while the dielectric material layers 732b, 733b and 733c are made of lanthanum oxide (LaO x ) can be produced.

[0090] The first dielectric gate layer 731, the second dielectric gate layer 732, and the third dielectric gate layer 733 may include the same number or different numbers of dielectric material layers. The numbers of dielectric material layers in the first dielectric gate layer 731, the second dielectric gate layer 732, and the third dielectric gate layer 733 are not limited to this exemplary embodiment. Furthermore, the first gate layer 751, the second gate layer 752, and the third gate layer 753 may each include only one conductive material layer (as in Fig. 6) or multiple conductive material layers. The first gate layer 751, the second gate layer 752, and the third gate layer 753 may contain the same number or different numbers of conductive material layers. The numbers of conductive material layers in the first gate layer 751, the second gate layer 752, and the third gate layer 753 are not limited to this exemplary embodiment.

[0091] In some embodiments, the first gate dielectric layer 731 has a first thickness t1, the second gate dielectric layer 732 has a second thickness t2, and the third gate dielectric layer 733 has a third thickness t3. In this example, the first thickness t1, the second thickness t2, and the third thickness t3 are different from each other.

[0092] In some embodiments, the first thickness t1 of the first gate dielectric layer 731 may be about 0.1 nm to about 5 nm. The second thickness t2 of the second gate dielectric layer 732 may also be about 0.1 nm to about 5 nm. The third thickness t3 of the third gate dielectric layer 733 may also be about 0.1 nm to about 5 nm. It should be noted that these numerical values ​​for the first gate dielectric layer 731, the second gate dielectric layer 732, and the third gate dielectric layer 733 are only exemplary. Depending on the design requirements, any suitable numerical values ​​for the first thickness t1 of the first gate dielectric layer 731, the second thickness t2 of the second gate dielectric layer 732, and the third thickness t3 of the third gate dielectric layer 733 may be used.

[0093] In the devices exemplified in the semiconductor device structure of Fig. 6, the gate dielectric layer of a high-voltage device has a dielectric material composition that differs from that of the gate dielectric layers of other high-voltage devices. Furthermore, the three high-voltage devices have different gate heights. Accordingly, the high-voltage devices fabricated on the same semiconductor substrate 100 have different specific threshold voltages (Vt), as exemplified in Fig. 6. That is, the specific threshold voltages of the high-voltage devices can be fine-tuned in some embodiments. Therefore, these high-voltage devices with specific threshold voltages can meet the electrical property requirements and also achieve the optimal HCI lifetime and device resistance (such as on-resistance).

[0094] Fig. 7A shows cross-sectional views of other gate structures of the devices on a semiconductor substrate according to some embodiments of the present disclosure. In Fig. 7A, nine gate structures are provided, and for simplicity of illustration, only a single gate dielectric layer of each gate structure is shown. Note that the configurations of the gate structures are merely examples. The gate dielectric layer of each gate structure may be only one dielectric material layer or a multilayer structure composed of multiple dielectric materials. Furthermore, the gate layer of each gate structure may include one or more conductive material layers. For example, the gate layer may include only one n-type metallic material, or it may also include one or more p-type metallic materials.

[0095] In Fig. 7A, gate structures GS-1, GS-2, GS-3, GS-4, GS-5, GS-6, GS-7, GS-8, and GS-9 are formed on semiconductor substrate 100. These gate structures include gate dielectric layers 831, 832, 833, 834, 835, 836, 837, 838, and 839, respectively. Gate structures GS-1, GS-2, GS-3, GS-4, GS-5, GS-6, GS-7, GS-8, and GS-9 include gate layers 851, 852, 853, 854, 855, 856, 857, 858, and 859, respectively.

[0096] In this exemplary embodiment, three different gate dielectric materials HK-1, HK-2, and HK-3 are implemented in these gate dielectric layers. That is, each of the gate dielectric layers 831, 834, and 837 comprises the gate dielectric material HK-1. Each of the gate dielectric layers 832, 835, and 838 comprises the gate dielectric material HK-2. Each of the gate dielectric layers 833, 836, and 839 comprises the gate dielectric material HK-3.

[0097] In this example, three different combinations of conductive material layers are implemented to provide different gate layers. For example, each of gate layers 851, 852, and 853 includes a metallic n-type material layer. Each of gate layers 854, 855, and 856 includes a metallic p-type material layer and a metallic n-type material layer formed on the metallic p-type material layer. Each of gate layers 857, 858, and 859 includes two metallic p-type material layers and a metallic n-type material layer formed on the metallic p-type material layers.

[0098] The gate structures, which are exemplified in Fig. 7A, the devices with the gate structures fabricated on the same semiconductor substrate 100 have nine different specific threshold voltages, such as Vt_1, Vt_2, Vt_3, Vt_4, Vt_5, Vt_6, Vt_7, Vt_8, and Vt_9. These specific threshold voltages of the high-voltage devices can be controlled and fine-tuned in some embodiments by implementing different dielectric material compositions for forming the gate dielectric layers of different devices. In some embodiments, different combinations of conductive material layers are also implemented during gate layer formation, resulting in devices with their own specific threshold voltages.

[0099] Fig. 7B shows cross-sectional views of different gate structures of conventional devices on a semiconductor substrate. Conventionally, the gate dielectric layers of devices fabricated on the same semiconductor substrate 100 are formed from the same dielectric material compositions. For example, each of a plurality of gate dielectric layers 931 of gate structures GS-C1, GS-C2, GS-C3, GS-C4, GS-C5, and GS-C6 comprises the same gate dielectric material HK. Specific threshold voltages of the devices, such as threshold voltages Vt_C1, Vt_C2, Vt_C3, Vt_C4, Vt_C5, and Vt_C6, are controlled with the materials and configurations of gate layers 951, 952, 953, 954, 955, and 956, respectively. Fig. 7B, gate layer 951 of gate structure GS-C1 includes a p-type metallic material layer and an n-type metallic material layer formed on the p-type metallic material layer. Gate layer 952 of gate structure GS-C2 includes two p-type metallic material layers and one n-type metallic material layer formed on the p-type metallic material layers. Gate layer 953 of gate structure GS-C3 includes three p-type metallic material layers and one n-type metallic material layer formed on the p-type metallic material layers. Gate layer 954 of gate structure GS-C4 includes four p-type metallic material layers and one n-type metallic material layer formed on the p-type metallic material layers. Gate layer 955 of gate structure GS-C5 includes five p-type metallic material layers and one n-type metallic material layer formed on the p-type metallic material layers.The gate layer 956 of the gate structure GS-C6 includes six p-type metallic material layers and one n-type metallic material layer formed on the p-type metallic material layers. Since the threshold voltage is determined by the number of conductive material layers of the gate layer, it is difficult to fine-tune the threshold voltages of these conventional devices due to the conventional design of the gate structures GS-C1, GS-C2, GS-C3, GS-C4, GS-C5, and GS-C6. Furthermore, the process for fabricating the conventional gate structure (e.g., GS-C1, GS-C2, GS-C3, GS-C4, GS-C5, and GS-C6), especially a high-k metal gate structure (HKMG structure), is complicated, resulting in an offset between the conductive material layers (e.g., the metallic material layers) in a stack of the gate structure.

[0100] Fig. Figure 8 shows a trade-off between the HCI lifetime and the device resistance of a high-voltage semiconductor device. Typically, the HCI lifetime decreases with increasing threshold voltage (Vt) of the semiconductor device. Furthermore, the device resistance (such as the on-resistance R on ) increases with increasing threshold voltage (Vt) of the semiconductor device. The curve Css represents the optimal curve of the HCI lifetime and the device resistance (such as the on-resistance). On the curve Css of Fig. 8 are the nine different specific threshold voltages of the devices ( Fig. 7A) of the above-described embodiments, namely Vt_1, Vt_2, Vt_3, Vt_4, Vt_5, Vt_6, Vt_7, Vt_8 and Vt_9. On the curve Css of Fig. 8 also shows the six different specific threshold voltages of the conventional devices described above ( Fig. 7B), namely Vt_C1, Vt_C2, Vt_C3, Vt_C4, Vt_C5 and Vt_C6.

[0101] Fig. Figure 8 clearly shows that the threshold voltages of the high-voltage devices can be fine-tuned by fabricating the dielectric gate layers with different dielectric material compositions or further by fabricating the gate layers with different combinations of conductive material layers. In the devices in the Fig. 7A and Fig. 7B and the curve Css of Fig.8, the difference between the threshold voltages Vt_1 and Vt_2 is smaller than the difference between the threshold voltages Vt_C1 and Vt_C2. The difference between the threshold voltages Vt_3 and Vt_4 is smaller than the difference between the threshold voltages Vt_C2 and Vt_C3. The difference between the threshold voltages Vt_5 and Vt_6 is smaller than the difference between the threshold voltages Vt_C3 and Vt_C4. The difference between the threshold voltages Vt_8 and Vt_9 is smaller than the difference between the threshold voltages Vt_C5 and Vt_C6. Thus, in some embodiments, the specific threshold voltages of the high-voltage devices can be fine-tuned.According to the embodiments, these high-voltage devices can be manufactured with specific threshold voltages to meet the electrical property requirements and also achieve the optimal HCI lifetime and device resistance (such as on-resistance).

[0102] According to some embodiments described above, the semiconductor device structure and method of fabricating it offer several advantages. In some embodiments, by implementing the gate dielectric layer with appropriate dielectric materials (such as one or more high-k dielectric materials) in each of the gate structures of the devices, the HCI effect is avoided, thereby improving the electrical properties of the devices. Furthermore, in some embodiments, different threshold voltages (Vt) of devices (such as high-voltage devices) fabricated on the same semiconductor substrate 100 can be fine-tuned by adjusting the material composition and dielectric constant of each of the gate dielectric layers of the devices.In some embodiments of the present disclosure, each of the devices can be operated within a suitable window of HCI lifetime and device resistance by providing flexible threshold voltages (Vt). That is, by fabricating the gate layers with different gate dielectric layers (having different dielectric material compositions and distinct dielectric constants), in some embodiments, the semiconductor devices could have specific threshold voltages (Vt) that not only meet the design requirements (i.e., provide good electrical properties) but also achieve the optimal HCI lifetime and device resistance.Furthermore, in some embodiments, the semiconductor device structure and the method for manufacturing it reduce the process complexity in manufacturing the gate structure, thereby solving the existing problem of offset of the structural elements (e.g., offset between the conductive material layers in a stack of the gate structure) and improving the electrical properties of the devices.

Claims

[1] Semiconductor device structure comprising: a semiconductor substrate (100); a first transistor fabricated in a first region of the semiconductor substrate, the first transistor having a first gate structure on the semiconductor substrate over a junction between a p-well region (104) and an n-well region (106), the first gate structure comprising: a first dielectric gate layer (131; 731; 831) on the semiconductor substrate, and a first gate layer (151; 751; 851) on the first gate dielectric layer; and a second transistor fabricated in a second region of the semiconductor substrate, the second transistor having a second gate structure on the semiconductor substrate over a junction between a p-well region (104) and an n-well region (106), the second gate structure comprising: a second dielectric gate layer (132; 732; 832) on the semiconductor substrate, and a second gate layer (152; 752; 852) on the second gate dielectric layer, wherein the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor have different dielectric material compositions and the transistors have different threshold voltages. [2] The semiconductor device structure of claim 1, wherein the first gate dielectric layer has a first dielectric constant and the second gate dielectric layer has a second dielectric constant, the first dielectric constant being different from the second dielectric constant, optionally wherein the second dielectric constant of the second gate dielectric layer is greater than the first dielectric constant of the first gate dielectric layer. [3] The semiconductor device structure according to claim 1 or 2, wherein the first transistor and the second transistor are high voltage metal oxide semiconductor transistors. [4] A semiconductor device structure according to any preceding claim, wherein the first dielectric constant of the first gate dielectric layer and the second dielectric constant of the second gate dielectric layer are equal to or greater than 20. [5] A semiconductor device structure according to any preceding claim, wherein the first gate dielectric layer has a first thickness and the second gate dielectric layer has a second thickness, the first thickness being equal to or different from the second thickness. [6] A semiconductor device structure according to any preceding claim, wherein the first thickness of the first gate dielectric layer is 0.1 nm to 5 nm and the second thickness of the second gate dielectric layer is also 0.1 nm to 5 nm. [7] A semiconductor device structure according to any preceding claim, wherein the first gate dielectric layer is a single dielectric material layer and the second gate dielectric layer comprises a plurality of dielectric material layers (132a, 132b; 732a, 732b). [8] A semiconductor device structure according to any one of claims 1 to 6, wherein the first gate dielectric layer and the second gate dielectric layer each comprise a plurality of dielectric material layers, wherein optionally, the first dielectric gate layer has a different number of dielectric material layers than the second dielectric gate layer, or the first gate dielectric layer has the same number of dielectric material layers as the second gate dielectric layer. [9] A semiconductor device structure according to any preceding claim, wherein the first gate layer of the first gate structure is a single metallic n-type material layer and the second gate layer of the second gate structure comprises a plurality of conductive material layers. [10] A semiconductor device structure according to any one of claims 1 to 8, wherein the first gate layer of the first gate structure and the second gate layer of the second gate structure each comprise a plurality of conductive material layers, wherein optionally, the first gate layer of the first gate structure has a different number of conductive material layers than the second gate layer of the second gate structure, or the first gate layer of the first gate structure has the same number of conductive material layers as the second gate layer of the second gate structure. [11] A semiconductor device structure according to any one of the preceding claims, wherein the first gate layer of the first gate structure and the second gate layer of the second gate structure each comprise: one or more conductive p-type material layers formed over the semiconductor substrate; and a metallic n-type material layer formed on the one or more conductive p-type material layers, optionally wherein a thickness of the one or more conductive p-type material layers is 0.1 nm to 5 nm and a thickness of the metallic n-type material layer is 0.1 nm to 50 nm. [12] A semiconductor device structure according to any one of the preceding claims, wherein the first gate dielectric layer and the second gate dielectric layer each comprise hafnium oxide (HfO x ), lanthanum oxide (LaO x ), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or a combination thereof. [13] A semiconductor device structure according to any preceding claim, further comprising: a third transistor formed in a third region of the semiconductor substrate, the third transistor having a third gate structure on the semiconductor substrate, the third gate structure comprising: a third dielectric gate layer on the semiconductor substrate; and a third gate layer on the third gate dielectric layer, wherein the third gate dielectric layer and the first gate dielectric layer have different dielectric material compositions and the third gate dielectric layer and the second gate dielectric layer also have different dielectric material compositions. [14] A semiconductor device structure according to claim 13, wherein the first gate dielectric layer has a first dielectric constant, the second gate dielectric layer has a second dielectric constant, and the third gate dielectric layer has a third dielectric constant, wherein the first, second, and third dielectric constants are different from each other, wherein optionally the first, second and third dielectric constants are each equal to or greater than 20. [15] A semiconductor device structure according to claim 13 or 14, wherein the first dielectric gate layer has a first thickness, the second dielectric gate layer has a second thickness, and the third dielectric gate layer has a third thickness, wherein the first, second, and third thicknesses are different from each other, and / or wherein the first thickness of the first gate dielectric layer is 1 nm to 5 nm, the second thickness of the second gate dielectric layer is also 1 nm to 5 nm, and the third thickness of the third gate dielectric layer is also 1 nm to 5 nm. [16] The semiconductor device structure of any one of claims 13 to 15, wherein at least one of the first, second and third gate dielectric layers comprises a plurality of dielectric material layers. [17] A semiconductor device structure according to claim 16, wherein the second dielectric gate layer has a different number of dielectric material layers than the third dielectric gate layer, or the second gate dielectric layer has the same number of dielectric material layers as the third gate dielectric layer. [18] A semiconductor device structure according to any one of claims 13 to 17, wherein one of the first, second and third gate layers is only an n-type metallic material layer and the other gate layers each comprise a plurality of conductive material layers. [19] A semiconductor device structure according to any one of claims 13 to 18, wherein the first, second and third gate layers each comprise a different number of conductive material layers. [20] A semiconductor device structure according to any one of claims 13 to 19, wherein the third gate dielectric layer comprises hafnium oxide (HfO x ), lanthanum oxide (LaO x), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or a combination thereof. [21] A semiconductor device structure according to any one of claims 13 to 20, wherein the third transistor is a high voltage metal oxide semiconductor transistor. [22] A semiconductor device structure according to any one of the preceding claims, wherein the first transistor further comprises a first source region (180) and a first drain region (181) on opposite sides of the first gate structure, and the second transistor further comprises a second source region (182) and a second drain region (183) on opposite sides of the second gate structure. [23] A method of manufacturing a semiconductor device structure, comprising: Providing a semiconductor substrate having a first and a second region; and Producing a first transistor in the first region above a junction between a p-well region and an n-well region and a second transistor in the second region above a junction between a p-well region and an n-well region, wherein the first transistor has a first gate structure on the semiconductor substrate and the second transistor has a second gate structure on the semiconductor substrate, wherein fabricating the first gate structure comprises: Forming a first dielectric gate layer on the semiconductor substrate, and Forming a first gate layer on the first gate dielectric layer, and forming the second gate structure comprises: Forming a second dielectric gate layer on the semiconductor substrate, and Forming a second gate layer on the second dielectric gate layer, wherein the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor have different dielectric material compositions and are fabricated with different threshold voltages. [24] A method of manufacturing a semiconductor device structure according to claim 23, wherein the first dielectric gate layer has a first dielectric constant and the second dielectric gate layer has a second dielectric constant, wherein the first dielectric constant is different from the second dielectric constant, and / or the first transistor and the second transistor are high-voltage metal-oxide-semiconductor transistors, and / or the first dielectric constant of the first gate dielectric layer and the second dielectric constant of the second gate dielectric layer are equal to or greater than 20, and / or the second dielectric constant of the second gate dielectric layer is greater than the first dielectric constant of the first gate dielectric layer. [25] A method of manufacturing a semiconductor device structure according to claim 23 or 24, wherein the first gate dielectric layer has a first thickness and the second gate dielectric layer has a second thickness, wherein the first thickness is equal to the second thickness, or the first thickness is different from the second thickness.

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