Power FinFETs with alternating shielding regions and one-piece control electrodes and methods for manufacturing the same

Abstract

A method for fabricating power FinFETs with one-piece control electrodes is disclosed, wherein the power FinFET comprises a semiconductor body having a second terminal area and a drift layer, the second terminal area forming a front face of the semiconductor body. The method comprises the steps of creating a first structured mask on the front face of the semiconductor body by means of a lithography step, wherein the first structured mask has oxide regions and first open regions, the first open regions exposing the front face of the semiconductor body; creating first trenches below the first open regions by means of a first etching process starting from the front face of the semiconductor body and extending into the drift layer; creating shielding regions below the first trenches by means of a first implantation process; and depositing an isotropic oxide layer onto the front face of the semiconductor body.Creating a second structured mask by means of a second etching process, such that the isotropic oxide layer has second open regions, and the second open regions expose the front face of the semiconductor body; creating second trenches below the second open regions by means of a third etching process starting from the front face and extending into the drift layer, wherein the second trenches are substantially parallel to the first trenches, and the first and second trenches alternate, the second trenches having a narrower width than the first trenches; oxidizing the front face so that another oxide layer is arranged on the front face; widening the first and second trenches by means of a fourth etching process so that fins are formed between the first and second trenches, the fins having a width of less than 500 nm.Applying a polysilicon layer to the front of the semiconductor body so that the first and second trenches are completely filled, and activating the shielding regions by annealing.

Description

[0001] The invention relates to methods for producing power FinFETs with alternating shielding regions and one-piece control electrodes and power FinFETs with alternating shielding regions and one-piece control electrodes. State of the art

[0002] Wide-bandgap semiconductors such as SiC or GaN are used in power electronics. Power MOSFETs with a vertical channel region are typically used.

[0003] To increase the breakdown voltage of such power MOSFETs, shielding regions are arranged beneath the trenches. These shielding regions can be connected to the source regions via a contact in the trenches, forming split control electrodes within the trenches, as shown, for example, in document DE 102 24 201 B4.

[0004] A disadvantage here can be, for example, that the trenches must be very wide, resulting in large pitch dimensions and on-resistance of the power MOSFET. A form factor can be large. Furthermore, the process for manufacturing split control electrodes can be complex.

[0005] Between the shielding regions, which are typically p-doped, a so-called JFET is formed between two adjacent trenches. This serves to limit the current through the channel region in the event of a short circuit. For this purpose, p-doped shielding regions are implanted using a lithographically patterned mask.

[0006] A disadvantage here can be, for example, that the distances between two p-doped shielding regions are exposed to process fluctuations that influence the limitation of the short-circuit current.

[0007] The object of the invention is to overcome these and other disadvantages. Disclosure of the invention

[0008] The invention provides methods for manufacturing power FinFETs with alternating shielding regions and one-piece control electrodes and power FinFETs with alternating shielding regions and one-piece control electrodes according to the independent claims.

[0009] Preferred embodiments are the subject of the respective subclaims.

[0010] According to a first aspect, the invention relates to a method for producing power FinFETs with one-piece control electrodes and a semiconductor body having a second connection region and a drift layer, wherein the second connection region forms a front side of the semiconductor body, comprising producing a first structured mask on the front side of the semiconductor body using a lithography step, wherein the first mask has oxide regions and first open regions, wherein the first open regions expose the front side of the semiconductor body, and producing first trenches below the first open regions using a first etching process starting from the front side of the semiconductor body into the drift layer. Furthermore, the method comprises producing shielding regions below the first trenches using a first implantation process.The method comprises applying an isotropic oxide layer to the front side of the semiconductor body, producing a second structured mask using a second etching process such that the isotropic oxide layer has second open regions, the second open regions exposing the front side of the semiconductor body, and producing second trenches beneath the second open regions using a third etching process starting from the front side into the drift layer, the second trenches being arranged substantially parallel to the first trenches and the first trenches and the second trenches alternating, the second trenches having a smaller width than the first trenches.The method further comprises oxidizing the front side so that a further oxide layer is arranged on the front side, and widening the first trenches and the second trenches using a fourth etching process so that fins are formed between the first trenches and the second trenches, the fins having a width of less than 500 nm. The method comprises applying a polysilicon layer to the front side of the semiconductor body so that the first trenches and the second trenches are completely filled, and activating the shielding regions by means of annealing.

[0011] One advantage here may be that a short-circuit current-limiting effect is created between the shielding region and the sidewalls of the second trenches. This allows process variations to be tolerated. Furthermore, the distance between the shielding regions can be reduced.

[0012] In a further development, the first structured mask has nitride regions, wherein the oxide regions are arranged on the nitride regions.

[0013] An advantage here is that oxidation of the fin top is prevented.

[0014] In a further embodiment, spreading regions below the second trenches are created by means of a second implantation process, wherein the second implantation energy has a value between 200 keV and 2500 keV.

[0015] One advantage here may be that the on-resistance can be reduced.

[0016] In a further development, the first etching process, the second etching process and the third etching process are anisotropic plasma etching processes.

[0017] It can be advantageous that the structured masks can be transferred into the underlying layers with minimal widening.

[0018] In one embodiment, the first implantation process has a first implantation energy in the range of 30 keV to 2700 keV.

[0019] One advantage here may be that the shielding regions are created below the gate oxide to be protected in the trench bottom, so that maximum shielding effect is achieved without pitch loss.

[0020] According to a second aspect, the invention relates to a power FinFET with one-piece control electrodes and a semiconductor body having a drift layer and a second connection region. The second connection region is arranged above the drift layer, and first trenches and second trenches extend from the second connection region into the drift layer. First trenches and second trenches are arranged alternately with one another, wherein the second trenches have a smaller width than the first trenches and shielding regions are arranged below the first trenches. The shielding regions directly adjoin the first trenches, wherein the shielding regions are electrically conductively connected to source regions, wherein the electrically conductive connections are not arranged within the first trenches (206).A single-piece control electrode is arranged within each of the first trenches, each single-piece control electrode being electrically insulated from the shielding region beneath the first trenches. Fins are arranged between the first trenches and the second trenches, with the fins having a maximum width of 500 nm.

[0021] One advantage here may be that a short-circuit current can be limited by the space charge zone of the shielding regions and the opposite trench wall of a second trench. Furthermore, it may be advantageous that the influence of process variability on the short-circuit current and the on-resistance can be reduced.

[0022] In a further development, spreading areas are arranged below the second trenches.

[0023] One advantage here may be that the current spread can be increased and / or the on-resistance can be reduced.

[0024] In a further embodiment, the shielding regions are p-doped and have a dopant concentration of at least 1E18 / cm 3 on.

[0025] It may be advantageous that high implantation doses can be introduced cost-effectively below the trench floor.

[0026] In one embodiment, the semiconductor body comprises SiC.

[0027] One advantage here may be that aluminum, which is easily activated, can be used for implantation.

[0028] In a further embodiment, the semiconductor body comprises GaN.

[0029] The advantage here is that the critical field strength and electron mobility can be increased.

[0030] Further advantages will become apparent from the following description of embodiments. Short description of the drawings

[0031] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. They show: Fig. 1 a method for manufacturing a power FinFET with alternating shielding regions and one-piece control electrodes, and Fig. 2 a power FinFET with alternating shielding regions and one-piece control electrodes.

[0032] Fig. Figure 1 shows a method for manufacturing a power FinFET with alternating shielding regions without split control electrodes. The control electrodes are formed as a single piece. Generally, at least one control electrode can be formed as a single piece. Shielding regions of the power FinFET are connected to source regions. The connections are not arranged within the trenches of the power FinFET. Instead, the source regions can be electrically connected, for example, by a contact at the end of a cell array or by a deep connection region implanted, for example, at periodic intervals along a fin.

[0033] The power FinFET comprises a semiconductor body, which comprises, for example, SiC or GaN, a second connection region and a drift layer, wherein the second connection region forms a front side of the semiconductor body.

[0034] The method may include a step 105 in which a first patterned mask is created on the front side of the semiconductor body using a lithography step. The first patterned mask may include oxide regions and first open regions that expose the front side of the semiconductor body.

[0035] In a step 110, first trenches below the first open regions can be created by means of a first etching process starting from the front side of the semiconductor body into the drift layer.

[0036] In a step 115, shielding regions beneath the first trenches can be created using a first implantation process with a first implantation energy. The first implantation energy is between 30 keV and 2700 keV. The shielding regions can be p-doped.

[0037] In a step 120, an isotropic oxide layer can be applied to the front side of the semiconductor body.

[0038] In a step 125, a second structured mask may be produced by means of a second etching process, so that the isotropic oxide layer has second open regions, wherein the second open regions expose the front side of the semiconductor body.

[0039] In a step 130, second trenches can be created below the second open regions using a third etching process, starting from the front side of the semiconductor body and extending into the drift layer. The second trenches are preferably arranged parallel to the first trenches and alternate. The second trenches can have a smaller width than the first trenches.

[0040] In other words, a self-aligned mask can be created in step 125. As a result, in step 130, the second trenches can be produced sublithographically using a mask reversal process, and the width of the mesas between the first trenches and the second trenches, or the pitch, can be determined by the thickness of the isotropic oxide layer. Furthermore, precise alignment between the shielding regions below the first trenches and the opposite sidewalls of the second trenches is possible, allowing for optimal adjustment of the on-resistance, the short-circuit current, and the field in the oxide of the trench bottom of the second trenches.

[0041] In a step 135, the front side of the semiconductor body can be oxidized, so that a further oxide layer is arranged on the front side of the semiconductor body. The further oxide layer has a thickness of at least 10 nm.

[0042] In a step 140, the first trenches and the second trenches can be widened using a fourth etching process, so that fins are formed between the first trenches and the second trenches, which fins can, for example, have a width of less than 500 nm, preferably a width in the range between 400 and 50 nm, more preferably a width in the range between 200 and 50 nm. In this case, the oxide from step 135 can be selectively wet-chemically etched.

[0043] Depending on the desired fin width, steps 135 and 140 can be performed cyclically. In other words, the front side of the semiconductor body can be oxidized multiple times. An etching step can be performed between the oxidation steps. The trench widening can thus be performed without adjustment, since the lateral oxidation rate exceeds the vertical oxidation rate by approximately a factor of two.

[0044] In a step 145, a polysilicon layer can be applied to the front side of the semiconductor body so that the first trenches and the second trenches are completely filled. During subsequent etching, this can result in not only a spacer remaining on the trench sidewall, but also in all first and second trenches still being completely filled. Alternatively or additionally, the first trenches and / or the second trenches can be partially or completely filled in separate steps.

[0045] In a subsequent step 150, the shielding regions can be activated by annealing. Annealing typically occurs at 1700 °C.

[0046] With the aid of the method according to the invention, the shielding regions below the first trenches are further apart from each other than the shielding regions are from the opposite trench walls or sidewalls of the second trenches. As a result, the short-circuit current is not limited by the collision of the space charge zones of two shielding regions, but rather by the space charge zone of each p-doped shielding region, which forces or presses the current against the opposite trench wall of a second trench. The low sensitivity to process variability is achieved by the fact that, in the event of a short circuit, the trench wall of the respective second trench forms an accumulation channel due to the positive gate voltage, which cannot be cleared by the space charge zone of the p-doped shielding region.

[0047] The first etching process, the second etching process, and / or the third etching process may be anisotropic etching processes. The fourth etching process may be isotropic.

[0048] In the case of a SiC semiconductor body, the first and / or third etching process can select between SiC that is etched and SiO2, SiN, and Si that are not etched. The second etching process and / or the fourth etching process can select between SiO2 that is etched and SiC, SiN, and Si that are not etched, in the case of a SiC semiconductor body.

[0049] In one embodiment, the first patterned mask has nitride regions located between the front side and the oxide regions. The nitride regions protect the front side or the surface of the fins, as this prevents oxidation of the fin top side in step 140. The nitride regions can be formed in a Fig. 1, the intermediate step between step 145 and step 150, not shown, can be removed.

[0050] In a further embodiment, spreading regions can be implanted beneath the second trenches using a second implantation process. The spreading regions can be n-doped and can have a higher doping than the n-doped drift layer. This can enhance the current spreading effect beneath the second trenches. The second implantation process can have a second implantation energy that has a value between 200 keV and 2500 keV.

[0051] Fig. Figure 2 shows a power FinFET 200 with alternating shielding regions without split control electrodes 209. The control electrodes 209 are one-piece. The power FinFET 200 comprises a semiconductor body 201 having a first connection region 202, a drift layer 203, a channel region 204, and a second connection region 205. The first connection region 202 functions as a drain connection, and the second connection region 205 as a source connection. The drift layer 203 is arranged on the first connection region 202, the channel region 204 is arranged on the drift layer 203, and the second connection region 205 is arranged on the channel region 204. The second connection region 205 functions as the front side of the semiconductor body 201.

[0052] Starting from the front side of the semiconductor body 201, first trenches 206 and second trenches 207 extend into the drift layer 203, with the second trenches 207 having a smaller width than the first trenches 206. The first trenches 206 and the second trenches 207 are arranged alternately with one another. Shielding regions 211 are arranged beneath the first trenches 206, which are preferably p-doped and directly adjoin a trench bottom of the first trenches 206. The dopant concentration of the shielding regions 211 is at least 1E18 / cm 3 The shielding regions 211 are connected to source regions 210, which are not arranged within the trenches, but for example by a contact at the end of a cell field, or, as in Fig.2, electrically conductively connected by a deep connection region implanted, for example, at periodic intervals along the fin. The control electrode 209 can function as a gate connection. Dividing a control electrode 209 into two parts can be completely or at least partially omitted. One, several, or all control electrodes 209 can thus be one-piece. Control electrodes 209 are electrically insulated from the shielding region 211 by means of an oxide layer 208. Between the first trenches 206 and the second trenches 207, fins 212 are arranged, which can, for example, have a width of less than 500 nm, preferably a width in the range between 400 and 50 nm, more preferably a width in the range between 200 and 50 nm.

[0053] The semiconductor body 201 may comprise SiC and / or GaN.

[0054] In one embodiment, spreading regions 213 are arranged below the second trenches 207. The spreading regions 213 can be n-doped. They can have a higher doping than the drift layer 203, which can also be n-doped. Shielding regions 211 and spreading regions 213 can be arranged alternately, in particular alternating, or in a periodic pattern. A distance between directly adjacent shielding regions 211 can be in the range between 800 and 1000 nm, preferably in the range between 850 and 950 nm. More preferably, a distance between directly adjacent shielding regions can be 900 nm.

[0055] The Power FinFET is used, for example, in DC / DC converters and inverters in the electric drive train of electric or hybrid vehicles, as well as in vehicle chargers. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 102 24 201 B4

[0003]

Claims

[1] Method (100) for producing power FinFETs (200) with one-piece control electrodes, wherein the power FinFET comprises a semiconductor body (201) having a second connection region (205) and a drift layer (203), wherein the second connection region (205) forms a front side of the semiconductor body (201), comprising the steps: • producing (105) a first structured mask on the front side of the semiconductor body (201) by means of a lithography step, wherein the first structured mask has oxide regions and first open regions, wherein the first open regions expose the front side of the semiconductor body (201), • producing (110) first trenches (206) below the first open regions by means of a first etching process starting from the front side of the semiconductor body (201) into the drift layer (203), • Creating (115) shielding regions (211) beneath the first trenches by means of a first implantation process, • Applying (120) an isotropic oxide layer to the front side of the semiconductor body (201), • producing (125) a second structured mask by means of a second etching process, so that the isotropic oxide layer has second open regions, and the second open regions expose the front side of the semiconductor body (201), • Creating (130) second trenches (207) below the second open regions by means of a third etching process starting from the front side into the drift layer (203), wherein the second trenches (207) are arranged substantially parallel to the first trenches (206), and the first trenches (206) and the second trenches (207) alternate, wherein the second trenches (207) have a smaller width than the first trenches (206), • Oxidizing (135) the front side so that a further oxide layer is arranged on the front side, • widening (140) the first trenches (206) and the second trenches (207) with the aid of a fourth etching process, so that fins (212) are formed between the first trenches (206) and the second trenches (207), the fins (212) having a width of less than 500 nm, • Applying (145) a polysilicon layer to the front side of the semiconductor body so that the first trenches (206) and the second trenches (207) are completely filled, and • Activating (150) the shielding areas (211) by tempering. [2] The method (100) of claim 1, wherein the first patterned mask comprises nitride regions, the oxide regions being disposed on the nitride regions. [3] Method (100) according to one of claims 1 or 2, wherein spreading regions below the second trenches are created by means of a second implantation process, wherein a second implantation energy has a value between 200 keV and 2500 keV. [4] A method according to any one of the preceding claims, wherein the first etching process, the second etching process and the third etching process are anisotropic plasma etching processes. [5] A method according to any one of the preceding claims, wherein the first implantation process has a first implantation energy in the range of 30 keV to 2700 keV. [6] Power FinFET (200) with one-piece control electrodes and a semiconductor body (201) having a drift layer (203) and a second connection region (205), wherein the second connection region (205) is arranged above the drift layer (203) and first trenches (206) and second trenches (207) extend from the second connection region (205) into the drift layer (203), wherein first trenches (206) and second trenches (207) are arranged alternately with one another, wherein the second trenches (207) have a smaller width than the first trenches (206), wherein shielding regions (211) are arranged below the first trenches (206), wherein the shielding regions (211) directly adjoin the first trenches (206) and the shielding regions (211) are electrically conductively connected to source regions (210), wherein the electrically conductive connections are not arranged within the first trenches (206), wherein a respective one-piece control electrode (201) is arranged within the first trenches (206), wherein the respective one-piece control electrode (201) is electrically insulated from the shielding region (211) below the first trenches (206), and wherein fins (212) are arranged between the first trenches (206) and the second trenches (207), wherein the fins (212) have a maximum width of 500 nm. [7] Power FinFET (200) according to claim 6, wherein spreading regions (213) are arranged below the second trenches (207). [8] Power FinFET (200) according to one of claims 6 or 7, wherein the shielding regions are p-doped and have a dopant concentration of at least 1E18 / cm 3 have. [9] Power FinFET (200) according to one of claims 6 to 8, wherein the semiconductor body (201) comprises SiC. [10] Power FinFET (200) according to one of claims 6 to 8, wherein the semiconductor body (201) comprises GaN.

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