SYSTEM FOR ELIMINATIVE INDUCTIVITY IN X-TYPE MULTI-STAGE CONVERTERS

Abstract

A multiphase inverter for an electric drive system comprises multiple X-type multi-stage power converters positioned between a high-voltage DC power supply and an electric machine. Each of the multiple X-type multi-stage power converters is an integrated solid-state circuit (IC) comprising a positive DC power bus, a negative DC power bus, a neutral bus, and multiple semiconductor switches arranged in a stacked configuration. The multiple semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

Description

INTRODUCTION

[0001] The concepts described here generally refer to vehicles with electrified powertrains or propulsion systems equipped with direct current (DC) power supplies that deliver alternating current (AC) to multi-phase inverters to control the operation of one or more electric machines.

[0002] High-voltage, high-power multilevel inverters (MLIs) have gained attention due to the rapidly accelerating electrification of the transportation sector toward high-capacity mass transit systems, such as electric aircraft, trains, and ships. MLIs such as neutral-point clamped (NPC) and T-type inverters offer high-voltage, high-power capabilities but incorporate stacked DC link capacitors with a neutral-point connection for a zero-sequence voltage vector. This neutral-point connection to the stacked DC link capacitor can generate a zero-sequence current oscillating at three times the fundamental frequency, potentially leading to capacitor voltage imbalance and overvoltage stress on capacitors and switching devices.

[0003] A multiphase inverter circuit can create an inherent power loop in which a high current flows from a DC link capacitor to a high side of the multilevel inverter and then to a low side of the multilevel inverter and back. The power loop can generate a magnetic field that forms a parasitic inductance.

[0004] Because multiphase inverters operate at higher switching frequencies, even small parasitic inductances can cause problems such as, but not limited to, ringing and / or electromagnetic interference (EMI).

[0005] The current flow path determines the size of the power loop, which in turn determines the size of the generated magnetic field and thus the size of the parasitic inductance. The current flow path is determined by the circuit topology, and therefore the circuit topology can influence the size of the parasitic inductance. DESCRIPTION

[0006] In view of the above discussion, it is useful to develop a system and method for canceling mutual inductance for a multiphase inverter including a plurality of X-type multilevel power converters with a topology that reduces the parasitic inductance within the multiphase inverter and / or within each X-type multilevel power converter.

[0007] The concepts disclosed herein relate to a system for a multiphase inverter having a plurality of X-type multilevel power converters that achieve mutual inductance cancellation. Such a system may be used in vehicles with an electrified propulsion system, such as, but not limited to, a motor vehicle with an electrified powertrain or propulsion system, such as an electric vehicle (EV) or plug-in hybrid vehicle (PHEV), or other mobile platform capable of being powered by an electric propulsion system, to reduce parasitic inductance within the multiphase inverter.

[0008] Each multiphase inverter can contain multiple X-level power converters positioned between a high-voltage DC power supply and an electrical machine. The number of X-level multilevel power converters required depends on the application.

[0009] Any X-type multilevel power converter can be configured as a solid-state integrated circuit (IC) containing a variety of circuit components, such as, but not limited to, semiconductor switches and power rails, connected to form a network of connections through which current can flow. The shape of this network of interconnected circuits is called the circuit topology.

[0010] The concepts described herein provide a multiphase inverter advantageously arranged to minimize stray inductance and loop inductance through magnetic field cancellation. This involves the use of field cancellations through the arrangement of positive, neutral, and negative buses and a plurality of X-type multilevel power converters arranged in solid-state integrated circuits with stacked or tiered elements. The arrangement of the X-type multilevel power converters with stacked or tiered elements allows for either single-sided or double-sided cooling to reduce thermal impedance. This configuration can serve to reduce stray inductance, resulting in lower switching losses, less ringing, less electromagnetic interference (EMI), and lower thermal stress on the equipment.

[0011] One aspect of the disclosure may include a multiphase inverter for an electric powertrain, wherein the multiphase inverter converts high-voltage direct current electrical power into multiphase alternating current (AC) power that is transmitted to the electric powertrain. The multiphase inverter includes a plurality of X-type multilevel power converters disposed between a high-voltage direct current supply and an electric machine.Each of the plurality of X-type multi-level power converters is a solid-state IC comprising: a positive DC power bus; a negative DC power bus; a first neutral bus; a second neutral bus; a first AC bus; a second AC bus; a plurality of semiconductor switches including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink connected to the positive DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and a second heat sink connected to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0012] The first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus. The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus.The first semiconductor switch is connected to the second semiconductor switch at a first node, the second semiconductor switch is connected to the third semiconductor switch at a second node, the third semiconductor switch is connected to the fourth semiconductor switch at a third node, the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node. The first power diode is connected between the third node and the fourth node, and the second power diode is connected between the first node and the sixth node. The second node is connected to the first AC bus, and the fifth node is connected to the second AC bus.

[0013] Another aspect of the disclosure may include the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode being arranged in a plurality of layers, including: a first layer consisting of the first semiconductor switch arranged coplanar with the second semiconductor switch, arranged coplanar with the third semiconductor switch, arranged coplanar with the fourth semiconductor switch;a second layer consisting of the first power diode, the second power diode, the positive DC power bus arranged coplanar with the first AC bus, and the negative DC power bus arranged coplanar with the negative AC bus, and a third layer consisting of the second semiconductor switch arranged coplanar with the third semiconductor switch, the sixth semiconductor switch arranged coplanar with the seventh semiconductor switch; wherein the first layer is arranged parallel to the second layer, which is arranged parallel to the third layer;

[0014] Another aspect of the disclosure may include the first AC bus being arranged in parallel with the second AC bus.

[0015] Another aspect of the disclosure may be that the positive DC power bus is arranged in parallel with the negative DC power bus. Another aspect of the disclosure may include the positive DC power bus and the negative DC power bus being disposed at a first end of the X-type multi-level power converter, and the first AC bus and the second AC bus being disposed at a second end of the X-type multi-level power converter.

[0016] Another aspect of the disclosure may include the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch being connected to a first side of the first DBC substrate, and the first heat sink being connected to a second side of the first DBC substrate; and the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch being connected to a first side of the second DBC substrate, and the second heat sink being connected to a second side of the second DBC substrate.

[0017] Another aspect of the disclosure may include that the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, including: a first layer consisting of the first semiconductor switch arranged coplanar with the second semiconductor switch, arranged coplanar with the third semiconductor switch, arranged coplanar with the fourth semiconductor switch, the positive DC power bus, and the first AC bus;a second layer consisting of the first power diode and the second power diode, and a third layer consisting of the second semiconductor switch arranged coplanar with the third semiconductor switch, the sixth semiconductor switch arranged coplanar with the seventh semiconductor switch, the negative DC power bus, and the second AC bus; wherein the first layer is arranged parallel to the second layer, which is arranged parallel to the third layer;

[0018] Another aspect of the disclosure may include the first AC bus being arranged in parallel with the second AC bus.

[0019] Another aspect of the disclosure may be that the positive DC power bus is arranged in parallel with the negative DC power bus.

[0020] Another aspect of the disclosure may include the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch being adjacent to a first side of the first DBC substrate, and the first heat sink being adjacent to a second side of the first DBC substrate; and the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch being adjacent to a first side of the second DBC substrate, and the second heat sink being adjacent to a second side of the second DBC substrate.

[0021] Another aspect of the disclosure may include an X-type multi-level power converter for a multi-phase electrical inverter, the X-type multi-level power converter being a solid-state integrated circuit (IC) comprising: a positive DC power bus; a negative DC power bus; a first neutral bus; a second neutral bus; a first AC bus; a second AC bus; a plurality of semiconductor switches including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink connected to the positive DC power bus of the solid-state IC via a first direct-bonded copper (DBC) substrate;and a second heatsink connected to the negative DC power bus of the solid-state IC via a second DBC substrate.;

[0022] The first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus. The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus.The first semiconductor switch is connected to the second semiconductor switch at a first node, the second semiconductor switch is connected to the third semiconductor switch at a second node, the third semiconductor switch is connected to the fourth semiconductor switch at a third node, the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node. The first power diode is connected between the third node and the fourth node, and the second power diode is connected between the first node and the sixth node. The second node is connected to the first AC bus, and the fifth node is connected to the second AC bus.

[0023] Another aspect of the disclosure may include an electrified vehicle having an electric propulsion system including an electric motor configured to power the electric propulsion system and a multi-phase inverter having a plurality of X-type multi-level power converters disposed between a high-voltage DC power supply and an electric machine, wherein each of the plurality of X-type multi-level power converters is a solid-state integrated circuit.

[0024] Another aspect of the disclosure may include a method for inductance cancellation in a multi-phase inverter, including: arranging a plurality of semiconductor switches in an X-type multi-level stack; assembling the plurality of semiconductor switches arranged in the X-type multi-level stack into a solid-state integrated circuit (IC) having: a positive DC power bus; a negative DC power bus; and a neutral bus; and connecting the plurality of semiconductor switches across the positive DC power bus, the negative DC power bus, and the neutral bus.

[0025] The above features and advantages, as well as other features and associated advantages of this disclosure, will be readily apparent from the following detailed description of illustrative examples and modes for carrying out the present disclosure, when considered in conjunction with the accompanying figures and the appended claims. Furthermore, this disclosure expressly contemplates combinations and subcombinations of the elements and features presented above and below. BRIEF DESCRIPTION OF THE CHARACTERS

[0026] The accompanying figures, which are incorporated in this specification, illustrate embodiments of the disclosure which, together with the description, serve to explain the principles of the disclosure. Fig. 1 schematically shows an electric drive system with a multi-phase inverter arranged between a high-voltage DC power supply and an electric machine, according to the disclosure. Fig. 2 schematically shows an electric drive system with a multiphase inverter including a plurality of X-type multilevel power converters arranged between a high voltage DC power supply and an electric machine, in accordance with the disclosure. Fig. 3 schematically shows an electrical diagram of an X-type multi-level power converter according to one aspect of the disclosure. Fig. 4A schematically shows a front view of an X-type multi-level power converter according to one aspect of the disclosure. Fig. 4B schematically illustrates a cutaway end view of an X-type multi-level power converter according to one aspect of the disclosure. Fig. 4C schematically shows a rear view of an X-type multi-level power converter according to one aspect of the disclosure. Fig. 5A schematically shows a front view of an X-type multi-level power converter according to another aspect of the disclosure. Fig. 5B schematically illustrates a cutaway end view of an X-type multi-level power converter according to another aspect of the disclosure. Fig. 5C schematically shows a rear view of an X-type multi-level power converter according to another aspect of the disclosure.

[0027] The accompanying figures are not necessarily to scale and present a somewhat simplified representation of various preferred features of the present disclosure as disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes. Details besides such features will be determined in part by the particular intended application and environment of use. DETAILED DESCRIPTION

[0028] The components of each aspect of the disclosure, as described and illustrated herein, can be arranged and configured in a variety of different configurations. Therefore, the following detailed description is not intended to limit the scope of the claimed disclosure, but is merely representative of possible aspects of the disclosure. Furthermore, while numerous specific details are set forth in the following description in order to provide a thorough understanding of each aspect of the disclosure disclosed herein, some aspects of the disclosure may be practiced without some of these details. Furthermore, for clarity, certain technical material known in the related art has not been described in detail so as not to unnecessarily obscure the disclosure.Furthermore, the disclosure as shown and described herein may be practiced without any element not expressly disclosed herein.

[0029] The present disclosure may be embodied in many different forms. Representative examples of the disclosure are illustrated in the drawings and described in detail herein as non-limiting examples of the disclosed principles. To this end, elements and limitations described herein but not expressly recited in the claims are not to be incorporated into the claims, either individually or collectively, by implication, inference, or otherwise.

[0030] For the purposes of this description, the use of the singular includes the plural and vice versa, unless expressly excluded; the terms "and" and "or" apply both subjunctive and disjunctive; and the words "including," "containing," "comprising," "having," and the like mean "including without limitation." Furthermore, words of approximation such as "approximately," "almost," "substantially," "generally," "about," etc., may be used herein to mean "at, near, or almost at," or "within 0-5% of," or "within acceptable manufacturing tolerances," or logical combinations thereof.

[0031] As used herein, the term "system" refers to mechanical and electrical hardware, software, firmware, electronic control components, processing logic and / or processors, individually or in combination, including without limitation: application specific integrated circuit (ASIC), an electronic circuit, a processor (common, dedicated or group) that executes one or more software or firmware programs, memory device(s) that electrically store software or firmware instructions, a combinational logic circuit and / or other components that provide the described functionality.

[0032] Terms such as "vertical," "horizontal," "left," "right," "top," "bottom," and similar expressions are non-limiting terms that merely describe the various elements as illustrated in the figures and are not intended to limit the scope of the disclosure.

[0033] The term “electric machine” as used herein refers to an electric motor / generator with a rotor and a stator that is capable of converting electrical energy into mechanical energy and / or converting mechanical energy into electrical energy by electromagnetic force.

[0034] With reference to the drawings, in which like reference numbers refer to like or similar components in the different figures, the Fig. 1 and Fig. 2 schematically illustrates an electric powertrain 100 consisting of a DC power source 101, a multi-phase inverter 104, a multi-phase electric rotary motor, generator, or motor-generator (electric machine) 10, and a torque actuator 120, the operation of which is monitored and controlled by a controller 30. In one aspect of the disclosure, the electric powertrain 100 is arranged to generate torque in the form of one or more drive wheels and transfer it to the torque actuator 120 to perform work. The controller 30 executes control routines to control and manage the operation of the multi-phase inverter 104. In one aspect of the disclosure, the electric powertrain 100 is arranged on an electrified vehicle, shown schematically at 20, and is capable of generating traction torque for vehicle propulsion.When disposed on the electrified vehicle 20, the electrified vehicle 20 may include, but is not limited to, a mobile platform in the form of a commercial vehicle, an industrial vehicle, an agricultural vehicle, a passenger vehicle, an aircraft, a watercraft, a train, an off-road vehicle, a personal mobility device, a robot, and the like to fulfill the purposes of this disclosure. Alternatively, the electric powertrain 100 may also be an element of a stationary system.

[0035] The controller 30 may be embodied as one or more digital computing devices and may include one or more processors 34 and a memory 32. A control routine 36 may be stored as an executable instruction set in the memory 32 and executed by one of the processors 34 of the controller 30. The controller 30 is in communication with the multi-phase inverter 104 to control its operation in response to the execution of the control routine 36 to operate the electric machine 10. The multi-phase inverter 104 exchanges or transfers electrical energy to the electric machine 10 via a plurality of first AC buses 121 and second AC buses 122.

[0036] The term "control unit" and related terms such as microcontroller, control module, module, controller, control unit, processor and similar terms refer to one or various combinations of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), electronic circuits, central processing units, e.g., microprocessors and associated memory components in the form of transient and / or non-transitory memory components and storage devices (read-only, programmable read-only, random access, hard disk devices, etc.).The non-transitory memory component is capable of storing machine-readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuits, input / output circuits and devices, signal conditioning and buffering circuits, and other components accessible by one or more processors to provide described functionality. Input / output circuits and devices include analog-to-digital inverters and related devices that monitor inputs from sensors, where these inputs are monitored at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms, and similar terms refer to sets of instructions executable by the controller, including calibrations and lookup tables.

[0037] The electric machine 10 includes a cylindrically shaped rotor assembly mounted on a rotor shaft and located within an annular stator, the rotor assembly being coaxial with a rotor opening formed in the stator. Other elements of the electric machine 10, such as end caps, shaft bearings, electrical terminals, etc., are included but not shown. The stator's electrical windings are arranged with a number of electrical phases and a number of electrical turns per phase. Depending on the specific arrangement, the number of electrical phases can range from 3 to 6, and the number of conductor layers can range from 4 to 12.

[0038] The multiphase inverter 104 includes a plurality of semiconductor switches (illustrated with reference to Fig. 3 et seq.), which are arranged and controllable to convert DC electrical power to AC electrical power and to convert AC electrical power to DC electrical power using a pulse-width modulation signal 108 or other control technique. The multi-phase inverter 104 is arranged and controllable to convert DC energy from the high-voltage DC power source 101 into AC energy to actuate the electric machine 10 by electromagnetic force. The electric machine 10 is controllable to rotate and generate mechanical torque, which is transmitted to the torque actuator 120 via a rotatable member 12 and a gear train 114 when operated in a torque-generating mode.The electric machine 10 is controllable to generate an alternating electrical current from the mechanical torque provided by the torque actuator 120 by electromagnetic force, which is converted by the multi-phase inverter 104 into direct electrical current stored in the high-voltage direct current source 101 when operating in a power generation mode. The torque actuator 120, in one aspect of the disclosure, includes a vehicle wheel that transmits torque to a ground surface to effect forward motion as part of a traction drive system. The high-voltage direct current source 101 may be in the form of a rechargeable electrochemical battery device, a fuel cell, an ultracapacitor, and / or other electrical energy storage / generation technology.

[0039] The high-voltage DC power source 101 may be a rechargeable electrochemical battery device, a fuel cell, an ultracapacitor, and / or other electrical energy storage / generation technology. The high-voltage DC power source 101 is connected to the multi-phase inverter 104 via a high-voltage DC power bus having a positive terminal 102 and a negative terminal 103, and the multi-phase inverter 104 is connected to the electric machine 10 via a plurality of first AC buses 121 and second AC buses 122 for transmitting the pulse-width modulation signal 108.

[0040] As in Fig. 2, the multi-phase inverter 104 of the electric powertrain 100 is comprised of a plurality of X-type multi-level power converters 150 disposed between the high-voltage DC power source 101 and the electric machine 10, with a DC link capacitor 105 disposed between the high-voltage DC power source 101 and the multi-phase inverter 104 of the electric powertrain 100, and with respective first AC buses 121 and second AC buses 122. As illustrated, and in one non-limiting aspect of the disclosure, the multi-phase inverter 104 of the electric powertrain 100 is constructed with a number of three X-type multi-level power converters 150.

[0041] Fig. 3 schematically illustrates one of the X-type multi-level power converters 150 arranged as a solid-state integrated circuit (IC) with a plurality of semiconductor switches arranged in a stacked or stepped arrangement. In one aspect of the disclosure and as illustrated, the plurality of semiconductor switches includes a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, a sixth semiconductor switch S6 156, a seventh semiconductor switch S7 157, and an eighth semiconductor switch S8 158. In one aspect of the disclosure, at least a portion of the semiconductor switches is a field-effect transistor (FET). In one aspect of the disclosure, the FETs are gallium nitride (GaN) transistors. In one aspect of the disclosure, at least a portion of the semiconductor switches are insulated-gate bipolar transistors (IGBTs).

[0042] Other components of the X-type multi-level power converter 150 include the positive DC power bus 110, the neutral bus 111, and the negative DC power bus 112. The positive DC power bus 110 is connected to the positive intermediate link 102 of the high-voltage DC power bus, and the negative DC power bus 112 is connected to the negative intermediate link 103 of the high-voltage DC power bus.

[0043] The first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, and the fourth semiconductor switch S4 154 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112. This includes the first semiconductor switch S1 151 being connected to the second semiconductor switch S2 152 at the first node 161; the second semiconductor switch S2 152 being connected to the third semiconductor switch S3 153 at the second node 162; and the third semiconductor switch S3 153 being connected to the fourth semiconductor switch S4 154 at the third node 163.

[0044] The fifth semiconductor switch S5 155, the sixth semiconductor switch S6 156, the seventh semiconductor switch S7 157, and the eighth semiconductor switch S8 158 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112. This includes the fifth semiconductor switch S5 155 being connected to the sixth semiconductor switch S6 156 at the fourth node 164; the sixth semiconductor switch S6 156 being connected to the seventh semiconductor switch S7 157 at the fifth node 165; and the seventh semiconductor switch S7 being connected to the eighth semiconductor switch S8 158 at the sixth node 166.

[0045] A first power diode 171 is arranged between the fourth node 164 and the third node 163, wherein the anode of the first power diode 171 is connected to the fourth node 164 and the cathode of the first power diode 171 is connected to the third node 163.

[0046] A second power diode 172 is arranged between the first node 161 and the sixth node 166, wherein the anode of the second power diode 172 is connected to the sixth node 166 and the cathode of the second power diode 172 is connected to the first node 161.

[0047] The first node 161 is connected to the first AC bus 121 to transmit power to the electric machine 10 (as shown in Fig. 2).

[0048] The second node 162 is connected to the second AC bus 122 to transmit power to the electric machine 10 (as shown in Fig. 2). A positive DC power bus 110, a neutral power bus 111 and a negative DC power bus 112 are shown schematically.

[0049] By configuring the topology in each of the X-type multi-level converters 150 so that both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111, mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop currents in each of the X-type multi-level converters 150.

[0050] According to one aspect of the disclosure, illustrated in (I), the buses are configured from top 33 to bottom 34 such that the positive DC power bus 110 is parallel to the neutral bus 111, which in turn is parallel to the negative DC power bus 112.

[0051] According to another aspect of the disclosure, as shown in (II), the buses are configured from top 33 to bottom 34 such that the positive DC power bus 110 is in parallel with the negative DC power bus 112, which is then in parallel with the neutral bus 111.

[0052] According to another aspect of the disclosure, as shown in (III), the buses are configured from top 33 to bottom 34 such that the neutral bus 111 is in parallel with the positive DC power bus 110, which is then in parallel with the negative DC power bus 112.

[0053] According to another aspect of the disclosure, as shown in (IV), the positive DC power bus 110 is coplanar with the negative DC power bus 112, while both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111.

[0054] Although several topologies have been discussed above, these are merely exemplary and non-limiting aspects of the disclosure. Accordingly, it should be understood that within each of the X-type multi-level converters 150, mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance for the commutation loop currents within each of the X-type multi-level converters 150, i.e., by configuring the topology of the X-type multi-level inverter 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are in parallel with the neutral bus 111.

[0055] In the Fig. 4A, Fig. 4B and Fig. 4C illustrates a topology of one of the X-type multilevel power converters 150, arranged as a multilevel inverter (MLI), according to one aspect of the disclosure. In one aspect of the disclosure and as described herein, each of the X-type multilevel power converters 150 employs a no-neutral-point (NPL) MLI topology. Topology refers to the physical arrangement of the constituent elements, including the network bus interconnections, dielectrics, semiconductor switches, and other elements.

[0056] The X-type multi-level power converter 150 is configured as a solid-state integrated circuit (IC) with a plurality of semiconductor switches arranged in a stacked or stepped configuration. According to one aspect of the disclosure, the plurality of semiconductor switches includes a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, a sixth semiconductor switch S6 156, a seventh semiconductor switch S7 157, an eighth semiconductor switch S8 158, a first power diode 171, and a second power diode 172.

[0057] According to one aspect of the present disclosure, each semiconductor switch S1-S8 151-158 comprises three dies D arranged in parallel to one another. S. However, it should be noted that each semiconductor switch S1-S8 151-158 may contain a different number of parallel-arranged chips than the three shown, as required by the particular application.

[0058] According to one aspect of the disclosure, at least some of the semiconductor switches are field-effect transistors (FETs). According to another aspect of the disclosure, the FETs are gallium nitride (GaN) transistors. According to another aspect of the disclosure, at least some of the semiconductor switches are insulated-gate bipolar transistors (IGBTs).

[0059] According to one aspect of the present disclosure, each power diode 171, 172 comprises two chips D arranged in parallel to each other D . However, it should be noted that each power diode 171, 172 may contain a different number of parallel-arranged chips than the two shown, as required by the particular application.

[0060] Other elements of the X-type multi-level power converter 150 include the positive DC power bus 110, the neutral bus 111, the negative DC power bus 112, the first AC bus 121, and the second AC bus 122. The positive DC power bus 110 and the negative DC power bus 112 are disposed at a first end 131 of the X-type multi-level power converter 150. The first AC bus 121 and the second AC bus 122 are disposed at a second end 132 of the X-type multi-level power converter 150, which is opposite the first end 131.

[0061] The first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, the fourth semiconductor switch S4 154, the fifth semiconductor switch S5 155, the sixth semiconductor switch S6 156, the seventh semiconductor switch S7 157, the eighth semiconductor switch S8 158, the first power diode 171, and the second power diode 172 are arranged in a stacked or multi-layer configuration including a first layer 135, a second layer 136, and a third layer 137.

[0062] The first layer 135 includes the first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, the fourth semiconductor switch S4 154, the first heat sink 141, and the first DBC plate 143.

[0063] The second layer 136 includes the first power diode 171 and the second power diode 172, conductive spacers 146, the positive DC power bus 110, the neutral bus 111, the negative DC power bus, the first AC bus 121, and the second AC bus 122.

[0064] The third level 137 includes the fifth semiconductor switch S5 155, the sixth semiconductor switch S6 156, the seventh semiconductor switch S7 157, the eighth semiconductor switch S8 158, the second DBC plate 144, and the second heat sink 142.

[0065] Other elements of the X-type multi-level power converter 150 include the positive DC power bus 110, the neutral bus 111, the negative DC power bus, the first AC bus 121, and the second AC bus 122. The positive DC power bus 110 and the negative DC power bus 112 are disposed at a first end 131 of the X-type multi-level power converter 150. The first AC bus 121 and the second AC bus 122 are disposed at a second end 132 of the X-type multi-level power converter 150, which is opposite the first end 131.

[0066] In the Fig. 5A, Fig. 5B and Fig. 5C illustrates a topology of one of the X-type multilevel power converters 250 according to another aspect of the disclosure, arranged as a multilevel inverter (MLI). In another aspect of the disclosure and as described herein, each of the X-type multilevel power converters 250 employs a neutral point-less (NPL) MLI topology.

[0067] The X-type multi-level power converter 250 is arranged as a solid-state integrated circuit (IC) with a plurality of semiconductor switches arranged in a stacked or stepped arrangement. According to one aspect of the disclosure, the plurality of semiconductor switches includes a first semiconductor switch S1 251, a second semiconductor switch S2 252, a third semiconductor switch S3 253, a fourth semiconductor switch S4 254, a fifth semiconductor switch S5 255, a sixth semiconductor switch S6 256, a seventh semiconductor switch S7 257, an eighth semiconductor switch S8 258, a first power diode 271, and a second power diode 272. According to one aspect of the disclosure, at least a portion of the semiconductor switches is a field-effect transistor (FET). According to another aspect of the disclosure, the FETs are gallium nitride (GaN) transistors.According to another aspect of the disclosure, at least a portion of the semiconductor switches is an insulated gate bipolar transistor (IGBT).

[0068] Other elements of the X-type multi-level power converter 250 include the positive DC power bus 110, the neutral bus 111, the negative DC power bus, the first AC bus 121, and the second AC bus 122. The positive DC power bus 110 and the negative DC power bus 112 are disposed at a first end 231 of the X-type multi-level power converter 250. The first AC bus 121 and the second AC bus 122 are disposed at a second end 232 of the X-type multi-level power converter 250, which is opposite the first end 231.

[0069] The first semiconductor switch S1 251, the second semiconductor switch S2 252, the third semiconductor switch S3 253, the fourth semiconductor switch S4 254, the fifth semiconductor switch S5 255, the sixth semiconductor switch S6 256, the seventh semiconductor switch S7 257, the eighth semiconductor switch S8 258, the first power diode 271, and the second power diode 272 are arranged in a stacked or multi-layer configuration including a first layer 235, a second layer 236, and a third layer 237.

[0070] The first layer 235 includes the first semiconductor switch S1 251, the second semiconductor switch S2 252, the third semiconductor switch S3 253, the fourth semiconductor switch S4 254, the first heat sink 241, and the first DBC plate 243.

[0071] The second level 236 includes the first power diode 271 and the second power diode 272, the positive DC power bus 110, the neutral bus 111, the negative DC power bus 112, the first AC bus 121, and the second AC bus 122.

[0072] The third level 237 includes the fifth semiconductor switch S5 255, the sixth semiconductor switch S6 256, the seventh semiconductor switch S7 257, the eighth semiconductor switch S8 258, the second DBC plate 244, and the second heat sink 242.

[0073] The illustrated aspects of the X-type multi-level power converter disclosure provide for overlapping the positive DC power bus 110, the neutral bus 111, and the negative DC power bus 112 to reduce mutual inductance. This arrangement includes overlaying the first AC bus 121 with the second AC bus 122 to balance dV / dt and reduce or eliminate electromagnetic interference, and to achieve field cancellation across the P, O, and N currents to minimize parasitic loop and stray inductances.

[0074] The concepts and aspects of the disclosure described herein facilitate the optimal design of the positive DC power bus 110, the negative DC power bus 112, the neutral bus 111, and the DC link capacitor 105 to achieve mutual inductance cancellation.

[0075] The concepts and aspects of the disclosure described herein facilitate various heat transfer and cooling systems, including direct cooling, indirect cooling, immersion cooling, single-sided cooling, or double-sided cooling.

[0076] The concepts and aspects of the disclosure described herein enable reduction of voltage and current overshoot during device stress, including the chip / power module, power rails, and DC link capacitor.

[0077] The concepts and aspects of the disclosure described herein facilitate downsizing and increasing power density compared to current systems.

[0078] The concepts and aspects of the disclosure described herein facilitate the use of semiconductor switching tools with lower voltage ratings for lower conduction losses and a wider EV range compared to current systems.

[0079] The concepts and aspects of the disclosure described herein enable reduction of ringing and radiated / conductive electromagnetic interference with other subsystems.

[0080] The concepts and aspects of the disclosure described herein enable higher switching speed, which can reduce losses and thus increase the range and current carrying capacity of the vehicle.

[0081] These and other advantages of the present disclosure will be appreciated by those skilled in the art in view of the foregoing disclosure.

[0082] The detailed description and the drawings or figures are supportive and descriptive of the present teachings, but the scope of the present teachings is defined solely by the claims. While some of the best modes and other examples for carrying out the present teachings have been described in detail, various alternative designs and aspects of the disclosure exist for carrying out the present teachings, which are defined in the appended claims.

Claims

[1] A multi-phase inverter for an electric drive system, the multi-phase inverter comprising: a plurality of X-type multi-level power converters arranged to transfer electrical power between a high-voltage direct current (DC) supply and an electric machine, each of the plurality of X-type multi-level power converters being a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a first neutral bus; a second neutral bus; a first, DC, AC bus; a second AC bus; a plurality of semiconductor switches, including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink connected to the positive DC power bus of the solid-state IC via a first directly bonded copper substrate, DBC; and a second heat sink connected to the negative DC power bus of the solid-state IC via a second DBC substrate; and wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein the third semiconductor switch is connected to the fourth semiconductor switch at a third node; wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node; wherein the first power diode is connected between the third node and the fourth node; wherein the second power diode is connected between the first node and the sixth node; wherein the second node is connected to the first AC bus; and where the fifth node is connected to the second AC bus. [2] The multi-phase inverter according to claim 1, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, including: a first layer consisting of the first semiconductor switch arranged coplanar with the second semiconductor switch arranged coplanar with the third semiconductor switch arranged coplanar with the fourth semiconductor switch; a second plane consisting of the first power diode, the second power diode, the positive DC power bus arranged coplanar with the first AC bus, and the negative DC power bus arranged coplanar with the negative AC bus; and a third layer consisting of the second semiconductor switch arranged coplanar with the third semiconductor switch arranged coplanar with the sixth semiconductor switch arranged coplanar with the seventh semiconductor switch, wherein the first layer is arranged parallel to the second layer arranged parallel to the third layer. [3] The multi-phase inverter according to claim 2, wherein the first AC bus is arranged in parallel with the second AC bus. [4] A multi-phase inverter according to claim 3, wherein the positive DC power bus is arranged in parallel with the negative DC power bus. [5] The multi-phase inverter of claim 4, wherein the positive DC power bus and the negative DC power bus are disposed at a first end of the X-type multi-level power converter, and wherein the first AC bus and the second AC bus are disposed at a second end of the X-type multi-level power converter. [6] The multi-phase inverter according to claim 2, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected to a first side of the first DBC substrate, and the first heat sink is connected to a second side of the first DBC substrate; and wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected to a first side of the second DBC substrate, and the second heat sink is connected to a second side of the second DBC substrate. [7] The multi-phase inverter of claim 1, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, including: a first layer consisting of the first semiconductor switch arranged coplanar with the second semiconductor switch arranged coplanar with the third semiconductor switch, which is arranged coplanar with the fourth semiconductor switch, the positive DC power bus and the first AC bus; a second layer consisting of the first power diode and the second power diode; and a third level consisting of the second semiconductor switch arranged coplanar with the third semiconductor switch, arranged coplanar with the sixth semiconductor switch, arranged coplanar with the seventh semiconductor switch, the negative DC power bus, and the second AC bus; and wherein the first plane is arranged parallel to the second plane, which is arranged parallel to the third plane. [8] The multi-phase inverter of claim 7, wherein the first AC bus is arranged in parallel with the second AC bus. [9] The multi-phase inverter of claim 7, wherein the positive DC power bus is arranged in parallel with the negative DC power bus. [10] The multi-phase inverter according to claim 1, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected to a first side of the first DBC substrate, and the first heat sink is connected to a second side of the first DBC substrate; and wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected to a first side of the second DBC substrate, and the second heat sink is connected to a second side of the second DBC substrate.

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