Circuit arrangement with dead-time control to reduce power losses

DE102025101408A1Undetermined Publication Date: 2026-07-16ROBERT BOSCH GMBH
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Patent Information

Application Number
DE102025101408
Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-01-16
Publication Date
2026-07-16

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Abstract

Circuit arrangement (SA) and method with dead-time control for reducing power losses, wherein the circuit arrangement comprises a half-bridge circuit (HB) with a first switch (S1) and a second switch (S2) interconnected at a switching node (SK); and a detection unit (DE) designed to detect the duration of a reverse current flowing through one of the two switches (S1; S2) of the half-bridge circuit (HB) for dead-time control.
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Citation Information

Patent Citations

  • power semiconductor module

    DE10200332A1

  • SMOOTH SWITCHING FOR EFFICIENT NON-CMOS-BASED DC-DC CONVERTER

    DE102023118638A1