CIRCUIT FOR GRANTING SWITCHING ENERGY

Abstract

In one described example, a circuit includes a switching converter comprising a switch with a first current input, a second current input, and a control input, each of the first and second current inputs having an associated parasitic impedance. An energy harvesting circuit has a third input and a first output, the third input being coupled to each of the first and second current inputs. A voltage regulator has a fourth input and a second output, the fourth input being coupled to the first output or an input voltage terminal, and the second output being coupled to a voltage terminal of the circuit.

Description

TECHNICAL AREA

[0001] This description concerns a circuit for recovering switching energy. BACKGROUND

[0002] Power switches are used in a variety of applications to regulate the supply of electrical power. For example, a controller can supply a pulse-width modulated (PWM) input signal to a driver circuit designed to provide a drive signal to an output stage. The output stage may include one or more transistors that switch between on and off states to provide electrical power at an output to which a load can be connected. Switching the transistors can introduce switching losses due to parasitic elements, which can reduce the efficiency of the power converter. SUMMARY

[0003] A described example provides a circuit comprising a switching converter, a power harvesting circuit, and a voltage regulator. The switching converter includes a switch with a first current input, a second current input, and a control input, each of which has an associated parasitic impedance. The power harvesting circuit has a third input and a first output, the third input being coupled to each of the first and second current inputs. The voltage regulator has a fourth input and a second output, the fourth input being coupled to the first output or an input voltage terminal, and the second output being coupled to a voltage terminal of the circuit.

[0004] Another example circuit includes a switching converter, an energy harvesting circuit, and a voltage regulator. The switching converter includes a switch designed to turn on and off in response to a switch control signal. The circuit incorporates a parasitic impedance coupled to each terminal of the switch. The energy harvesting circuit is designed to clamp a voltage across the respective switch terminal and harvest energy in response to the switch turning on and / or off. This energy is stored in the parasitic impedance. The power supply circuit is designed to provide an output voltage in response to the harvested energy.

[0005] Another described example provides a system that includes a controller, a driver circuit, a switching converter, a rectifier, a capacitor, and a voltage regulator. The controller includes a control output. The driver circuit includes a signal input, a bias input, and a driver output. The switching converter includes a switch with a first current input, a second current input, and a control input, where a parasitic inductor is coupled to the first current input and the control input is coupled to the driver output. The rectifier includes a rectifier input and a rectifier output, where the rectifier input is coupled to the first current input. The capacitor is coupled between the rectifier output and a ground connection.The voltage regulator includes a regulator input and a regulator output, wherein the regulator input is coupled to the rectifier output or to an input voltage connection and the regulator output is coupled to the bias input. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic block diagram of an example circuit for energy recovery from a switch. Fig. Figure 2 is a circuit diagram of an exemplary power converter circuit that includes an energy harvesting circuit. Fig. Figure 3 is a circuit diagram of another exemplary power converter circuit that includes an energy harvesting circuit. Fig. 4 and Fig. 5 are plots that provide signals for a simulation of the circuit of Fig. Show 2. Fig. 6 are plots that compare estimated and simulated stresses plotted over a range of currents. Fig. Figure 7 shows the efficiency plots over a range of currents for the power converter of Fig. 2 with and without inclusion of the energy generation circuit. DETAILED DESCRIPTION

[0006] This description relates to a circuit arrangement for recovering energy from a parasitic impedance associated with a switch in response to the switching on and / or off of the switch.

[0007] As an example, a circuit includes a switching converter and an energy harvesting circuit. The switching converter includes one or more switches (e.g., transistors) designed to turn on and off in response to a switch control signal. The switching converter can be a buck, boost, buck-boost, or other converter topology. An inherent parasitic impedance (e.g., parasitic inductance and / or capacitance) can be coupled to a respective terminal of the switch, such as from an integrated circuit (IC) package containing the switch, a printed circuit board, and / or associated connections to that terminal. The energy harvesting circuit is designed to clamp a voltage across the respective switch terminal and harvest energy stored in the parasitic impedance in response to the switch turning on and / or off.In some examples, a power supply circuit (e.g., a voltage regulator) may be designed to provide an output voltage in response to the captured energy, which can be used to power other circuit arrangements that may be located within (e.g., part of) an integrated circuit (IC) that includes the switch and the energy harvesting circuit. In other examples, which may depend on the voltage across the parasitic impedance, the energy harvesting circuit (e.g., a diode and a capacitor) may be coupled to another circuit arrangement and designed to supply the output voltage directly to that other circuit arrangement.

[0008] Many existing approaches slow down switching transition rates and / or use active terminals to dissipate energy stored in parasitic elements to prevent excessive voltage fluctuations at the switch. Unlike such existing approaches, which tend to dissipate or otherwise waste energy, the circuits and systems described here are designed to recover energy stored in such parasitic elements. As described here, the stored energy can be supplied to other circuit arrangements. This can improve the overall power efficiency, particularly at higher switching frequencies.

[0009] Fig. Figure 1 is a schematic diagram of an exemplary circuit 100, which includes a switching converter shown as switch 102. Switch 102 includes a first current input 104, a second current input 106, and a control input 108. In one example, switch 102 is a field-effect transistor (FET), such as an n-channel or p-channel FET. In other examples, a different type of transistor can be used to implement switch 102, such as a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, or the like. In the example of Fig. In Figure 1, the first current input 104 has an associated parasitic impedance, shown as 110, where the parasitic impedance 110 is coupled between the first current input 104 and an input voltage terminal 112 of an input voltage supply 114. In other examples, one or more parasitic impedances may be associated with the second current input 106, the control input 108, and / or the first current input 104. The parasitic impedance 110 may be associated with any one or more of the respective inputs 104, 106, or 108 of the switch 102 and may include a parasitic inductance, a parasitic capacitance, or a combination of parasitic inductance and capacitance.

[0010] Switch 102 is designed to be turned on (e.g., to provide a short-circuit path) or turned off (e.g., to provide an open circuit path) in response to a switch control signal at control input 108 between current inputs 104 and 106. For example, a switch control circuit 116 has an output 118 coupled to the control input 108 of the switch. The switch control circuit 116 may include logic, one or more drivers, and / or other circuitry designed to control the turning on and off of switch 102 according to application requirements. In some examples, another circuitry 120 is coupled between the second current input 106 and a ground terminal 122. This other circuitry may vary depending on the application environment.For example, the other circuit arrangement 120 may include a load, one or more switches, a power supply circuit arrangement, or another circuit arrangement to which the switch can supply an electrical signal (e.g., current and / or voltage).

[0011] An energy harvesting circuit 124 has an input 126 that is coupled to the first current input 104 (or another terminal) of the switch 102 with the associated parasitic impedance 110. The energy harvesting circuit 124 also has an output 128 that is coupled to an input 130 of a power supply circuit 132. The energy harvesting circuit 124 and the power supply circuit 132 may also each have a terminal that is coupled to the ground terminal 122 of the circuit 100. The power supply circuit 132 has an output 134 that may be, or be coupled to, a voltage terminal (e.g., a voltage rail) 136 of the circuit 100. In some examples, such as in Fig. As shown in Figure 1, the switch control circuit 116 can have a voltage input 138 that is coupled to the output 134 of the power supply 132. Furthermore, or as an alternative example, the output 128 of the energy harvesting circuit 124 can be coupled to the voltage input 138, as shown by the dashed line 140, to supply a voltage directly to the switch control circuit 116.

[0012] As described here, the switch 102 is designed to turn on and off in response to the switch control signal at the control input 108, which can be provided by the switch control circuit 116. The energy harvesting circuit 124 is designed to clamp a voltage at the first current input 104 and, in response to the turning on and / or off of the switch, to harvest energy stored in the parasitic impedance 110. For example, the energy harvesting circuit 124 includes a rectifier diode designed to rectify the voltage at the first current input 104 and, in response to the turning on and / or off of the switch, to provide a DC current that indicates the energy stored in the parasitic impedance 110. The energy harvesting circuit 124 can include one or more storage elements (e.g.,The power supply circuit 132 includes one or more capacitors designed to store energy according to the direct current provided by rectification and to provide a corresponding voltage signal at output 128. The power supply circuit 132 is designed to provide an output voltage in response to the voltage at 128, which depends on the energy recovered. For example, the power supply circuit 132 is a voltage regulator designed to provide a regulated voltage VREG at output 134, which can supply power to the switch control circuit 116 or to another circuit arrangement 120 that is part of or coupled to the circuit 100.

[0013] The circuit 100 can be part of an IC on a semiconductor die or be implemented as such, which may be encapsulated in a potting compound to provide an encapsulated semiconductor device. In one example, the IC on the semiconductor die includes the switch 102 and at least part of the energy harvesting circuit 124 (e.g., up to and including the entire energy harvesting circuit). In some examples, an energy storage element of the energy harvesting circuit 124 includes a discrete capacitor that is implemented within the encapsulated semiconductor device but is coupled to the die containing the IC (e.g., by bond wires).

[0014] Fig. Figure 2 is a circuit diagram of an exemplary power converter circuit 200 (also referred to as a system or power converter) which includes an energy harvesting circuit 202. The power converter circuit 200 is an example that can be used to illustrate circuit 100. Fig. 1 to implement, where energy harvesting circuit 202 provides a further example of energy harvesting circuit 124. Accordingly, the description of Fig. 2 on specific aspects of the circuit 100 of Fig. 1.

[0015] The power converter circuit 200 includes a first and a second switch, shown as transistors (e.g., FETs) Q1 and Q2, connected in series between a voltage terminal 204 and a ground terminal 206. In the example of Fig. In section 2, transistors Q1 and Q2 define a switching converter. The voltage terminal 204 can be connected to an output of a voltage supply (e.g., the input supply 114 of a power supply). Fig. 1) be coupled to a device designed to provide an input voltage VIN (e.g., a DC voltage). The power supply may be located on the same semiconductor device (e.g., IC chip) as some or all of the components of the power converter circuit 200. Alternatively, the power supply may be implemented outside of a semiconductor device containing transistor Q1 via an electrical connection (e.g., a trace or wire).

[0016] Transistor Q1 has a first current input (e.g., a drain) 208, a second current input (e.g., a source) 210, and a control input (e.g., a gate) 212. The first current input 208 is coupled to the voltage terminal 204 via a parasitic impedance, which is represented as a parasitic inductance (e.g., a drain inductance of Q1). The second current input 210 is coupled to a switching terminal (e.g., a switching node of a half-bridge defined by Q1 and Q2) 214. The other transistor Q2 can be coupled between the switching terminal 214 and the ground terminal 206. In the example of Fig. In Figure 2, transistor Q2 has a first current input (e.g., a drain) 216, a second current input (e.g., a source) 218, and a control input (e.g., a gate) 220, where the first current input 216 is coupled to the switching terminal 214 and the second current input 218 is coupled to the ground terminal 206. For example, transistors Q1 and Q2 are power FETs, which can be n-channel FETs (NFETs) or p-channel FETs (PFETs). In the example of Fig. 2. Transistors Q1 and Q2 can define a power stage (e.g., a half-bridge circuit), where Q1 is a high-side FET and Q2 is a low-side FET. Transistors Q1 and Q2 can be implemented by other types of transistors in other examples, as described here.

[0017] The energy harvesting circuit 202 has an input 222 and an output 224, with the input 222 being coupled to the first current input 208. In one example, the energy harvesting circuit 202 includes a rectifier with a rectifier input coupled to the first current input 208 and a rectifier output coupled to the output of the energy harvesting circuit 202.

[0018] In the example of Fig. Figure 2 of the energy harvesting circuit 202 includes a diode D1 (e.g., a rectifier diode) and a capacitor C1. The diode D1 has an anode and a cathode, with the anode connected to the first current input (e.g., drain) 208 of the transistor Q1. The cathode of diode D1 is connected to the output 224 of the energy harvesting circuit 202. The capacitor C1 is connected between the output 224 and the ground terminal 206. The diode can be an ordinary semiconductor diode, or a transistor (e.g., a diode-switched transistor emulating a diode) designed to allow current flow in only one direction can be used.

[0019] The power converter circuit 200 also includes a voltage regulator, shown as a low-dropout (LDO) regulator 230. The LDO regulator 230 has a regulator input 232 and a regulator output 234. The regulator input 232 is coupled to the output 224 of the energy harvesting circuit 202, and the LDO regulator 230 can also be coupled to the ground terminal 206. The regulator output 234 can be coupled to a bias input 236 of a drive circuit 238. The LDO regulator 230 can be an on-chip LDO capable of operating based on the VIN_LDO voltage.

[0020] The control circuit 238 includes one or more gate drivers 240 and 242, which are designed to supply control signals to the control inputs 212 and 220 of the respective transistors Q1 and Q2 in response to control signals (e.g., logic signals) provided by a controller 244. The controller 244 and the gate drivers 240 and 242 can control a switch control circuit 246 (e.g., the switch control circuit 116 of Fig. 1) Define. The gate driver 240 has a signal input 248, a bias input 236, and a driver output 250. The signal input 248 is coupled to a signal output of the controller 244, and the driver output is coupled to the control input (e.g., gate) 212 of transistor Q1. Similarly, the gate driver 242 has a signal input 252, a bias input 253, and a driver output 254, where the signal input 252 is coupled to another signal output of the controller 244, and the driver output 254 is coupled to the control input (e.g., gate) 220 of transistor Q2. In some examples, the bias input 253 may be coupled to the regulator output 234 to receive the regulated voltage. In other examples, the bias input 253 can be coupled to another regulator circuit that is separate from the regulator 230 in order to receive a respective bias voltage.

[0021] In some examples, the switching terminal 214 can be coupled to an output terminal 256 of the power converter circuit 200 via an LC network comprising an inductor L_OUT and a capacitor C_OUT. The switching control circuit 246 can be configured to control the respective transistors Q1 and Q2 (e.g., to switch Q1 and Q2 on and off) to provide an output voltage VOUT at the output terminal 256.

[0022] As another example, the controller 244 includes one or more control loops designed to provide respective control signals to regulate the output voltage VOUT at the output terminal 256. The control signals can be signal pulses, such as pulse-width modulated (PWM) signals with a variable duty cycle based on one or more detected conditions (e.g., representing voltage and / or current) of the power converter. The controller 244 can supply respective control signals to the gate driver inputs 248 and 252. The gate drivers 240 and 242 can supply respective drive signals (e.g., gate drive signals) in response to the respective control signals to the control inputs 212 and 220 of transistors Q1 and Q2. Each of the transistors Q1 and Q2 can be switched on or off depending on the value of the control signal received at its control input 212, 220 (e.g. partially or completely).

[0023] As described here, the parasitic inductor L_PAR, connected in series with transistor Q1, is designed to store parasitic energy based on current flowing through transistor Q1. Accordingly, in response to the switching off of transistor Q1 while it is conducting current, the energy stored in the parasitic inductor L_PAR is recovered by the energy recovery circuit 202, thereby reducing otherwise large voltage fluctuations across the switched-off transistor Q1. The energy recovery circuit 202 can also recover excess energy from the parasitic inductor L_PAR in response to the switching on of transistor Q1.

[0024] For example, diode D1 is designed to rectify a voltage at the first current input 208 and provide a DC current in response to the switching on and / or off of transistor Q1. Capacitor C1 is designed to store energy and provide a capacitor voltage (shown at output 224 at VIN_LDO (e.g., a rectified rail voltage)) in response to the current provided by diode D1. LDO regulator 230 is designed to provide a regulated voltage VREG at regulator output 234 in response to the capacitor voltage VIN_LDO at regulator input 232. The regulated voltage VREG can be supplied to one or more components in circuit 200, such as to provide a bias voltage at the bias input 236 of gate driver 240. Additionally or alternatively, the regulated voltage VREG can be supplied to a bias input of the other gate driver 242.As another example, diode D1 is designed as a reverse-blocking structure (e.g., when VIN_LDO exceeds VIN), so that VREG can also be supplied externally by an IC containing the LDO regulator 230. For example, the regulator output 234 can be coupled to an output pin (e.g., a pin) of an IC chip to supply the regulated voltage outside the chip.

[0025] It can be shown that the voltage VIN_LDO is approximately equal to the following: VIN_LDO=VIN−Vd+12L_PAR⋅IPK2⋅fSWILDO, where: V d the voltage drop across the terminal diode is, I PK the peak inductance current during switching on or off of the HFET is, fsw the switching frequency is and I LDO the current consumed by the LDO (including a fixed bias current and a gate drive current).

[0026] As shown by the equation above, the capacitor voltage VIN_LDO across C1 exceeds the input supply voltage VIN during steady-state operation, allowing the LDO regulator 230 to operate at lower VIN voltages with reduced LDO dropout voltage issues. However, when the circuit 200 is switched on under light load conditions and / or before energy is stored in the parasitic inductance L_PAR, the capacitor voltage VIN_LDO may be approximately one diode drop (e.g., approximately 0.7 V) below VIN, which is sufficient to power the LDO regulator 230. As the load increases, more energy is stored in the parasitic inductance L_PAR, and the capacitor voltage VIN_LDO rises above VIN, thus reverse-biasing diode D1.Thus, the power converter circuit 200 can recover energy stored in parasitic elements instead of dissipating and / or wasting such energy, as is the case with many existing approaches. As a result, the overall efficiency of the power converter 200 can be improved compared to such existing approaches, especially at higher switching frequencies.

[0027] Another example is the voltage drop across the diode V d The peak inductance current I is approximately 0.7 V, although other voltage values ​​(e.g., lower voltage drop) can be implemented, for example by using a Schottky diode or a switch emulating diode D1. PKThe current can vary depending on the application and in some examples can be 60 A or even more. The switching frequency can also depend on the application and in some examples range from about 300 kHz to several MHz (e.g., 5 MHz or higher). The current I LDO similarly, it can vary depending on the application, for example, typically in the two-digit mA range (e.g., 10 mA to 100 mA).

[0028] In some examples, the power converter circuit 200 also includes a voltage terminal 260 with a terminal input 262, which is coupled to the output 224. The voltage terminal 260 is designed to clamp the capacitor voltage VIN_LDO above a voltage threshold, thereby protecting the LDO regulator from an increased capacitor voltage VIN_LDO that can be supplied at the regulator input 232.

[0029] As another example, the power converter circuit 200 can be implemented on one or more ICs. In a first example, one or both of the transistors Q1 and Q2 can be implemented on a semiconductor die that includes the diode D1. In the first example, the capacitor C1 can be implemented as one or more discrete components that may be located within the same encapsulated semiconductor device as the semiconductor die containing D1. In another embodiment of the first example, the capacitor C1 can be located outside the encapsulated semiconductor device that includes D1 and Q1 and / or Q2. In the first example, the control 244 and / or the drive circuit 238 can be implemented in one or more ICs of semiconductor devices that are separate from and coupled to the semiconductor device containing Q1 and / or Q2 and D1.In a second example, one or both of transistors Q1 and Q2, diode D1, and capacitor C1 are implemented on the same semiconductor die within an encapsulated semiconductor device. Implementing capacitor C1 on the same die as the diode and switches increases the power and efficiency of the energy harvesting circuit. In the second example, the control 244 and / or the drive circuit 238 can be implemented in one or more ICs of semiconductor devices that are separate from and coupled to the semiconductor device containing Q1, Q2, D1, and C1. In both the first and second examples, each of transistors Q1 and Q2 can be implemented in separate ICs in the same or different semiconductor devices, or transistors Q1 and Q2 can be implemented in the same IC.

[0030] Fig. Figure 3 represents another exemplary power converter circuit 300 (also referred to as a system) that includes an energy harvesting circuit 302. The power converter circuit 300 can be used to power the circuit 100 of Fig. 1 to implement, where energy harvesting circuit 302 provides a further example of energy harvesting circuit 124. Accordingly, the description of Fig. 3 on specific aspects of the circuit 100 of Fig. 1. The power converter circuit 300 can be a half-bridge (e.g., identical or similar to the converter circuit 200 from Fig. 2) or another converter topology.

[0031] The power converter circuit 300 includes a first and a second switch, shown as transistors (e.g., FETs) Q3 and Q4, connected in series between a voltage terminal 304 and a ground terminal 306. The voltage terminal 304 can be connected to an output of a voltage supply (e.g., the input supply 114 of Fig. 1) be coupled to a device designed to provide an input voltage VIN (e.g., a DC voltage). The power supply may be located on the same semiconductor device (e.g., IC chip) as some or all of the components of the power converter circuit 300. Alternatively, the power supply may be implemented outside of a semiconductor device containing transistor Q3 via an electrical connection (e.g., a trace or wire).

[0032] Transistor Q3 has a first current input (e.g., a drain) 308, a second current input (e.g., a source) 310, and a control input (e.g., a gate) 312. The first current input 308 is coupled to the voltage terminal 304 via a parasitic impedance (e.g., a drain inductance of Q3) L_PAR1. The second current input 310 is coupled to a switching terminal 314. The other transistor Q4 can be coupled between the switching terminal 314 and the ground terminal 306. In the example of Fig. In Figure 3, transistor Q4 has a first current input (e.g., a drain) 316, a second current input (e.g., a source) 318, and a control input (e.g., a gate) 320. The first current input 316 is coupled to the switching terminal 314, and the second current input 318 is coupled to the ground terminal 306 via a parasitic impedance (e.g., the source inductance of Q4) L_PAR2. Transistors Q3 and Q4 can be FETs or other types of transistors in other examples, as described here.

[0033] The energy harvesting circuit 302 has an input 322 and an output 324, where input 322 is coupled to the second current input (e.g., the source) 318 of Q4. The energy harvesting circuit 302 may include a rectifier. In the example of Fig. The energy harvesting circuit 302 includes a diode D2 (e.g., a rectifier diode) and a capacitor C2. Diode D2 has an anode and a cathode, with the anode connected to the second current input (e.g., source) 318 of transistor Q4. The cathode of diode D2 is connected to the output 324 of energy harvesting circuit 302. Capacitor C1 is connected between output 324 and ground 306. Diode D2 can be a standard semiconductor diode or a transistor (e.g., a diode-switched transistor).

[0034] A control circuit 338 includes one or more gate drivers 340 and 342, which are designed to supply control signals to the control inputs 312 and 320 of the respective transistors Q3 and Q4 in response to control signals (e.g., logic signals) provided by a controller 344. The controller 344 and the gate drivers 340 and 342 can control a switch control circuit 346 (e.g., the switch control circuit 116 of Fig. 1) Define. The gate driver 340 has a signal input 348, a bias input 350, and a driver output 350. The signal input 348 is coupled to a signal output of the controller 344, and the driver output is coupled to the control input (e.g., gate) 312 of transistor Q3. Similarly, the gate driver 342 has a signal input 352, a bias input 354, and a driver output. The signal input 352 is coupled to another signal output of the controller 344, and the driver output is coupled to the control input (e.g., gate) 320 of transistor Q4.

[0035] In the example of Fig. The output 324 of the energy harvesting circuit 302 is coupled to the bias input 354 of the gate driver 342. In this way, the energy harvesting circuit 302 can be configured to provide a voltage VREG1, corresponding to a voltage across capacitor C2, to directly power the gate driver 3421 in response to energy stored in L_PAR2. The voltage VREG1 can be a regulated voltage (e.g., an essentially fixed voltage). Alternatively, the voltage VREG1 can vary during operation of the power converter circuit 300 according to the available electrical energy from the parasitic impedance L_PAR2 for charging capacitor C2 and the amount of power used by the gate driver 342.

[0036] In some examples, the power converter circuit 300 may include a regulator circuit 356 with a voltage input 358 and voltage outputs 360 and 362. The voltage input 358 may be coupled to the voltage terminal 304 to receive VIN, or in other examples, the voltage input 358 may be coupled to a different voltage source. The voltage output 362 may be coupled to the bias input 354. In some examples, a diode D3 may be coupled between the voltage output 362 and the bias input 354 to prevent current flow from the energy harvesting circuit 302 into the regulator circuit 356. The regulator circuit 356 can be designed to supply a regulated voltage to the bias input 354 of the gate driver 342, such as during low load current conditions that result in less energy being introduced by the parasitic impedance L_PAR2.

[0037] The regulator circuit 356 can also be configured to supply a regulated voltage VREG2 to the bias input 350 of the gate driver 340. In the Fig. In the second example shown, the voltage output 360 of the regulator circuit 356 is coupled to the bias input 350 of the gate driver 340. In other examples, the bias input 350 of the gate driver 340 can be coupled to the output 324 of the energy harvesting circuit 302 (also coupled to the bias input 354), so that both gate drivers 340 and 342 can be powered by the energy harvesting circuit 302 and / or the regulator circuit.

[0038] The regulator circuit 356 can implement separate regulators (e.g., LDOs) designed to provide VRFG1 and VREG2 at their respective outputs 362 and 360. Alternatively, a common circuit arrangement can be designed to provide VRFG1 and VREG2 at their respective outputs 362 and 360. Regardless of how the regulator circuit 356 is implemented, the voltage VREG2 at the bias input 350 can be equal to or different from the voltage VRFG1 at the bias input 354.

[0039] The switching terminal 314 can be coupled to an output terminal 356 of the power converter circuit 300 via an LC network comprising an inductor L_OUT and a capacitor C_OUT. The switching control circuit 346 can thus be configured to control the respective transistors Q3 and Q4 (e.g., to switch Q3 and Q4 on and off) to provide an output voltage VOUT at the output terminal 356. The control circuit can be configured to supply respective control signals to the gate driver inputs 348 and 352, and the gate drivers 340 and 342 can, in response to the respective control signals, supply respective drive signals (e.g., gate driver signals) to the control inputs 312 and 320 of transistors Q3 and Q4, as described with reference to Fig. 2 described.

[0040] As described here, the parasitic inductance L_PAR2, connected in series with transistor Q4, is designed to store electrical energy based on a current flowing through transistor Q4 in response to Q4 being switched on and / or off. For example, diode D2 is designed to rectify a voltage at the first current input 322 and provide a DC current at the first output in response to transistor Q4 being switched on and / or off. The parasitic impedance L_PAR2 stores electrical energy in response to transistor Q3 being switched on and / or off under load conditions. Capacitor C2 is designed to store energy and provide a capacitor voltage at output 324 (e.g., a rectified voltage) in response to the current supplied by diode D2.The amount of energy stored in the parasitic impedance L_PAR2 and the current introduced by the parasitic impedance L_PAR2 can depend on the load conditions during the switching of Q4. While the energy harvested by the energy harvesting circuit can be effectively used to power internal circuitry within an IC or SOC device, in other examples the voltage VREG1 from output 324 can be supplied externally via a terminal by an IC that includes the energy harvesting circuit 302.

[0041] Fig. 4 and Fig. 5 are plots 400 and 500, the signal waveforms for a simulation of the power converter circuit 200 of Fig. 2 show. Accordingly, the description refers to Fig. 4 and Fig. 5 also on Fig. 2. Plot 400 represents the input voltage VIN shown at 402, which is received at the voltage terminal 204, and the capacitor voltage VIN_LDO shown at 404, which is provided at 224 by the energy harvesting circuit 202. Fig. Figure 5 also represents the input voltage VIN shown in Figure 502 and the capacitor voltage VIN_LDO shown in Figure 504; however, with increased magnification compared to Figure 504. Fig. 4. Thus, the capacitor voltage VIN_LDO 504 appears as a sawtooth waveform with each switching cycle of transistor Q1.

[0042] Fig. Figures 602 and 604 compare estimated and simulated versions of the capacitor voltage VIN_LDO plotted over a range of currents. In particular, Fig. Figure 6 shows that the estimated capacitor voltage 602 (e.g. determined here by Eq. 1) closely follows the simulated capacitor voltage 604.

[0043] Fig. Figures 702 and 704 represent the efficiency of the power converter circuit 200. Fig. 2. For simulations over a range of currents, the simulations were performed with continuous conduction of an inductance current, VIN = 12 V, fsw = 1 MHz and I. LDO = 35 mA (measured for a typical 35-40 A part). Plot 702 demonstrates the efficiency for circuit 200 including the energy-harvesting circuit 202, and plot 704 shows the efficiency for circuit 200 without the energy-harvesting circuit, but with one active terminal. Thus, as shown, the inclusion of the energy-harvesting circuit resulted in an improvement in efficiency in the range of 0.6% to 1% in the current range of 20 A to 35 A.

[0044] In this description, the numerical designations "first," "second," etc., do not necessarily correspond to the same designations in the claims herein. Furthermore, the term "couple" can encompass connections, communications, or signal paths that enable a functional relationship corresponding to this description. For example, if a device A generates a signal to control a device B to perform an operation, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B via an intermediary component C, provided that the intermediary component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0045] Furthermore, in this description, a device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer to perform that function at the time of manufacture, and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or additional alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the design and / or layout of hardware components and interconnections of the device, or a combination thereof. Additionally, a circuit or device described herein as containing certain components may instead be configured to be coupled with those components to form the described circuit arrangement or device.For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors) and / or one or more sources (such as voltage and / or current sources) may instead only include the semiconductor elements within a single physical device (e.g., a semiconductor wafer and / or an integrated circuit (IC) package) and may be configured to be coupled with at least some of the passive elements and / or sources to form the described structure either at the time of manufacture or after a period of manufacture, such as by an end user and / or a third party.

[0046] Within the scope of protection of the claims, modifications of the described embodiments as well as other embodiments are possible.

Claims

[1] Circuit comprising the following: a switching converter comprising a switch with a first current input, a second current input and a control input, wherein each of the first current input and the second current input has an associated parasitic impedance; an energy harvesting circuit with a third input and a first output, wherein the third input is coupled to the respective inputs of the first and second current inputs; and a voltage regulator with a fourth input and a second output, wherein the fourth input is coupled to the first output or an input voltage terminal and the second output is coupled to a voltage terminal of the circuit. [2] Circuit according to claim 1, wherein the switch comprises a field-effect transistor (FET), the parasitic impedance comprises a parasitic inductance at a drain of the FET and the third input is coupled to the drain of the FET. [3] Circuit according to claim 2, wherein the FET is a first FET with a source coupled to a switching terminal, the drain of the first FET is coupled to the input voltage terminal and the circuit further comprises: a second FET that is coupled between the switching terminal and a ground terminal. [4] Circuit according to claim 2, wherein the energy harvesting circuit comprises: a diode with an anode and a cathode, wherein the anode is coupled to the drain of the FET and the cathode is coupled to the first output; and a capacitor coupled between the first output and a ground connection. [5] Circuit according to claim 4, wherein the voltage regulator comprises a low-dropout voltage regulator. [6] Circuit according to claim 5, further comprising: a gate driver with a control output and a bias input, wherein the control output is coupled to a gate of the FET and the bias input is coupled to the second output of the voltage regulator. [7] Circuit according to claim 6, wherein: the diode is designed to rectify an AC voltage at the anode and to provide a rectified voltage at the first output in response to the switching on and / or off of the switch, The capacitor is designed to store energy in response to the rectified voltage, and The low-dropout voltage regulator is designed to provide a regulated voltage to the bias input of the gate driver. [8] Circuit according to claim 7, further comprising a semiconductor die comprising an integrated circuit comprising the FET and the diode. [9] Circuit according to claim 8, wherein the integrated circuit of the semiconductor die comprises the capacitor or the capacitor is located within an encapsulation of a potting compound comprising the semiconductor die. [10] Circuit according to claim 1, wherein the energy harvesting circuit comprises: a diode with an anode and a cathode, wherein the anode is coupled to the respective first and second current inputs and the cathode is coupled to the first output; and a capacitor coupled between the first output and a ground connection. [11] Circuit according to claim 1, wherein the energy harvesting circuit comprises: a rectifier designed to rectify a voltage at the respective first and second current inputs and to provide a rectified voltage at the first output in response to the switching on and / or off of the switch; and a capacitor designed to store energy and provide a capacitor voltage at the first output in response to the rectified voltage, the voltage regulator is designed to provide a regulated voltage at the second output in response to the capacitor voltage. [12] Circuit according to claim 11, further comprising: a control circuit designed to provide a control signal, wherein the switch is designed to turn on or off in response to the control signal; and a voltage clamp with a clamp input coupled to the first output, wherein the voltage clamp is designed to clamp the capacitor voltage above a voltage threshold. [13] Circuit comprising the following: a switching converter comprising a switch designed to turn on and off and provide a converter output voltage in response to a switch control signal, wherein the switch comprises a parasitic impedance at each switch terminal of the switch; and an energy harvesting circuit designed to harvest energy stored in the parasitic impedance at the respective switch terminal in response to the switching on and / or off of the switch. [14] Circuit according to claim 13, wherein the switch comprises a field-effect transistor (FET) and the parasitic impedance comprises a parasitic inductance at a drain of the FET. [15] Circuit according to claim 14, wherein the energy harvesting circuit comprises: a rectifier designed to rectify the voltage at the respective switch terminal and to provide a direct current in response to the switching on and off of the switch; and a capacitor designed to store the energy gained and to provide a capacitor voltage in response to the direct current, wherein the power supply circuit is designed to provide the output voltage in response to the capacitor voltage. [16] Circuit according to claim 15, further comprising a voltage clamp designed to clamp the capacitor voltage above a threshold. [17] Circuit according to claim 15, wherein: the rectifier includes a diode, the FET is a first FET whose drain is coupled to an input voltage terminal and whose source is coupled to a switching terminal, a power supply circuit comprising a voltage regulator designed to provide a regulated voltage in response to the capacitor voltage, and The circuit also includes the following: a second FET coupled between the switching terminal and a ground terminal; a gate driver designed to supply a drive signal to a gate of the first FET in response to a control signal and the regulated voltage; and a controller designed to provide the control signal. [18] Circuit according to claim 17, further comprising a semiconductor die comprising an integrated circuit, wherein the integrated circuit comprises the first FET, the second FET and the diode, and the integrated circuit of the semiconductor die further comprises the capacitor, or the capacitor is located within an encapsulated semiconductor device comprising the semiconductor die. [19] System comprising the following: a controller with a control output; a driver circuit with a signal input, a bias input and a driver output; a switching converter comprising a switch with a first current input, a second current input and a control input, wherein a parasitic inductance is located at one of the respective first current inputs or the second current inputs and the control input is coupled to the driver output; a rectifier with a rectifier input and a rectifier output, wherein the rectifier input is coupled to the respective first current input or the second current input; and a capacitor coupled between the rectifier output and a ground connection; and a voltage regulator with a regulator input and a regulator output, wherein the regulator input is coupled to the rectifier output or to an input voltage terminal and the regulator output is coupled to the bias input. [20] System according to claim 19, further comprising a voltage terminal parallel to the capacitor, wherein: the rectifier is designed to rectify a voltage at the rectifier output and to provide a DC signal in response to the switching on and off of the switch, The capacitor is designed to store energy and provide a capacitor voltage in response to the DC signal. the controller input is coupled to the rectifier output, The voltage regulator is designed to provide a regulated voltage at the regulator output in response to the capacitor voltage, and and the voltage clamp is designed to clamp the capacitor voltage above a threshold. [21] System according to claim 19, wherein: the regulator voltage input is coupled to the input voltage terminal, the rectifier is designed to rectify a voltage at the rectifier input and to provide a DC signal in response to the switching on and / or off of the switch, The capacitor is designed to store energy and, in response to the DC signal, provide a capacitor voltage at the rectifier output. the controller input is coupled to the voltage input supply, a diode is coupled between the regulator output and the bias input and The voltage regulator is designed to provide a regulated voltage at the regulator output, and a voltage is provided at the bias input based on the regulated voltage and the capacitor voltage.

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