A voltage difference current transfer transconductance amplifier system

Abstract

A voltage differential current feed transconductance amplifier system (VDCCTA), consisting of: a voltage differential current booster module (VDCC); an operational transconductance amplifier (OTA) module, combined with the VDCC module on a Z-connector; and a variety of connections, including: two input connections; five output connections; and two buffered connections, wherein the two input connections are configured to receive differential input voltages, one output connection is configured to provide current output, two output connections are configured to provide current images of the connection providing current output, and two further output connections are configured to provide transconductance outputs; the system is configured to be tunable by pre-flows; and the system is further configured to operate as an active inductor simulator when connected to a grounded capacitor.

Description

AREA OF INVENTION

[0001] The present disclosure relates to a system with a voltage-differentiated current transport transconductance amplifier (VDCCTA). More precisely, the present invention relates to a current-mode component (CM) for a voltage-differentiated current transport transconductance amplifier (VDCCTA) developed by combining a voltage-differentiated current transport transconductance amplifier (VDCC) and an operational transconductance amplifier (OTA). BACKGROUND OF THE INVENTION

[0002] Operational transconductance amplifiers (OTAs) have become fundamental components in analog circuit design, offering significant advantages in signal processing applications such as amplifiers, filters, and oscillators. The continued development of CMOS-based OTA designs has led to the creation of numerous active current-mode (CM) blocks that combine basic CM elements with OTA circuitry to extend functionality into the transconductance domain.

[0003] Several active current-mode elements have been developed, including the current-carrying transconductance amplifier (CCTA), the voltage-difference transconductance amplifier (VDTA), the differential voltage-current-carrying transconductance amplifier (DVCCTA), and many others. These elements aim to provide improved performance characteristics compared to their voltage-mode counterparts, such as extended dynamic range, excellent linearity, wide bandwidth, higher slew rate, and better low-voltage performance.

[0004] Active inductor simulators (AIS) have proven to be crucial components for overcoming the limitations of passive inductors, including high weight, lack of tunability, and monolithic integration challenges. While existing functional block designs offer both grounded and groundless active inductors, they suffer from several issues, including a lack of component matching, the use of groundless capacitors unsuitable for integrated circuit implementation, series capacitor connections to terminals limiting high-frequency operation, and complex circuits requiring multiple passive and active elements.

[0005] Among the various active components, voltage differential current boosters (VDCC) are considered simple and effective active elements for the design of analog circuits.

[0006] The preceding discussion clearly demonstrates the need for improved active elements that enable resistance-free inductor simulation with enhanced performance characteristics and broader application possibilities in signal processing circuits. Therefore, the present invention provides a voltage-differentiating current transport transconductance amplifier system (VDCCTA) as an active inductor simulator (AIS). Summary of the invention

[0007] The present disclosure relates to a VDCCTA (Voltage Differentiating Current Conveyor Transconductance Amplifier) ​​system that can be implemented as an active inductor simulator (AIS). The system combines a VDCC (Voltage Differentiating Current Conveyor) block with an OTA (Operational Transconductance Amplifier) ​​block. The system has eight terminals and is configured to function as an active inductor simulator in conjunction with a grounded capacitor, providing tunable transconductance parameters through bias currents without requiring any component matching.

[0008] The present disclosure relates to providing a VDCCTA (Voltage Differentiating Current Conveyor Transconductance Amplifier) ​​system. The system comprises: a VDCC (Voltage Differentiating Current Conveyor) module; an OTA (Operational Transconductance Amplifier) ​​module combined with the VDCC block at a Z-terminal; and several terminals, including two input terminals, five output terminals, and two buffered terminals. The two input terminals are configured to receive differential voltages, one output terminal for current output, two output terminals for providing current images of the current-output terminal, and two further output terminals for providing transconductance outputs. The system is tunable via bias currents and, when connected to a grounded capacitor, functions as an active inductor simulator.

[0009] One objective of the present disclosure is to provide a voltage-differentiating current-feeding transconductance amplifier system (VDCCTA) that can be implemented as an active inductor simulator (AIS).

[0010] Another objective of the present disclosure is to provide an active VDCCTA element that combines the functionality of VDCC and OTA blocks to develop a versatile component for analog circuit applications, especially for active inductor simulation without component matching requirements.

[0011] Another objective of the present disclosure is to develop a system capable of implementing multiple inductor configurations, including grounded positive, grounded negative, and floating positive active inductors, using a single VDCCTA block and a grounded capacitor, thereby simplifying the circuit design and reducing the number of components.

[0012] Another objective of the present disclosure is to provide a tunable active element system that can be extended for various electronic applications, including general-purpose voltage mode filters and chaotic circuit generators, while maintaining excellent performance characteristics over a wide frequency range.

[0013] To further clarify the advantages and features of the present disclosure, the invention is explained in more detail with reference to specific embodiments illustrated in the accompanying drawings. These drawings merely show typical embodiments of the invention and are therefore not to be understood as limiting its scope. The invention is described and explained more precisely and in greater detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE FIGURES

[0014] These and other features, aspects, and advantages of the present disclosure will be better understood if the following detailed description is read with reference to the accompanying drawings, in which identical symbols consistently represent identical parts. The following applies: Fig. Figure 1 shows a block diagram of a voltage-differentiating current feeder transconductance amplifier (VDCCTA) system according to an embodiment of the present disclosure. Fig. Figure 2 shows (a) the electrical symbol and (b) the internal CMOS structure of VDCCTA according to an embodiment of the present disclosure. Fig. Figure 3 illustrates a diagram showing the macro model of VDCCTA according to an embodiment of the present disclosure; Fig. Figure 4 illustrates diagrams showing the DC characteristics of an active CMOS-based VDCCTA element: (a) V X opposite V Z , (b) I WP opposite I WN , (c) I O+ opposite I O- and (d) I Z according to one embodiment of the present disclosure; Fig. Figure 5 illustrates diagrams showing the DC characteristics of an IC-based active VDCCTA element: (a) V Xopposite V Z , (b) I WP opposite I WN , (c) I O+ opposite I O- and (d) I WP and I X according to one embodiment of the present disclosure; Fig. 6A illustrates a diagram showing the variation of g m2 opposite I B2 for CMOS-based VDCCTA according to an embodiment of the present disclosure; Fig. Figure 6B shows a table with the basic properties of the proposed VDCCTA system according to an embodiment of the present disclosure. Fig. Figure 7 shows a diagram of a proposed lossless grounded positive / negative active inductor according to an embodiment of the present disclosure. Fig. Figure 8 shows a diagram of the proposed VDCCTA FPAI according to an embodiment of the present disclosure. Fig. Figure 9 shows a diagram of a fifth-order HP filter using GPAI according to an embodiment of the present disclosure. Fig. Figure 10 shows a diagram of a chaotic circuit based on an operational amplifier according to an embodiment of the present disclosure. Fig. Figure 11 shows a diagram of a fourth-order LP filter using FPAI according to an embodiment of the present disclosure. Fig. Figure 12 shows a diagram of a universal second-order filter using the proposed FPAI according to an embodiment of the present disclosure. Fig. Figure 13 shows a diagram of a general structure of a VDCCTA with a parasitic element according to an embodiment of the present disclosure.

[0015] Experts will also recognize that the elements in the drawings are presented for the sake of simplicity and are not necessarily to scale. For example, the flowcharts illustrate the process by highlighting the main steps to enhance understanding of the aspects of this disclosure. Furthermore, with regard to the design of the device, one or more components of the device may be represented in the drawings by conventional symbols, and the drawings may show only the specific details relevant to understanding the embodiments of this disclosure, so as not to clutter the drawings with details that are readily apparent to those skilled in the art after reading this description. DETAILED DESCRIPTION:

[0016] For a better understanding of the inventive principles, reference is made below to the embodiment shown in the drawings, which is described in specific language. However, this does not limit the scope of the invention. Changes and further modifications of the illustrated system, as well as further applications of the inventive principles, are possible, as would normally occur to a person skilled in the art in this field.

[0017] It is clear to the person skilled in the art that the preceding general description and the following detailed description are exemplary and explanatory of the invention and are not intended as a limitation of it.

[0018] References in this specification to “an aspect”, “another aspect”, or similar expressions mean that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, occurrences of the expressions “in one embodiment”, “in another embodiment”, and similar expressions in this specification may all refer to the same embodiment, but need not.

[0019] The terms "includes," "include," or other variations thereof are intended to cover non-exclusive inclusion, such that a process or method that includes a list of steps may not only contain those steps but may also include other steps not expressly listed or inherent in such process or method. Likewise, the statement "includes..." in the case of one or more devices, subsystems, elements, structures, or components does not, without further limitations, preclude the existence of other devices, subsystems, elements, structures, components, or additional devices, subsystems, elements, structures, or components.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by a person skilled in the art in the field of the invention. The systems, methods, and examples provided herein serve only for illustration and are not to be construed as limitations.

[0021] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0022] Fig. Figure 1 illustrates a block diagram of a voltage-differentiating current-carrying transconductance amplifier system (VDCCTA) (100) according to an embodiment of the present disclosure.

[0023] Referring to Fig. 1 The system (100) comprises: a VDCC (Voltage Differentiating Current Conveyor) module (102); an OTA (Operational Transconductance Amplifier) ​​module (104) combined with the VDCC module (102) at a Z-terminal; and several terminals (106), including: two input terminals (106a); five output terminals (106b); and two buffered terminals (106c), wherein the two input terminals are configured to receive differential input voltages, one output terminal is configured to provide a current output, two output terminals are configured to provide current images of the terminal providing a current output, and two further output terminals are configured to provide transconductance outputs; wherein the system (100) is configured to be tunable via precurrents;and wherein the system (100) is further configured to function as an active inductor simulator when connected to an earthed capacitor.;

[0024] In one embodiment, the transconductance parameters are configured to be controlled by the bias current and the electrical MOSFET parameters, including electron mobility, gate oxide capacitance, and transistor width and length parameters.

[0025] In one embodiment, the system further comprises an internal CMOS architecture (108) configured to implement the functions of differential voltage current booster and operational transconductance amplifier.

[0026] In one embodiment, the system is configured to implement: a grounded positive active inductor configuration (GPAI); a grounded negative active inductor configuration (GNAI); and a floating positive active inductor configuration (FPAI) using a single VDCCTA block and a grounded capacitor with no component matching requirements, wherein a higher-order high-pass filter is designed using the GPAI, the GPAI also being suitable for chaotic circuit application, and the FPAI being used for a higher-order low-pass filter.

[0027] In one embodiment, the system is also configured to implement a universal multi-input, single-output voltage-mode filter configuration, which is implemented by adding two external passive elements to form a positive floating inductor configuration.

[0028] In one embodiment, the system is also configured to implement a chaotic circuit generator configuration, which is implemented using the VDCCTA block, wherein the system is configured to generate chaotic waveforms using the transconductance properties of the VDCCTA.

[0029] The present invention describes a voltage-differentiating current transport transconductance amplifier system (VDCCTA), which is an active current-mode device formed by combining a voltage-differentiating current transporter (VDCC) with an operational transconductance amplifier (OTA) at the Z terminal. The VDCCTA system comprises eight terminals, including two input terminals P and N, five output terminals X, WP, WN, O+, and O-, and two buffered terminals X* and Z. The system is specifically configured to function as an active inductor simulator when connected to a grounded capacitor, thus eliminating the component modifications required in conventional designs. The transconductance parameters of the system are adjustable via quiescent currents and are controlled by electrical MOSFET parameters.The system can implement three different active inductor configurations: grounded positive active inductance, grounded negative active inductance, and floating positive active inductance using a single VDCCTA block. The invention extends beyond inductance simulation, enabling the implementation of universal voltage-mode filters with multiple inputs and one output by adding two external passive elements to the floating positive inductance configuration. Furthermore, the system supports MOS switching techniques for toggling between positive and negative inductance operation and can be configured as a chaotic circuit generator. Operating effectively in a frequency range of 10 kHz to 5 MHz, the system offers advantages such as extended dynamic range, excellent linearity, wide bandwidth, and higher performance compared to voltage-driven counterparts.This makes it suitable for various signal processing applications.

[0030] Fig. Figure 2 illustrates (a) the electrical symbol and (b) the internal CMOS structure of VDCCTA according to an embodiment of the present disclosure.

[0031] Fig. Figure 3 illustrates a diagram showing the macro model of VDCCTA according to an embodiment of the present disclosure.

[0032] In the proposed configuration, two variants of a VDCC (Voltage Differencing Current Conveyor) and an OTA (Operational Transconductance Amplifier) ​​are integrated to create a VDCCTA (Voltage Differencing Current Conveyor Transconductance Amplifier). This integration effectively extends the operating range of the VDCC towards its transconductance mode. The corresponding electrical symbol and the CMOS-based internal structure of the VDCCTA are described in Fig. shown, with the system comprising eight connections.

[0033] Fig. Figure 2(a) shows that in the VDCCTA architecture, terminals P and N function as input terminals, while terminals X, WP, WN, O + and O - These serve as output terminals. The additional terminals Z and X' function as buffered terminals. Furthermore, the transconductance gain of the component at the current output terminals is 10. + and 10 - accessible. A current pattern generated at terminal X is replicated accordingly at terminals WP and WN.

[0034] The macromodel implementation of the VDCCTA, created by using an OTA in conjunction with a second-generation active Current Conveyor (CCII) element, is in Fig. Figure 3 shows the connection characteristics of the active VDCCTA element. The connection characteristics are mathematically represented in matrix form in equation (1) below. [INIPIZVXIWPIWNIO=˙]=[00000000gm−gm0000100001000−100±gm0][VPVNVZIX].

[0035] The transconductance parameter (gm) expressed in equation (1) is defined as a combined functional relationship of the electrical parameters of standard MOSFETs, namely carrier mobility (µ), oxide capacitance (Cox), quiescent current (IB), channel width (W), and channel length (L). The analytical expressions that determine this relationship are given in equations (2) and (3) below. gm1=μCαxIB1WM1,2LM1,2, gm2=μCαxIB2WM25,26LM25,26.

[0036] Fig. Figure 4 illustrates diagrams showing the DC characteristics of a CMOS-based active VDCCTA element: (a) V X opposite V Z , (b) I WP opposite I WN , (c) I O+ opposite I O- and (d) I Z according to one embodiment of the present disclosure.

[0037] Fig. Figure 5 illustrates diagrams showing the DC characteristics of an IC-based active VDCCTA element: (a) V X opposite V Z , (b) I WP opposite I WN , (c) I O+ opposite I O- and (d) I WP and I X according to one embodiment of the present disclosure.

[0038] Fig. 6A illustrates a diagram showing the variation of g m2 opposite I B2 for CMOS-based VDCCTA according to an embodiment of the present disclosure.

[0039] Fig. Figure 6B shows a table with the basic properties of the proposed VDCCTA system according to an embodiment of the present disclosure.

[0040] The novelty of the proposed active element is evaluated by analyzing its current-voltage characteristics and demonstrating its applicability in a range of benchmark signal processing circuits, such as a zero-resistance active inductor, filter design, and a chaotic signal generation circuit. Initial verification of the VDCCTA is performed by validating the port characteristics. This involves using both a CMOS-based implementation and an integrated circuit (IC) with AD844 and LM13700 components in a PSPICE simulation environment. The experimentally determined DC characteristics of the CMOS structure and the commercially available IC-based VDCCTA are presented in Fig. depicted.

[0041] Fig. Figure 4 shows that integrating the OTA at the Z-terminal of the VDCC does not cause any changes to the observed DC characteristics. How Fig. As shown, the simulated DC characteristics are validated by the macromodel implementation of the VDCCTA using the active elements OTA (LM13700) and MO-CCII (AD844). The relationship between the transconductance parameter (gm) and the applied quiescent current (IB2), expressed in amperes (A), is shown in Fig. 6A is shown.

[0042] A summary of the performance characteristics of the proposed VDCCTA with respect to basic design parameters such as supply voltage, control voltage, power dissipation, cutoff frequency, voltage gain, and current gain is provided in Fig. 6B presented in tabular form, with a comparative representation for both CMOS and IC-based implementations of the VDCCTA.

[0043] Fig. Figure 7 shows a diagram of a proposed lossless grounded positive / negative active inductor according to an embodiment of the present disclosure.

[0044] The functional validation of the VDCCTA is further demonstrated by extending its applicability to several well-established electronic circuit designs, such as active inductors (AIS), filter circuits, and chaotic oscillators. The first VDCCTA-based application is realized for AIS implementation. Both a grounded positive active inductor (GPAI) and a grounded negative active inductor (GNAI) are designed using a single VDCCTA in conjunction with a grounded capacitor, as shown in [reference to be added]. Fig. 7 shown. The single active block topology in Fig. 7 offers multifunctional inductor behavior and provides both GPAI and GNAI functionality, which is controlled by the switching of the gate voltages at the MOSFET components M1 and M2.

[0045] The MOSFET bias control voltage (VC) facilitates the electronic tuning of the active inductor. The switching mechanism controlled by the MOSFET bias works as follows: When the bias control voltage (VC) is high, the NMOS transistor (M1) begins to conduct, thereby establishing an electrical path between the terminals O + and X. Conversely, the PMOS transistor (M2) conducts at low bias control voltage (VC) and establishes a current path between terminals X and O. - By modulating the MOSFET bias, the AIS behavior switches accordingly between GPAI and GNAI without requiring a change in the circuit topology. The corresponding admittance expressions for GPAI and GNAI are defined in equation (4). Zin(s)|Vc=0GPAI=sCgm1gm2, Zin(s)|Vc=1GNAI=−sCgm1gm2.

[0046] Fig. Figure 8 shows a diagram of the proposed VDCCTA FPAI according to an embodiment of the present disclosure.

[0047] In addition to the grounded configurations (GPAI / GNAI), the proposed VDCCTA is further extended to implement a floating positive active inductance (FPAI), as shown in Fig. Figure 8 shows the admittance of the FPAI being derived by applying a conventional circuit analysis and expressed in equation (5). [I1I2]=gm1gm2sC[+1−1−1+1][V1V2].

[0048] It is observed that the equivalent inductance of the FPAI is identical to that of the GPAI and the GNAI. Furthermore, normalized sensitivity analyses of the equivalent inductance (Leq) with respect to active and passive circuit components are calculated for the grounded and floating active inductor configurations, as expressed in equation (6). Sgm1L|GI / FI=Sgm2L|GI / FI=−1, SCL|GI / FI=1.

[0049] The sensitivity values ​​are on the order of one, confirming that both grounded and ungrounded inductors implemented with the proposed active element exhibit low active and passive sensitivity.

[0050] Fig. Figure 9 shows a diagram of a fifth-order HP filter using GPAI according to an embodiment of the present disclosure.

[0051] To further extend the application of VDCCTA-based active inductors, a fifth-order high-pass (HP) filter is developed using the proposed GPAI, as shown in Fig. Figure 9. The transfer function of the passive high-pass filter of ninth order is determined by conventional circuit analysis and represented in equation (7), where the denominator coefficients (Di) are further defined by equation (8). T(s)|5th−order=s5C1C2C3Leq1Leq2RloadD5s5+D4s4+D3s3+D2s2+D1s+1, D5=C1C2C3Leq1Leq2(Rload+Rs)D4=Leq1Leq2(C1C2+C1C3+C2C3)+C1+C2C3RloadRs(Leq1+Leq2)D3=C3Rload(C2Leq 2+Leq1(C1+C2))+C1Rs(C3Leq2+C2(Leq1+Leq2))D2=Leq1(C1+C2)+Leq2(C2+C3)+C1C3RloadRsD1=C3Rload+C1Rs}.

[0052] Fig. Figure 10 shows a diagram of a chaotic circuit based on an operational amplifier according to an embodiment of the present disclosure.

[0053] Furthermore, the proposed GPAI is used to implement a chaotic circuit. The feasibility of the VDCCTA-based GPAI is demonstrated in the design of Chua's chaotic oscillator, where a small inductance value (in the range of nH to H) is advantageous. Conventional circuit implementations of Chua use a large inductance value (>10 mH), making them unsuitable for compact, resistance-free designs with active inductance. Fig. Figure 10 shows a chaotic operational amplifier-based circuit incorporating the proposed GPAI. In this design, the oscillation state (CO) and oscillation frequency (FO) are tuned by varying the resistance (R). The inductance term appearing in the expressions CO and FO is replaced by the proposed GPAI, allowing the oscillator to be controlled electronically via the transconductance parameters g. m1 (I B1 ) and g m2 (I B2 ) becomes tunable. Consequently, the chaotic circuit is implemented without physical inductance, enabling its integration as a completely inductance-free IC design. The electronically tunable CO and FO expressions of the proposed chaotic circuit are shown in equation (9). CO:RC2=(C2+C1)(R−d(C / gm1gm2))FO:fo=12πC1(R−d(C / gm1gm2))RC1C2Cgm1gm2}.

[0054] Fig. Figure 11 shows a diagram of a fourth-order LP filter using FPAI according to an embodiment of the present disclosure.

[0055] In addition to chaotic oscillator applications, the proposed FPAI is used in the design of a higher-order fourth-order low-pass (LP) filter, as in Fig. Figure 11 shows the routine circuit analysis yields the transfer function of the fourth-order passive LP filter, expressed in equation (10), with denominator coefficients (Di) explicitly defined in equation (11). T(s)|fourth−or=RLoadD4s4+D3s3+D2s2+D1s+RLoad, D4=Leq2C2RLoadD3=Leq2C+LeqC2RSRLoad+RSLeqCD2=LeqCRLoad+LeqCRSRLoadD1=Leq+CRSRLoad}.

[0056] Fig. Figure 12 shows a diagram of a universal second-order filter using the proposed FPAI according to an embodiment of the present disclosure.

[0057] Another filter application as a universal filter is based on the concept of multi-input, single-output (MISO) filter function architecture. The design uses the concept of a multi-input, single-output (MISO) architecture to achieve second-order universal filter functionality, as shown in Fig. Figure 12 illustrates the proposed filter, which comprises the FPAI and a small number of passive components, specifically a resistor and a capacitor. By applying the superposition principle, the output filter response (VO(s)) is derived by taking each input voltage individually and grounding the remaining inputs. Accordingly, the universal filter achieves five different filter responses: low-pass (LP), high-pass (HP), band-pass (BP), notch-pass (NP), and all-pass (AP).

[0058] Using conventional analysis, the voltage transfer function is derived, which provides the output voltage as a function of the applied input voltage, as expressed in equation (12). VO(s)|UF=s2C1C2R(V3)+sC2(V2)+gm1gm2R(V1)s2C1C2R+sC2+gm1gm2R.

[0059] The denominator of the transfer function is quadratic in the complex frequency variable (s), which gives both the 3 dB cutoff frequency (wo) and the quality factor (Qo), as expressed in equations (13) and (14). ωO=gm1gm2C1C2 QO=RC1gm1gm2C2,

[0060] It is important that the power parameters (ωo and Qo) are electronically determined via the transconductance parameter (g). mi) are adjustable, which provides inherent adjustability for the proposed filter. Finally, the active and passive sensitivities of the MISO VM universal filter are calculated as expressed in equations (15) and (16). Sgm1ωu=Sgm2ωu=12, SC1Qo=SC2Qo=−12, SRQo=1, SC1Qo=Sgm1Qo=Sgm2Qo=12, SC2Qo=−12.

[0061] Fig. Figure 13 shows a diagram of a general structure of a VDCCTA with a parasitic element according to an embodiment of the present disclosure.

[0062] The non-ideal performance evaluation of the active-element-based IS and VM MISO universal filter VDCCTA is due to non-ideal and parasitic elements connected to the active device. The dominant deviation in the frequency response is mainly attributable to the non-ideal frequency-dependent current transfer gain (αi(s)) and voltage transfer gain (β(s)), where αi(s) = αi / (1 + s / ωαi) and βi(s) = βs / (1 + s / ωβi). Furthermore, an additional term γ accounts for the inaccuracy of the OTA's transconductance transfer, while the parameters (RO and CO) denote parasitic elements at the OTA output. The modified characteristic equations, which account for non-ideal gains (α, β, and γ), are presented in equation (17) as shown below. [INIPIZVXIWPIWNIO±]=[00000000γgm1−γgm10000β0000α000−α00±γgm20][VPVNVZIX].

[0063] The revised expression for the equivalent inductance (Leq) of the active inductor simulator is derived taking into account the non-ideal gain factors (α, β and γ) of the VDCCTA and is represented in equation (18). Leq|α,θ,γGPI.FPI.GNI=±sCαγ2gm1gm2.

[0064] Furthermore, the sensitivity of the inductance value with respect to variations of α and γ is expressed in equation (19). SαLeq=1, SγLeq=−2.

[0065] Furthermore, the new transfer function in conjunction with the pole frequency and the quality factor is determined by using a non-ideal gain (α, β and γ) for the VM-MISO universal filter and is given in equations (20), (21) and (22). VO(s)|α,β,γUF=s2C1C2R(V3)+sC2(V2)+αγ2gm1gm2R(V1)s2C1C2R+sC2+αγ2gm1gm2R, ωO=γαgm1gm2C1C2, QO=γRαC1gm1gm2C2,

[0066] The sensitivity of the filter performance parameters (ω) O and Q O) Variations in α and γ are quantified as expressed in equation (23). Sγωo=SγQo=1, Sαωo=SαQo=−12.

[0067] Another class of non-ideal behavior is examined in more detail with regard to the parasitic elements inherent in the VDCCTA. A significant parasitic factor occurs at the X-nodes and is designated as R. X + sL X quantifiziert The parasitic resistances of terminals P, N, Z, W P and W N are considered R P, R N , R Z , R WP or R WN designated. The corresponding parasitic capacities are C P , C N , C Z , C WP and C WN The combined effects of parasitic and passive elements at the connections (as in the Fig. 7 and Fig. 13 shown), at the connections such as P and WRP, X and O+ / O-, Z, N and W N Grounded positive / negative active inductors are defined as follows: {Req1=RP‖RWP,Ceq1=CP+CWP},{Req2=Rx+sLx},{Req3=Ro+ / Ro−,Ceq3=Co+ / Co−},{Req4=Rz,Ceq4=C+Cz} and {R eq5 = R N || R WN , C eq5 = C N + C WN}. The modified transfer function for the input impedance of GPAI / GNAI, including parasitic elements, is derived and represented in equation (24). Zin(s)|GPI.GNIParasitic=Vi(s)Ii(s)=±Z1(Z2:Z3)(1+sCZ1)gm1Z1Z4(gm2Z3−1)+(Z2+Z3)(1+sCZ1).

[0068] Fig. 13 (connection parasites) and Fig. The configuration shown in Figure 8 (passive elements) retains the same parasitic and passive element combinations as in GPAI, with the addition of an additional parasitic combination at the N and WN terminals, where R eq5 = R P || RWN and C eq5 = C N + C WN. Consequently, the new transfer function for the input impedance is derived and expressed in equation (25). For simplification, equations (24) and (25) are modeled using the impedance components Z1, Z2, Z3, Z4 and Z5, as shown in equation (26). Zin(s)|PFIParasitic=Z(Z2+Z3)sC(Z2+Z3)sC+2gm1(1+gm2Z3)(1+sCZ4)Z. Z1=Req1‖Ceq1Z2=Req2Z3=Req3‖Ceq3Z4=Req4‖Ceq4Z5=Req5‖Ceq5Z=Z1=Z5}.

[0069] Furthermore, the parasitic elements involved in the proposed universal filter transfer function VM-MISO are similar to the parasitic elements associated with the FPAI configuration, i.e., Z1 = R eq1 || C eq1 , Z2 = R eq2 || C eq2 , Z3 = R eq3 || C eq3 , Z4 = R eq4 || C eq4 and Z5 = R eq5 || C eq5.The values ​​of the equivalent resistors and capacitors are determined as follows: {Req1=RP‖RWP,Ceq1=CP+CWP},{Req2=Rx+sLx},{Req3=Ro+,Ceq3=Co+},{Req4=Rz,Ceq4=C+Cz} and {R eq5 = R N || R WN , C eq5 = C N + C WN Taking into account these parasitic elements within the universal filter circuit VM-MISO ( Fig. 12 and Fig. 13) the five response transfer functions are expressed in equation (27) where the numerator (Ni) and denominator coefficients (Di) are defined in equation (28). VO(a)Vm(s)|LPParasitic=N0s2D2+sD1+D0VO(a)Vm(s)|HPParasitic=s2N2s2D2+sD1+D0VO(a)Vm(s)|BPParasitic=sN 1s2D2+sD1+D0VO(a)Vm(s)|NFParasitic=N0+s2N2s2D2+sD1+D0VO(a)Vm(s)|APParasitic=s2N2−sN1+N0s2D2+sD1+D0}, N2=(Z2+Z3)C1C2RZ1Z4,N1=(Z2+Z3){C1RZ1+(R+Z1)C2Z4+RZ1},N0=gm1(1−gm2)RZ1Z4, D2=(Z2+Z3)C1C2RZ1Z4,D1=(Z2+Z3){C1RZ1+(R+Z1)C2Z4+RZ1},D0=gm1(1−gm2)RZ1Z4.

[0070] The present invention presents an inductor simulator (IS) for grounded and floating modes, which uses a grounded capacitor and employs a novel active element called the Voltage Differencing Current Conveyor Transconductance Amplifier (VDCCTA). The VDCCTA is constructed by integrating a Voltage Differencing Current Conveyor (VDCC) with a transconductance amplifier (TA) at the Z-terminal of the VDCC. The VDCCTA is ideally suited for inductor design, and its functionality can be extended to other areas such as filter design, chaotic oscillator implementation, and related electronic applications. Compared to conventional voltage-mode (VM) counterparts, the newly proposed block offers extended dynamic range, superior linearity, wide bandwidth, higher slew rate, and excellent low-voltage performance.

[0071] Furthermore, the proposed active element is particularly advantageous for IS circuit design and filter circuit conversion compared to previous VDCC-based IS configurations. The inclusion of TA parameters in the VDCCTA introduces an additional tunability function. Since the inductor circuits are implemented exclusively with grounded capacitors and no external passive resistors are required, they form canonical structures ideally suited for implementation in fully integrated circuits. Moreover, the P and N or O terminals allow for + and O -Grounded dual-mode IS operation is achieved through switching control or voltage biasing. Similarly, the differential input terminals P and N, together with the current-feeding output terminals Wp and Wn in the VDCCTA, enable floating IS configurations by fully utilizing the available connections. This work demonstrates the flexibility of this approach for floating IS circuits and its direct application in the realization of voltage-mode MISO filters (VM-MISO). A detailed evaluation of the proposed IS configuration is also presented with respect to tunability, frequency range, matching limitations, IS type, and filter design feasibility.

[0072] The present invention aims to implement the novel active block VDCCTA, developed by combining two active devices: VDCC and OTA. The connection behavior of the CMOS-based VDCCTA design was verified by simulation using the Personal Simulation Program with Integrated Circuit Emphasis (PSPICE), and its characteristic features are systematically summarized. This IS design enables the implementation of zero-resistance grounded and floating inductors with a single VDCCTA block. The performance of the IS was validated by analyzing its impedance-frequency characteristics and extended for various electronic applications.

[0073] Performance testing of VDCCTA-based applications, including inductor topologies ( Fig. 7 and Fig. 7), a fifth-order high-pass filter ( Fig. 9), a chaotic oscillator circuit ( Fig. 10), a fourth-order low-pass filter ( Fig. 11) and a VM MISO universal filter ( Fig. 12), were successfully simulated with PSPICE. The MOS-VDCCTA core ( Fig. 2(b)) was designed and implemented using 0.18 µm CMOS process parameters from Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), with a 0.9 V power supply and bias currents (I B1 = I B2 = 24.5 µA and I A = 100 µA) with MOS aspect ratios.

[0074] The functionality of the proposed active element, the VDCCTA, as an active core device is extended for the development of active inductors, filter circuits, phase cancellation networks, and chaotic waveform generators. The proposed inductor simulator is implemented with a VDCCTA and a single grounded capacitor, eliminating the need for passive component matching while ensuring perfect tunability through bias current. The inductor simulators have been proven to operate effectively in the frequency range from 10 kHz to 5 MHz. The proposed active-element-based inductor offers the following features: 1. The possibility of realizing both grounded and floating inductors with a single active element. A second possibility is to achieve both positive and negative inductive operations with a single active block using MOSFET switching control. 3. A wide tuning range, making it suitable for the design of monolithic integrated circuits. 4. Low power consumption (0.645 mW). 5. Built-in tunability features.

[0075] Furthermore, a voltage-mode (VM) filter can be implemented by integrating two passive elements into the proposed positive floating active inductor. The universal VM-MISO filter requires only a canonical number of passive components and exhibits a low output impedance. The proposed filter structures are characterized by low sensitivity, inherent tunability, and orthogonal control of both the quality factor and the pole frequency. A non-ideal analysis of the proposed inductor simulators and filter structures was also performed. Simulations conducted with 0.18 µm TSMC CMOS parameters confirm the theoretical analysis. The proposed filter exhibits low total harmonic distortion (%THD).

[0076] The drawings and the preceding description show examples of embodiments. Those skilled in the art will recognize that one or more of the described elements can be combined to form a single functional element. Alternatively, certain elements can be divided into several functional elements. Elements of one embodiment can be added to another embodiment. For example, the sequence of the processes described here can be changed and is not limited to the manner described here. Furthermore, the actions of a flowchart need not be implemented in the sequence shown; nor does it necessarily have to be performed by all actions. Actions that are not dependent on other actions can also be performed in parallel with the other actions. The scope of the embodiments is in no way limited by these specific examples.Numerous variations are possible, whether explicitly stated in the specification or not, such as differences in structure, dimensions, and material use. The range of embodiments is at least as broad as specified in the following claims.

[0077] Advantages, further benefits, and solutions to problems have been described above with reference to specific embodiments. However, the advantages, benefits, solutions, and all components that may lead to an advantage, benefit, or solution occurring or becoming more apparent are not to be construed as critical, necessary, or essential features or components of any or all claims. REFERENCES 100 A voltage difference current transfer transconductance amplifier system (Vdccta). 102 Differential voltage current feed module (Vdcc) 104 Operational Transconductance Amplifier Module (Ota) 106 Variety of Terminals 106a Input terminals 106b Output terminals 106c Buffered Terminals 108 CMOS Internal Architecture

Claims

[1] A voltage differential current feed transconductance amplifier system (VDCCTA) consisting of: a voltage differential current booster module (VDCC); an operational transconductance amplifier (OTA) module, combined with the VDCC module on a Z-connector; and a variety of connections, including: two input connections; five output connections; and two buffered connections, wherein the two input connections are configured to receive differential input voltages, one output connection is configured to provide current output, two output connections are configured to provide current images of the connection providing current output, and two further output connections are configured to provide transconductance outputs; the system is configured to be tunable by pre-flows; and the system is further configured to operate as an active inductor simulator when connected to a grounded capacitor. [2] System according to claim 1, wherein the transconductance parameters are configured to be controlled by bias current and electrical MOSFET parameters, including electron mobility, gate oxide capacitance and transistor width and length parameters. [3] System according to claim 1, further comprising an internal CMOS architecture configured to implement the functions of the differential voltage current feeder and the operational transconductance amplifier. [4] System according to claim 1, wherein the system is configured to implement: a grounded positive active inductor configuration (GPAI); a grounded negative active inductor configuration (GNAI); and a floating positive active inductor configuration (FPAI) using a single VDCCTA block; and a grounded capacitor without component matching requirements, wherein a higher-order high-pass filter is designed using the GPAI, wherein the GPAI is also suitable for chaotic circuit application, and wherein the FPAI is used for a higher-order low-pass filter [5] System according to claim 1, wherein the system is further configured to implement a universal voltage-mode filter configuration with multiple inputs and one output by adding two external passive elements to a positive floating inductor configuration. [6] System according to claim 1, wherein the system is further configured to implement a chaotic circuit generator configuration using the VDCCTA block, wherein the system is configured to generate chaotic waveforms using the transconductance properties of the VDCCTA.

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