Method for managing the power consumption of a memory device when using an error-correcting code and corresponding system

Abstract

A first memory domain (DM1) comprises a first portion of a first memory area (sram1) storing data, and a second memory domain (DM2) comprises a second portion of a second memory area (sram5) storing error-correcting code control bits associated with the data. Processing means (MT) are configured so that, upon the first read of data from said first portion, the error-correcting code control bits associated with that data, as well as all other error-correcting code control bits stored in said second portion, are read during the same memory access, and these other error-correcting code control bits are stored in a register (RG). Upon a subsequent read of other data from said first portion, the error-correcting code control bits associated with that other data are extracted from the register. Figure for the abbreviated version: [Fig. 2]

Description

Title of the invention: Method for managing the consumption of a memory device when using an error-correcting code and corresponding system

[0001] Implementations and embodiments of the invention relate to managing the consumption of a memory device when using an error correction code (ECC) in this memory device, in particular a volatile memory device, for example a static random access memory (SRAM) device.

[0002] An error-correcting code is well known to those skilled in the art and makes it possible to correct the erroneous logic value of a bit. More precisely, with an error-correcting code, if s control bits are added to b data bits, r errors among the b+s bits can be corrected.

[0003] When it is desired to implement an error-correcting code, the size of the memory containing the data and the control bits is greater than the size of a memory intended to store data without the use of an error-correcting code.

[0004] For information purposes, a static memory intended to store data over a width of 32 bits (32-bit words) has an additional width of 7 bits for storing the control bits, which leads to an overall width of 39 bits, so as to be able to store 39-bit words.

[0005] This results in a 22% increase in surface area compared to a 32-bit memory not intended to store control bits.

[0006] In the case where a user does not want to use error correcting code in a particular application, this additional 22% memory area will never be used because it is not accessible for data storage. However, this lost memory area has a direct impact on leakage currents, which is not negligible for low-power products.

[0007] Adding memory space also has an impact on the cost of the device.

[0008] It was proposed in the French patent application published under No. 3089317 to use a memory structure offering greater flexibility in the management of the memory space of a memory so as to take into account the optional nature of the use of an error correcting code.

[0009] Thus, in this aforementioned patent application, a memory was proposed capable of storing data and error-correcting code control bits and of possibly being able to reuse the memory space provided for these control bits, for purposes data storage in case in some applications it is not planned to use error correcting code.

[0010] More specifically, a system has been proposed comprising a memory device comprising a first memory domain intended to store first data at first addresses and a second memory domain intended to store, on command, either second data at second addresses, or error-correcting code control bits associated with the first data at third addresses.

[0011] This system is based on an organization of the memory domains in rows and on a particular storage of the data bits and the control bits (when it is planned to use an error correcting code) in these rows with a specific addressing.

[0012] That being said, when it is planned to use an error correcting code in such a system, for each memory access of a data item in the first memory domain, it is necessary to have a memory access in the second memory domain, which doubles the consumption.

[0013] There is therefore a need to reduce consumption in such a system using error correcting codes.

[0014] Although a preferred embodiment of the invention applies particularly to the system described in the aforementioned patent application, it is proposed according to a more general aspect, a system comprising -a memory device, for example a volatile memory device

[0015] comprising a first memory domain comprising at least a first part of at least a first memory area, and possibly several memory areas, intended to store data and a second memory domain comprising at least a second part of a second memory area intended to store error correcting code control bits associated with the data, -a register, and - processing means.

[0016] According to this general aspect, the processing means are configured to - during a first reading of data in the first part of the first memory zone, read during the same memory access, the error correction code control bits associated with this data as well as all the other error correction code control bits stored in the second part of the second memory zone and store in the register all these other error correction code control bits, and -when subsequently reading another data item in the first part of the first memory area, extract from the register the error correction code control bits associated with this other data item.

[0017] Thus, only one memory access is performed in the second memory domain during the first reading of data in the first memory zone, because this single memory access is used to extract all the error correction code control bits stored in this second memory domain and to store in the register the control bits associated with the other data stored in the first memory zone in order to extract them there during subsequent memory accesses to the first memory zone.

[0018] And accessing a register is less expensive in terms of consumption than accessing a memory.

[0019] According to an embodiment particularly suited to a system of the type described in the aforementioned patent application, - said at least one first memory zone and the second memory zone comprise rows, -each row of said at least one first memory zone and each row of the second memory zone are configured to store words of p bytes, -the control bits associated with the data stored in p successive rows of said at least one first memory area are stored in the p bytes of a row of the second memory area.

[0020] Furthermore, the processing means are configured to -during said first reading of a data item stored in a row of the first memory area, read during the same memory access, the byte containing the error correction code control bits associated with this data item and stored in the corresponding row of the second memory area as well as p-1 other bytes stored in said corresponding row of the second memory area and store these p-1 other bytes in the register, and - during said subsequent reading of another data item in another row of the first memory area, extracting from the register the byte containing the error correction code control bits associated with this other data item.

[0021] According to another aspect, a method for managing the consumption of a system is proposed, the system comprising a memory device comprising a first memory domain comprising at least a first part of at least a first memory area storing data, a second memory domain comprising at least a second part of a second memory area storing error correcting code control bits associated with the data, and a register, the method comprising, during a first reading of a data item in the first part of the first memory area, a reading during the same memory access, of the error correcting code control bits associated with this data item as well as all the other error correcting code control bits stored in the second part of the second memory area and a storage in the register of all the other error correcting code control bits error correcting code check, and upon a subsequent reading of another data item in the first part of the first memory area, an extraction from the register of the error correcting code check bits associated with this other data item.

[0022] According to an embodiment in which said at least one first memory area and the second memory area comprise rows, each row of said at least one first memory area and each row of the second memory area storing words of p bytes, the control bits associated with the data stored in p successive rows of said at least one first memory area being stored in the p bytes of a row of the second memory area, the method comprises during said first reading of a data item stored in a row of the first memory area, a reading during the same memory access of the byte containing the error correction code control bits associated with this data item and stored in the corresponding row of the second memory area as well as p-1 other bytes stored in said corresponding row of the second memory area and a storage in the register of these p-1 other bytes,and upon said subsequent reading of another data item in another row of the first memory area, an extraction from the register of the byte containing the error correction code control bits associated with this other data item.

[0023] The memory device may be a volatile memory device, for example a static random access memory (SRAM) but also a non-volatile memory, for example an EEPROM type memory, without these examples being limiting.

[0024] Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiment of the invention, which are in no way limiting, and the appended drawings in which

[0025] [Fig.l],

[0026] [Fig.2],

[0027] [Fig.3],

[0028] [Fig.4],

[0029] [Fig.5],

[0030] [Fig.6],

[0031] [Fig.7] and

[0032] [Fig.8] illustrate embodiments and implementations of the invention.

[0033] We will now describe embodiments and implementations compatible with a system structure of the type described in the aforementioned French patent application to which those skilled in the art may refer.

[0034] In [Fig.l], the reference DMM designates a memory device, here a volatile memory device, comprising a first memory domain DM1 and a second DM2 memory domain.

[0035] The first memory domain DM1 comprises four first memory areas sraml, sram2, sram3 and sram4 of identical memory size.

[0036] In the example illustrated here, these first memory areas are formed by distinct static RAMs. That being said, it would also be conceivable for these memory areas to be memory areas of the same memory.

[0037] The second memory domain DM2 comprises a second memory area sram5, of memory size identical to that of the memory areas sraml-sram4.

[0038] Again, the sram5 memory area is static RAM.

[0039] Each memory area has rows.

[0040] In the example described here, the width of the memory device is equal to 32 bits, that is to say that 32-bit data words each comprising four bytes can be stored.

[0041] The memory size is equal to n kbits, for example 64 kbits.

[0042] The memory areas sraml-sram4 are intended to store respectively Data-mem-cutl-4 data.

[0043] The sram5 memory area is intended to contain the error-correcting code control bits associated with the data stored in the sraml-sram4 memory areas.

[0044] The SYS system comprises, as illustrated in [Fig.2], a register RG and processing means MT comprising an SRINT interface connected to a BSS bus which can be of any conventional structure and for example an AHB bus using a protocol described for example in the document AMBA 3 AHB-Lite Protocol V1.0 Specification, from the company ARM (2001, 2006).

[0045] This bus carries in particular the Data-mem-cutl-4 data, HADRR initial addresses associated with the data, as well as other conventional bus signals not shown here for the sake of simplification.

[0046] The SRINT interface, of classic structure and known per se, is configured to deliver associated addresses given Data-mem-cutl-4

[0047] These addresses are taken from the initial HADRR addresses which were carried on the BSS bus.

[0048] The addresses could be identical to the initial addresses. However, depending on the system architecture, and in particular the width of the memory areas, the addresses can be obtained from the initial addresses by truncation of one or more bits.

[0049] In the example described here, it is possible to write in each row of a memory zone srami, i equal to 1, 2, 3, or 4, a 32-bit word composed of 4 bytes of 8 bits.

[0050] Thus, in this example, the Add-mem-cutl-4 references designate the addresses of a row of memory areas sraml-4 and the reference Mask-mem-cutl-4 designates the number of the byte in the designated row of the memory area considered.

[0051] Thus, the Add-mem-cutl-4 addresses and the Mask-mem-cutl-4 masks form said data storage addresses.

[0052] The WEN-cut-1-4 signals are conventional signals for controlling writing in the different memory areas and the CSEN-cutl-4 signals are conventional signals for selecting the memory area in question.

[0053] The processing means also comprise an error correcting code module MECC, of ​​conventional structure and known per se, configured to determine the control bits associated with said data Data-mem-cutl-4.

[0054] More precisely, for a four-byte word stored in a row of an sraml-4 memory area, the reference S designates the s control bits associated with this 4-byte word.

[0055] S is, in the case of a 32-bit word, a 7-bit word. Consequently, S can be stored in one byte of the sram5 memory area.

[0056] If the memory width were 64 bits and not 32 bits, S would be 8 bits long, which could still be stored in one byte of sram5 memory.

[0057] As is conventional, to write a new 32-bit word in a row of one of the memory areas sraml to sram4, we first read the word already stored in this row.

[0058] Then, the error correcting code module MECC determines a syndrome from the data bits and the set S of check bits.

[0059] It is recalled here that a syndrome is the result of the intermediate calculations carried out during error correction allowing the error to be detected and located.

[0060] If a bit is defective, the MECC block actually detects this defective bit and proceeds to correct it.

[0061] Before writing the new word to the address of the previous word in the corresponding memory area, the MECC block calculates the new set S of the new control bits corresponding to the new data bytes. In this regard, the new set S of the control bits is calculated with, where appropriate, the corrected value of the defective bit.

[0062] Then, the new word is written into the memory area corresponding to the first corresponding address.

[0063] As for the new set S of control bits, it is, as illustrated in [Fig.2], delivered to a memory interface DM2INT of the second memory domain DM2.

[0064] The processing means also comprise a BMT processing block configured to determine storage addresses of these control bits S.

[0065] These control bits S will in fact be stored in the sram5 memory area.

[0066] Such an address here comprises the address A-ecc of a row of the sram5 memory zone as well as an M-ecc mask making it possible to select one of the 4 bytes in said row.

[0067] As will be seen in more detail below, these addresses are determined from the Add-mem-cutl-4 row addresses.

[0068] The addresses A-ecc, M-ecc are also delivered to the DM2INT interface.

[0069] The signals WEN-cutl-4 and CSEN-cutl-4 are delivered to the DM1INT interface coupled to the first memory domain DM1.

[0070] [Fig.3] illustrates more particularly the obtaining of the addresses associated with the data intended to be stored in the sraml-sram4 memory zones from the initial HADRR addresses received by the SRINT memory interface.

[0071] In the example described here, the initial HADDR addresses are 18-bit coded addresses b0-bl7.

[0072] The left part of [Fig.3] illustrates these addresses in hexadecimal format.

[0073] The Add-mem-cut addresses are obtained by truncating the two least significant bits b0, bl of the initial addresses.

[0074] Thus, the right part of [Fig.3] illustrates these Add-mem-cut addresses in hexadecimal format.

[0075] More precisely, the value 0000 is the starting address of the sraml area while the address 3FFF is the ending address of this sraml memory area.

[0076] Address 4000 is the starting address of the sram2 memory area while address 7FFF is the ending address of this sram2 memory area.

[0077] Address 8000 is the starting address of the sram3 memory area while address BFFF is the ending address of this sram3 memory area.

[0078] Finally, the address C000 is the starting address of the sram4 memory area while the address FFFF is the ending address of the sram4 memory area.

[0079] [Fig.4] illustrates an example of obtaining A-ecc addresses from the first Add-mem-cut addresses.

[0080] More precisely, here again, a two-bit truncation of the Add-mem-cut addresses is carried out to obtain the A-ecc address of the corresponding row in the sram5 memory area.

[0081] More precisely, this truncation is a truncation of the two least significant bits bO-bl of the Add-mem-cut address.

[0082] Thus, the control bits S associated with the data stored in the sraml memory area will be written between addresses 0000 and 0FFF of the sram5 memory area.

[0083] The control bits associated with the data written in the sram2 memory area will be stored between addresses 1000 and 1FFF of the sram5 memory area.

[0084] The control bits associated with the data written in the sram3 memory area will be stored between addresses 2000 and 2FFF of the sram5 memory area.

[0085] Finally, the control bits associated with the data written in the sram4 memory area will be stored between addresses 3000 and 3FFF of the sram5 memory area.

[0086] Finally, as illustrated in [Fig.5], the M-ecc mask depends on the value of the two least significant bits bl, bO of the Add-mem-cut address.

[0087] More precisely, if these two bits bl, bO are equal to 0, then the first byte of M-ecc is equal to 1, the other bits being equal to 0, which means that the first byte of the corresponding row is selected to store the control bits S.

[0088] If the two bits bl, bO are respectively 0 and 1, then this time it is the second byte of the M-ecc mask which is 1, which means that the second byte of the row is selected to store the control bits S.

[0089] If bits bl, bO are respectively 1 and 0, this time it is the third byte of M-ecc which is 1 which corresponds to a selection of the third byte of the corresponding row to store the control bits S.

[0090] Finally, if both bits bl and bO are equal to 1, then it is the fourth byte of M-ecc that is equal to 1, which corresponds to a selection of the fourth byte of the corresponding row to store the control bits.

[0091] Of course, this way of determining M-ecc also applies to the determination of Mask-mem-cutl-4 so as to select for each byte of a data word to be stored, the corresponding byte in the addressed row.

[0092] Thus, for example, if we wish to store a byte of data at the initial address HADDR equal to 0x2001ABC8, the address will be equal, after truncation of the initial address, to 6AF2, which corresponds to a first Add-mem-cut2 address of a row of the second sram2 memory zone.

[0093] As for the 7-bit word forming the word S of the control bits associated with the new 32-bit word stored in the row, the address A-ecc of the corresponding row in the memory area sram5, is worth after truncation of the address Add-mem-cut2, 1ABC.

[0094] The M-ecc mask associated with this row address indicates, since the two least significant bits bl, bO of the first address are respectively 1 and 0, a selection of the third byte of this row to store this control word S.

[0095] In the example illustrated in [Fig.6], it is assumed that all memory areas sraml to sram2 and sram5 have a memory size of 64 kbits with a word width of 32 bits.

[0096] Consequently, each memory area has 2048 rows, each row being able to contain a 32-bit word (4 bytes).

[0097] A group of 4 rows of the sraml memory area represents a first part of this sraml memory area

[0098] A row of the sram5 memory area represents a second part of this area memory.

[0099] The error correcting code is applied. Each control word associated with a 32-bit data word contains 7 control bits.

[0100] By applying the rules for determining the addresses and masks mentioned above, we see that the set SU of control bits associated with the four bytes 0CT01, OCT11, OCT21 and OCT31 of the data in the first row of the sraml memory area will be stored in the byte OCT35 of the first row of the sram5 memory area.

[0101] Similarly, the word S21 of control bits associated with the four bytes OCT02, OCT12, OCT22 and OCT32 of the data of the second row of the memory area sraml, will be stored in the byte OCT25 of the first row of the memory sram5.

[0102] The word S31 of control bits associated with the four bytes OCT03, OCT13, OCT23 and OCT33 of the data of the third row of the sraml memory will be stored in the byte OCT15 of the first row of the sram5 memory.

[0103] Finally, the word S41 of control bits associated with the four bytes OCT04, OCT14, OCT24 and OCT34 of the data of the fourth row of the memory area sraml will be stored in the byte OCT05 of the first row of the memory area sram5.

[0104] And, this process of storing the different control bit words associated with the different rows will continue.

[0105] Generally speaking, the four words of control bits associated with the four words of four consecutive rows of a sram memory area, i varying from 1 to 4, will be stored in a single row of the sram5 memory area.

[0106] As a result, the control words associated with the 2048 rows of the sraml memory area will be stored in 512 rows of the sram5 memory.

[0107] And, the following 512 rows of the sram5 memory will be dedicated to the storage of the Si2 words of control bits associated with the data stored in the sram2 memory area.

[0108] We now refer more particularly to figures 7 and 8 to describe a mode of implementing consumption management when using error correcting code words.

[0109] It is assumed in step ST70 that the processing means MT activate reading means of conventional structure so as to carry out a first reading in the memory zone sraml of the data materialized by the four bytes OCT01 to OCT31 (see [Fig.6]).

[0110] The processing means MT then activate in step ST71 the reading means, so as to carry out during the same memory access a reading of the entire first row of the memory zone sram5 and extract the bytes OCT05, OCT15, OCT25 and OCT35.

[0111] The byte OCT35, representing the error correcting code word associated with the data materialized by the four bytes OCT01 to OCT31 is delivered (step ST72) while the other error correcting code bytes OCT05, OCT15 and OCT25 are stored in the register RG (step ST73).

[0112] During a subsequent sequential reading of the bytes OCT02 to OCT32 representing another data item from the group of the first four rows of the memory area sraml, the processing means MT extract from the register RG the byte OCT25 of error correction code associated with this other data item.

Claims

Claims

1. System comprising a memory device (DMM) comprising a first memory domain (DM1) comprising at least a first part of at least a first memory area (sraml) intended to store data and a second memory domain (DM2) comprising at least a second part of a second memory area (sram5) intended to store error correcting code control bits associated with the data, a register (RG), and processing means (MT) configured to, during a first reading of a data item in said first part of the first memory area, read during a same memory access the error correcting code control bits associated with this data item as well as all the other error correcting code control bits stored in the second part of the second memory area and store these other error correcting code control bits in the register,and upon a subsequent reading of another data item in the first part of the first memory area, extracting from the register the error correction code control bits associated with this other data item.,

2. System according to claim 1, wherein said at least one first memory area and the second memory area comprise rows, wherein each row of said at least one first memory area (sraml) and each row of the second memory area (sram5) are configured to store words of p bytes, the control bits associated with the data stored in p successive rows of said at least one first memory area are stored in the p bytes of a row of the second memory area, and the processing means (MT) are configured to, during said first reading of a data item stored in a row of the first memory area,reading during the same memory access the byte containing the error correction code control bits associated with this data and stored in the corresponding row of the second memory zone as well as the p-1 other bytes stored in said corresponding row of the second memory zone and storing these p-1 other bytes in the register, and during said subsequent reading of another data in another row of the first memory zone, extracting from the register the byte containing the error correction code control bits associated with this other data.,

3. System according to one of the preceding claims, in which the memory device (DMM) is a volatile memory device.

4. Method for managing the consumption of a system, the system comprising a memory device (DMM) comprising a first memory domain (DM1) comprising at least a first part of at least a first memory area storing data, a second memory domain (DM2) comprising a second part of a second memory area storing error correcting code control bits associated with the data, and a register, the method comprising, during a first reading of a data item in the first part of the first memory area, a reading during the same memory access, of the error correcting code control bits associated with this data item as well as all the other error correcting code control bits stored in the second part of the second memory area and a storage in the register of all the other error correcting code control bits,and upon a subsequent reading of another data item in the first part of the first memory area, an extraction from the register of the error correcting code control bits associated with this other data item.,

5. Method according to claim 4, in which, said at least one first memory area and the second memory area comprising rows, each row of said at least one first memory area (sraml) and each row of the second memory area storing words of p bytes, the control bits associated with the data stored in p successive rows of said at least one first memory area being stored in the p bytes of a row of the second memory area (sram5), the method comprises during said first reading of a data item stored in a row of the first memory area, a reading during the same memory access of the byte containing the error correction code control bits associated with this data item and stored in the corresponding row of the second memory area as well as p-1 other bytes stored in said corresponding row of the second memory area and a storage in the register of these p-1 other bytes,and upon said subsequent reading of another data item in another row of the first memory area, an extraction from the register of the byte containing the error correction code control bits associated with this other data item.,

6. Method according to one of claims 4 or 5, in which the device memory (DMM) is a volatile memory device.

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