CAPACITOR AND METHOD FOR MANUFACTURING A CAPACITOR

Abstract

According to one embodiment, a method for manufacturing a capacitor comprises providing a substrate (1) to be processed; providing a first conductive material portion (8) on the main surface (2a) of a semiconductor substrate (12) located in an opening (6); processing the conductive layer (4) in a pattern by dry etching; providing a first contact electrode (11), a second contact electrode (12), and a second conductive material portion (13); performing dry etching of the first conductive material portion (8) to disconnect the electrical connection between a connection portion (10) and the semiconductor substrate (2); and performing wet etching of the second conductive material portion (13) to disconnect the electrical connection between the first contact electrode (11) and the second contact electrode (12). Figure 17

Description

Title of the invention: CAPACITOR AND METHOD FOR MANUFACTURING A CAPACITOR Domain

[0001] Embodiments of the present invention relate to a capacitor and a method of manufacturing a capacitor. Background

[0002] In a method for producing a Si capacitor, after forming a trench in a Si substrate, a dielectric film and a poly-Si film are formed, and then a poly-Si film is patterned. The poly-Si film may be patterned by, for example, chemical dry etching (CDE). CDE is performed in a state where the Si substrate serving as a processing target substrate is clamped by means of an electrostatic chuck. In the case where the poly-Si film is patterned, contact between the poly-Si film and the Si substrate is lost. As a result, electric charges remain in the poly-Si film. Thus, the Si substrate is not separated from the stage even after it is unclamped, and damage such as cracks occurs in the Si substrate in the case where the Si substrate is pushed upward from the stage by means of a conductive lifting pin. Brief description of the drawings

[0003] [Fig.l] [Fig.l] is a top view of a processing target substrate to which a first step of a method of an embodiment is applied.

[0004] [Fig.2] [Fig.2] is a cross-sectional view of the treatment target substrate illustrated in [Fig.l], taken along line II-II.

[0005] [Fig.3] [Fig.3] is a circuit diagram illustrating the connection status of a portion to be a first fusible portion (poly-Si fusible portion).

[0006] [Fig.4] [Fig.4] is a top view of a treatment target substrate to which a second step of the method of the embodiment is applied.

[0007] [Fig.5] [Fig.5] is a cross-sectional view of the treatment target substrate illustrated in [Fig.4], taken along line VV.

[0008] [Fig.6] [Fig.6] is a top view of a treatment target substrate to which a third step of the method of the embodiment is applied.

[0009] [Fig.7] [Fig.7] is a cross-sectional view of the treatment target substrate illustrated in [Fig.6], taken along line VIL VIL

[0010] [Fig.8] [Fig.8] is a circuit diagram illustrating the connection status of the first fusible portion (poly-Si fusible portion).

[0011] [Fig.9] [Fig.9] is a top view of a treatment target substrate to which a fourth step of the method of the embodiment is applied.

[0012] [Fig. 10] [Fig. 10] is a cross-sectional view of the treatment target substrate shown in [Fig.9], taken along line XX.

[0013] [Fig. 11] [Fig. 11] is a top view of a processing target substrate to which a fifth step of the method of the embodiment is applied.

[0014] [Fig. 12] [Fig. 12] is a cross-sectional view of the treatment target substrate shown in [Fig.l 1], taken along line XII-XII.

[0015] [Fig. 13] [Fig. 13] is a top view of a processing target substrate to which a sixth step of the method of the embodiment is applied.

[0016] [Fig. 14] [Fig. 14] is a cross-sectional view of the treatment target substrate shown in [Fig. 13], taken along line XIV-XIV.

[0017] [Fig. 15] [Fig. 15] is a circuit diagram illustrating the connection status of the first fusible portion (poly-Si fusible portion) and a second fusible portion (Al fusible portion).

[0018] [Fig. 16] [Fig. 16] is a top view of a processing target substrate to which a seventh step of the method of the embodiment is applied.

[0019] [Fig. 17] [Fig. 17] is a cross-sectional view of the treatment target substrate shown in [Fig. 16], taken along line XVILXVIL

[0020] [Fig. 18] [Fig. 18] is a top view of a processing target substrate to which an eighth step of the method of the embodiment is applied.

[0021] [Fig. 19] [Fig. 19] is a cross-sectional view of the treatment target substrate shown in [Fig. 18], taken along line XIX-XIX.

[0022] [Fig.20] [Fig.20] is a circuit diagram illustrating the connection status of the first fusible portion (poly-Si fusible portion) and the second fusible portion (Al fusible portion).

[0023] [Fig.21] [Fig.21] is a top view of a treatment target substrate to which a ninth step of the method of the embodiment is applied.

[0024] [Fig.22] [Fig.22] is a cross-sectional view of the treatment target substrate illustrated in [Fig.21], taken along line XXII-XXIL

[0025] [Fig.23] [Fig.23] is a circuit diagram illustrating the connection status of the second fusible portion (Al fusible portion) and a third fusible portion (Al fusible portion).

[0026] [Fig.24] [Fig.24] is a top view of a treatment target substrate to which a tenth step of the method of the embodiment is applied.

[0027] [Fig.25] [Fig.25] is a cross-sectional view of the treatment target substrate illustrated in [Fig.24], taken along line XXV-XXV.

[0028] [Fig.26] [Fig.26] is a circuit diagram illustrating the connection status of the second fusible portion (Al fusible portion) and the third fusible portion (Al fusible portion).

[0029] [Fig.27] [Fig.27] is a cross-sectional view of a processing target substrate to which an eleventh step of the embodiment method is applied, taken along the x-axis direction.

[0030] [Fig.28] [Fig.28] is a top view illustrating a capacitor manufactured by the method of the embodiment.

[0031] [Fig.29] [Fig.29] is a cross-sectional view of the capacitor illustrated in the [Fig.28], taken along line XXVIIII-XXVIIII.

[0032] [Fig.30] [Fig.30] is a schematic view illustrating a step of attaching a target processing substrate to which dry etching is applied at one stage of an electrostatic chuck.

[0033] [Fig.31] [Fig.31] is a schematic view illustrating the state of the target substrate of treatment attached to the electrostatic chuck stage.

[0034] [Fig.32] [Fig.32] is a schematic view illustrating a state in which the substrate treatment target is locked on the electrostatic chuck stage.

[0035] [Fig.33] [Fig.33] is a schematic view illustrating a state after dry etching of the target processing substrate attached to the electrostatic chuck stage.

[0036] [Fig.34] [Fig.34] is a schematic view illustrating the state of the target substrate of processing in the case where the processing target substrate shown in [Fig.33] is unlocked from the electrostatic chuck stage.

[0037] [Fig.35] [Fig.35] is a schematic view illustrating a state in which a damage occurs in the processing target substrate in the event that the processing target substrate is unblocked from the electrostatic chuck stage. Detailed description

[0038] According to one embodiment, there is provided a method of manufacturing a capacitor. The method comprises: providing a substrate to be processed, the substrate comprising: a semiconductor substrate comprising a major surface having one or more recesses; a conductive layer disposed on the major surface and in the one or more recesses of the semiconductor substrate; and a dielectric layer disposed between the conductive layer and the semiconductor substrate, an opening penetrating the dielectric layer and the conductive layer being located on the major surface of the semiconductor substrate; providing a first portion of conductive material on the major surface of the semiconductor substrate located in the opening;

[0039] processing the conductive layer in the form of a pattern by dry etching, the pattern shape comprising a connection portion extending from the conductive layer and connected to the opening; providing a first contact electrode electrically connected to the conductive layer, a second contact electrode electrically connected to the semiconductor substrate, and a second portion of conductive material electrically connecting the first contact electrode and the second contact electrode; performing dry etching of the first portion of conductive material to disconnect the electrical connection between the connection portion and the semiconductor substrate; and implementing wet etching of the second portion of conductive material to disconnect the electrical connection between the first contact electrode and the second contact electrode. In one embodiment of the above-mentioned method, the semiconductor substrate contains silicon, and the conductive layer and the first portion of conductive material each contain poly-Si. In one embodiment of the above-mentioned method, the first contact electrode, the second contact electrode and the second portion of conductive material each contain aluminum.

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[0078] According to another embodiment, a capacitor comprises: a semiconductor substrate comprising a major surface having one or more recesses; a conductive layer disposed in the recess(es) and on the main surface of the semiconductor substrate; a dielectric layer disposed between the conductive layer and the semiconductor substrate; a connection portion from which the conductive layer located on the main surface of the semiconductor substrate extends; an opening connected to the connection portion and comprising a bottom wall located in the main surface of the semiconductor substrate; a first contact electrode electrically connected to the conductive layer; a second contact electrode electrically connected to the semiconductor substrate; a hole located between the first contact electrode and the second contact electrode and comprising a bottom wall located in the main surface of the semiconductor substrate; and an insulating layer placed in the opening and hole.

[0079] Embodiments will hereinafter be described in detail with reference to the accompanying drawings. Components which perform the same or similar functions are designated by the same reference numerals throughout the drawings, and repetitive descriptions will be omitted.

[0080] Dry etching is performed in a state where the substrate to be processed, serving as a processing target substrate, is clamped on one stage of an electrostatic chuck (ESC) in a reaction chamber. The electrostatic chuck used in dry etching processing will be described with reference to Figures 30 to 35. The substrate to be processed may be referred to as a processing target substrate.

[0081] [Fig. 30] is a schematic view illustrating a step of attaching a process target substrate to which dry etching is applied to a stage of an electrostatic chuck. First, a process target substrate 100, before application of dry etching, is pressed against a stage 200 of an electrostatic chuck by means of a conductive lifting pin 201.

[0082] As illustrated in [Fig.31], the processing target substrate 100 comprises a semiconductor substrate 101, a dielectric layer 102, and a conductive layer 103. The semiconductor substrate 101 is a Si wafer having a doped layer 101b doped with impurities on a single main surface 101a. A plurality of recesses (trenches) 104 are arranged in a single main surface 101a of the semiconductor substrate 101. The depth direction of each recess (trench) 104 is along the z-axis direction. In addition, the recesses (trenches) 104 are arranged along the x-axis direction at intervals from each other. Each recess (trench) 104 extends along the y-axis direction.

[0083] The dielectric layer 102 is disposed on the main surface 101a of the semiconductor substrate 101 and an inner surface of each recess 104. The conductive layer 103 is embedded in each recess 104. The conductive layer 103 covers the dielectric layer 102 in the recess 104 and the dielectric layer 102 located on the main surface 101a of the semiconductor substrate 101. In addition, the conductive layer 103 covers a main surface 101c on the opposite side and an end surface 101c connecting the two main surfaces 101a and 101c. The conductive layer 103 is formed, for example, of poly-Si doped with impurities. Therefore, as illustrated in [Fig. 30], following contact of the conductive lifting pin 201 of the electrostatic chuck with the processing target substrate 100, charges 202 from the electrostatic chuck can be stored in the conductive layer 103. As a result, as illustrated in [Fig.32], the semiconductor substrate 101 of the processing target substrate 100 is electrostatically attracted toward the stage 200 of the electrostatic chuck. As a result, the conductive layer 103 is in electrical conduction with the stage 200 of the electrostatic chuck. In this state, . in the case where the processing target substrate 100 is detached from the electrostatic chuck by pushing upwards the processing target substrate by means of the conductive lifting pin 201, the residual charges 202 in the conductive layer 103 can be discharged onto the stage from the conductive layer 103.

[0084] However, patterning the conductive layer 103 by dry etching disconnects the electrical conduction between the conductive layer 103 and the stage 200 of the electrostatic chuck, as illustrated in [Fig. 33]. As a result, as illustrated in [Fig. 34], the residual charges 202 remain in the conductive layer 103. A region 203 in which the residual charges 202 remain is indicated by a dashed frame. Therefore, as illustrated in [Fig. 35], even the upward pushing of the processing target substrate 100 by the conductive lifting pin 201 does not allow discharge of the residual charges, and the state in which the processing target substrate 100 is electrostatically attracted to the stage 200 is not released. Therefore, damage 204 such as cracks occurs in the semiconductor substrate 101 of the processing target substrate 100.In the case where the processing target substrate 100 does not include the dielectric layer 102, the charges 202 stored in the conductive layer 103 leak to the stage 200 through the semiconductor substrate 101 even after the conductive layer 103 has been processed in a pattern form by dry etching. Therefore, the problem of a degumming failure does not arise.

[0085] A method of manufacturing a condenser according to one embodiment will be described with reference to Figures 1 to 29. In each drawing, the z-axis direction is a direction parallel to the thickness direction of the semiconductor substrate, the x-axis direction is a direction parallel to the main surface of the semiconductor substrate, and the y-axis direction is a direction parallel to the main surface of the semiconductor substrate and perpendicular to the x-axis direction. (First step)

[0086] The first step includes providing a dielectric layer and a first conductive layer on a semiconductor substrate having one or more recesses in a single major surface. The first step will hereinafter be described with reference to Figures 1 to 3. [Fig.l] is a top view of a substrate to be processed. The substrate to be processed may be referred to as a process target substrate. [Fig.2] shows a cross-sectional view of the process target substrate shown in [Fig.l], taken along line IL IL [Fig.3] is a circuit diagram illustrating the connection state of a portion to be a first fusible portion (poly-Si fusible portion).

[0087] A processing target substrate 1 comprises a semiconductor substrate 2, a dielectric layer 3, and a conductive layer 4.

[0088] The semiconductor is for example silicon (Si); germanium (Ge); a semiconductor formed from a compound of a Group III element and a Group V element, such as gallium arsenide (GaAs) or gallium nitride (GaN); and silicon carbide (SiC). The term "Group" used herein is a short form "Group" of the Periodic Table.

[0089] The semiconductor substrate is, for example, a semiconductor wafer. The semiconductor wafer may be doped with an impurity, and may comprise a semiconductor element such as a transistor or a diode. Furthermore, the main surface of the semiconductor wafer may be parallel to any crystal plane of the semiconductor. A usable semiconductor wafer is, for example, a Si wafer (silicon wafer) whose main surface is a (100) plane, or a Si wafer (silicon wafer) whose main surface is a (110) plane.

[0090] The semiconductor substrate 2 shown in [Fig.2] is a Si wafer having a doped layer 2b doped with P-type or N-type impurities on a single main surface 2a. A plurality of recesses (trenches) 5 are arranged in a single main surface 2a of the semiconductor substrate 2. The recesses (trenches) 5 may be processed by, for example, metal-assisted chemical etching (MacEtch). The depth direction of each recess (trench) 5 is along the z-axis direction. Among the recesses 5, some recesses 5 are arranged along the x-axis direction at intervals from each other, and other recesses 5 are arranged along the y-axis direction at intervals from each other.A pattern in which the recesses 5 are arranged along the x-axis direction and a pattern in which the recesses are arranged along the y-axis direction are alternately arranged along each of the x-axis direction and the y-axis direction. [Fig. 2] illustrates a pattern in which the recesses 5 are arranged along the x-axis direction, and does not illustrate a pattern in which the recesses are arranged along the y-axis direction.

[0091] The dielectric layer 3 is provided on the main surface 2a of the semiconductor substrate 2 and an inner surface of each recess 5. The dielectric layer is made of, for example, an organic dielectric or an inorganic dielectric. As the organic dielectric, for example, a polyimide can be used. As the inorganic dielectric, a ferroelectric can also be used, and examples of the inorganic dielectric layer may include an oxide film and a nitride film. Paraelectrics such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide are preferable. These paraelectrics have a small change in dielectric constant due to temperature. Therefore, the dielectric layer including the paraelectric can amplify the heat resistance of the capacitor.

[0092] The first conductive layer 4 is embedded in each recess 5. The first conductive layer 4 is in contact with the dielectric layer 3 in the recess 5. The first conductive layer 4 covers the dielectric layer 3 located on the main surface 2a of the semiconductor substrate 2. The first conductive layer 4 embedded in each recess 5 is connected to the first conductive layer 4 arranged above the main surface 2a of the semiconductor substrate 2. The first conductive layer 4 is arranged on the dielectric layer 3 located on the main surface 2a of the semiconductor substrate 2. Therefore, the first conductive layers 4 embedded in the respective recesses 5 are electrically connected to each other. The first conductive layer 4 is formed for example from poly-Si (polysilicon) doped with impurities. Poly-Si doped with impurities has a low resistance.Examples of the impurities may include P-type impurities and N-type impurities. The first conductive layer 4 is not limited to poly-Si, and may be formed, for example, of a metal such as molybdenum, aluminum, gold, tungsten, platinum, nickel, or copper, or an alloy comprising the metal. The first conductive layer 4 may have a single-layer structure or a multi-layer structure.

[0093] The dielectric layer 3 and the first conductive layer 4 may be formed not only on the main surface 2a of the semiconductor substrate 2 but also on the other main surface 2c and an end surface connecting the main surfaces 2a and 2c.

[0094] A fusible portion is not yet provided on the processing target substrate 1. Therefore, as illustrated in [Fig. 3], a portion to be a fusible portion is in a state E1 in which a capacitor having a metal-insulator-metal (MIM) structure is formed by the first conductive layer 4, the dielectric layer 3, and the semiconductor substrate 2. (Second step)

[0095] The second step comprises providing one or more openings in the dielectric layer and the first conductive layer located on the main surface of the semiconductor substrate. The second step will hereinafter be described with reference to Figures 4 and 5. [Fig.4] is a top view of a processing target substrate. [Fig.5] is a cross-sectional view of the processing target substrate shown in [Fig.4], taken along line VV.

[0096] One or more openings 6 penetrating the dielectric layer 3 and the first conductive layer 4 located on the main surface 2a of the semiconductor substrate are provided herein. The opening 6 is desirably disposed at a portion remote from a region where the pattern of recesses 5 is formed. In the example illustrated in [Fig.4], the opening 6 is disposed near the center of a portion side parallel to the y-axis direction of the main surface 2a of the semiconductor substrate 2. The opening 6 is a cylindrical cavity having a portion of the dielectric layer 3 and a portion of the first conductive layer 4 as inner walls and a portion of the main surface 2a of the semiconductor substrate 2 as a bottom wall. The opening 6 is defined by the portion of the dielectric layer 3, the portion of the first conductive layer 4 and the portion of the main surface 2a of the semiconductor substrate 2. The opening 6 constitutes the first fusible portion, but the first fusible portion has not yet been completed at the stage where the second step is completed. Therefore, the portion to be the first fusible portion is in a state E1 in which the capacitor having the MIM structure, similar to that in the first step, is formed.

[0097] In Figures 4 and 5, the number of openings 6 is one, but is not limited thereto, and several openings may be present.

[0098] The opening 6 may be treated by dry etching such as chemical dry etching (CDE). As an example of CDE, reactive ion etching (RIE) is indicated.

[0099] Dry etching is performed in a state where the processing target substrate 1 is held by an electrostatic chuck (ESC chuck). The first conductive layer 4 is formed, for example, of poly-Si doped with impurities, and thus can store charges from the electrostatic chuck. As a result, the semiconductor substrate 2 of the processing target substrate 1 is electrostatically attracted to one stage of the electrostatic chuck. Although not illustrated, the first conductive layer 4 is provided not only on the main surface 2a of the semiconductor substrate 2, but also on the other main surface 2c and an end surface connecting the main surfaces 2a and 2c. As a result, the first conductive layer 4 is in electrical conduction with the stage of the electrostatic chuck.In the case where the processing target substrate 1 is detached from the electrostatic chuck by pushing up the processing target substrate by means of the conductive lifting pin after the dry etching processing, residual charges in the first conductive layer 4 can escape from the first conductive layer 4 to the stage, and thus the processing target substrate 1 can be detached from the electrostatic chuck without being damaged. (Third step).

[0100] The third step comprises providing a first portion of conductive material in the opening. The first portion of conductive material constitutes a first fusible portion (e.g., a poly-Si fusible portion). The third step will be described hereinafter with reference to Figures 6 to 8. [Fig. 6] is a top view of a processing target substrate. [Fig. 7] is a cross-sectional view of the processing target substrate illustrated in [Fig. 6], taken along line VIL VIL [Fig.8] is a circuit diagram illustrating the connection status of the first fusible portion (poly-Si fusible portion).

[0101] A second conductive layer 7 is disposed on the first conductive layer 4 located on the entire surface of the main surface 2a of the semiconductor substrate 2 of the processing target substrate 1. At this time, a first conductive material portion 8 made of the same material as that for the second conductive layer 7 is embedded in the opening 6. The first conductive material portion 8 is in direct contact with the main surface 2a of the semiconductor substrate 2 located in the opening 6. The first conductive material portion 8 is also in contact with the first conductive layer 4. Therefore, the first conductive layer 4 is in electrical conduction with the semiconductor substrate 2 via the first conductive material portion 8. The first conductive material portion 8 is also called the first fusible portion (poly-Si fusible portion). As illustrated in [Fig.8], the electrical connection state in the first fusible portion (poly-Si fusible portion) has a state E2 in which the first conductive layer 4 is directly electrically connected to the semiconductor substrate 2. .

[0102] The second conductive layer 7 may be formed for example from the same material as that for the first conductive layer 4. [Fig.7] illustrates the boundary between the first conductive layer 4 and the second conductive layer 7 for easy understanding, but the boundary (interface) between the first conductive layer 4 and the second conductive layer 7 is not clear in some cases. (Fourth step)

[0103] The fourth step comprises forming a pattern on the first conductive layer and the second conductive layer by dry etching. The fourth step will be described hereinafter with reference to Figures 9 and 10. [Fig. 9] is a top view of a processing target substrate. [Fig. 10] is a cross-sectional view of the processing target substrate shown in [Fig. 9], taken along line XX.

[0104] The first conductive layer 4 and the second conductive layer 7 of the processing target substrate 1 are processed in a pattern form by means of dry etching. The dry etching may be performed after forming a mask by photolithography. Pattern formation is performed to separate the first conductive layer 4 and the second conductive layer 7 for each chip, thereby providing the first conductive layer 4 and the second conductive layer 7 each having a target area for a given chip. However, if the first conductive layer 4 and the second conductive layer 7 are processed so as to have a target area, electrical conduction between the first conductive layer 4 and a first fusible portion 8 is disconnected. Therefore, pattern formation is performed so that a connection portion (wiring portion) 10 which is in electrical conduction with the first conductive layer 4 and the first fusible portion 8 is formed. Specifically, the first conductive layer 4 and the second conductive layer 7 located outside the region where the pattern of the recesses 5 is formed, in other words at an edge portion of the main surface 2a of the semiconductor substrate 2, are removed by dry etching except for a portion to be the connection portion 10. The connection portion 10 formed by direct extension from each of the first conductive layer 4 and the second conductive layer 7 is connected to the opening 6. Therefore, the connection portion 10 is located on the inner wall of the opening 6. The first fusible portion 8 embedded in the opening 6 is in contact with the connection portion 10 located on the inner wall of the opening 6.The first fusible portion 8 is also in contact with the main surface 2a of the semiconductor substrate located on the bottom wall of the opening 6. As a result, the first conductive layer 4 and the second conductive layer 7 are electrically connected to the semiconductor substrate 2 by the connection portion 10 and the first fusible portion 8. The electrical connection state in the first fusible portion (poly-Si fusible portion) 8 is in a state E2 similar to that in the third step.

[0105] Examples of the dry etching may include the same types as those described in connection with the third step.

[0106] Dry etching is performed in a state where the processing target substrate 1 is held by an electrostatic chuck (ESC chuck). In the case where the processing target substrate 1 is detached from the electrostatic chuck by pushing upward the processing target substrate by means of the conductive lifting pin after the dry etching processing, the residual charges in the first conductive layer 4 and the second conductive layer 7 can flow from the first fusible portion 8 to the semiconductor substrate 2 and escape from the semiconductor substrate 2 to the stage, and thus the processing target substrate 1 can be detached from the electrostatic chuck without being damaged. (Fifth step)

[0107] The fifth step comprises forming a pattern on the dielectric layer 3 by dry etching. The fifth step will be described hereinafter with reference to Figures 11 and 12. [Fig. 11] is a top view of a processing target substrate. [Fig. 12] is a cross-sectional view of the processing target substrate shown in [Fig. 11], taken along line XII-XII.

[0108] The dielectric layer 3 of the processing target substrate 1 is processed in a pattern form by dry etching. The dry etching can be performed after forming a mask by photolithography. The pattern formation is performed to separate the dielectric layer 3 formed on the entire main surface 2a of the semiconductor substrate 2 for each chip, thus giving the dielectric layer 3 having a target area for a given chip. The electrical connection state in the first fusible portion 8 (poly-Si fusible portion) is a state E2 similar to that in the third step.

[0109] Examples of the dry etching may include the same types as those described in connection with the third step.

[0110] Dry etching is performed in a state where the processing target substrate 1 is held by an electrostatic chuck (ESC chuck). In the case where the processing target substrate 1 is detached from the electrostatic chuck by pushing upward the processing target substrate by means of the conductive lifting pin after the dry etching processing, the residual charges in the first conductive layer 4 and the second conductive layer 7 can flow from the first fusible portion 8 to the semiconductor substrate 2 and escape from the semiconductor substrate 2 to the stage, and thus the processing target substrate 1 can be detached from the electrostatic chuck without being damaged. (Sixth step)

[0111] The sixth step includes providing a first contact electrode on the conductive layer, providing a second contact electrode on the semiconductor substrate, and providing a second conductive material portion electrically connecting the first contact electrode and the second contact electrode. The formation of the first contact electrode, the formation of the second contact electrode, and the formation of the second conductive material portion may be performed in this order, or the second conductive material portion may be formed after the formation of the first contact electrode and the second contact electrode, or all may be performed in a single batch. The sixth step will hereinafter be described with reference to Figures 13 to 15. [Fig. 13] is a top view of a processing target substrate. [Fig.14] is a cross-sectional view of the processing target substrate shown in [Fig. 13], taken along line XIV-XIV. [Fig. 15] is a circuit diagram illustrating the connection state of the first fusible portion (poly-Si fusible portion). .

[0112] The conductive layer comprises the first conductive layer 4 and the second conductive layer 7. A first contact electrode 11 is arranged on the xy plane of the second conductive layer 7. On the other hand, a second contact electrode 12 is arranged on the main surface 2a of the semiconductor substrate 2. The second conductive material portion 13 is arranged for example between the first contact electrode 11 and the second contact electrode 12 at a position facing the first fusible portion 8, with the first contact electrode 11 interposed between the second conductive material portion 13 and the first fusible portion 8. The second conductive material portion 13 is in contact with both the first contact electrode 11 and the second contact electrode 12. The second conductive material portion 13 electrically connects the first contact electrode 11 and the second contact electrode 12. Thus, the first contact electrode 11 and the second contact electrode 12 are short-circuited by the second conductive material portion 13. Therefore, the second conductive material portion 13 acts as a second fusible portion (Al fusible portion) which carries the conductive layer in electrical conduction with the semiconductor substrate 2. Therefore, as illustrated in [Fig.15], a state E3 is established in which the conductive layer is in electrical conduction with the semiconductor substrate 2 by each of the first fusible portion 8 and the second fusible portion 13.

[0113] Each of the first contact electrode 11, the second contact electrode 12, and the second conductive material portion 13 is formed, for example, from a metal such as aluminum. Each of the first contact electrode 11, the second contact electrode 12, and the second conductive material portion 13 is obtained by forming a film, for example, by sputtering. The sputtering can form the first contact electrode 11, the second contact electrode 12, and the second conductive material portion 13 in a single batch, and thus the number of steps required for manufacturing can be reduced.

[0114] Before the Al sputtering, a barrier layer may be arranged on the second conductive layer 7 and the semiconductor substrate 2. The barrier layer may be formed, for example, from Ti or TiN. The barrier layer may be formed, for example, by sputtering. (Seventh step)

[0115] The seventh step comprises the formation of an insulating layer (first insulating layer). The seventh step will be described hereinafter with reference to Figures 16 and 17. [Fig. 16] is a top view of a processing target substrate. [Fig. 17] is a cross-sectional view of the processing target substrate shown in [Fig. 16], taken along line XVII-XVII.

[0116] For the insulation of each of the first contact electrode 11, the second contact electrode 12, the first fusible portion 8 and the second fusible portion 13, a first insulating layer 14 is disposed at the target position of the processing target substrate 1. The first insulating layer 14 is also called an interlayer insulating film. The first insulating layer 14 is formed of an insulating material such as tetraethoxysilane (TEOS) or polyethyleneimine (PI).

[0117] The states of the first fusible portion 8 and the second fusible portion 13 are a state E3 similar to that in the sixth step. (Eighth step)

[0118] The eighth step comprises removing the first fusible portion 8 by dry etching. The eighth step will be described hereinafter with reference to Figures 18 to 20. [Fig. 18] is a top view of a processing target substrate. [Fig. 19] is a cross-sectional view of the processing target substrate shown in [Fig. 18], taken along line XIX-XIX. [Fig.20] is a circuit diagram illustrating the connection state of the first fusible portion (poly-Si fusible portion) and the second fusible portion (Al fusible portion).

[0119] The first fusible portion 8 embedded in the opening 6 is removed by dry etching. The dry etching can be carried out after forming a mask by photolithography. As a result, the electrical conduction (state E2) between the conductive layer (in this case comprising the first conductive layer 4 and the second conductive layer 7) and the semiconductor substrate 2 is connected. The disconnected state is indicated by the reference numeral E4 in [Fig.20].

[0120] Examples of the dry etching may include the same types as those described in connection with the third step.

[0121] Dry etching is performed in a state where the processing target substrate 1 is held by an electrostatic chuck (ESC chuck). Although electrical conduction through the first fusible portion 8 is disconnected by dry etching, electrical conduction (state E3) between the conductive layer and the semiconductor substrate 2 can be ensured by the second fusible portion 13. In the case where the processing target substrate 1 is detached from the electrostatic chuck by pushing upward the processing target substrate by means of the conductive lifting pin, residual charges in the conductive layer can flow from the second fusible portion 13 to the semiconductor substrate 2 and escape from the semiconductor substrate 2 to the stage, and thus the processing target substrate 1 can be detached from the electrostatic chuck without being damaged. (Ninth step)

[0122] The ninth step includes providing a first pad electrode on the first contact electrode and providing a second pad electrode on the second contact electrode. The formation of the first pad electrode and the formation of the second pad electrode may be performed in this order, the order may be reversed, or the first pad electrode and the second pad electrode may be formed in a single batch. The ninth step will hereinafter be described with reference to Figures 21 to 23. [Fig. 21] is a top view of a processing target substrate. [Fig. 22] is a cross-sectional view of the substrate. treatment target shown in [Fig.21], taken along line XXII-XXII. [Fig.23] is a circuit diagram illustrating the connection status of the second fusible portion (Al fusible portion) and a third fusible portion (Al fusible portion).

[0123] The electrode layer 17 to be the first pad electrode 15 and the second pad electrode 16 is arranged on the xy plane including the first contact electrode 11 and the second contact electrode 12. A third conductive material portion 18 may be embedded in the opening 6. The third conductive material portion 18 is in contact with the main surface 2a of the semiconductor substrate 2 located in the opening 6 and is in contact with the connection portion 10 located on the inner wall of the opening 6. Therefore, the third conductive material portion 18 electrically connects the conductive layer constituting the connection portion 10 and the semiconductor substrate 2, and thus functions as a third fusible portion 18. Therefore, the processing target substrate 1 has an electrical conduction state E5 by the second fusible portion 13 and the third fusible portion 18.

[0124] Each of the electrode layer 17 (including the first pad electrode 15 and the second pad electrode 16) and the third fusible portion 18 is made of a metal such as aluminum. Each of the electrode layer 17 and the third fusible portion 18 is obtained by forming a film, for example by sputtering. (Tenth step)

[0125] The tenth step comprises forming a pattern on the electrode layer as a target by wet etching. The tenth step will hereinafter be described with reference to Figures 24 to 26. [Fig. 24] is a top view of a processing target substrate. [Fig. 25] is a cross-sectional view of the processing target substrate shown in [Fig. 24], taken along line XXV-XXV. [Fig. 26] is a circuit diagram illustrating the connection state of the second fusible portion (Al fusible portion) and the third fusible portion (Al fusible portion).

[0126] The electrode layer 17 is provided with a pattern in the form of a target by wet etching. The wet etching can be performed after forming a mask by photolithography. Therefore, the first pad electrode 15 and the second pad electrode 16 are separated from each other. The first pad electrode 15 is electrically connected to the first contact electrode 11 in contact with the xy plane of the first contact electrode 11. The second pad electrode 16 is electrically connected to the second contact electrode 12 in contact with the xy plane of the second contact electrode 12. The second fusible portion 13 and the third fusible portion 18 embedded in the opening 6 are removed by wet etching. After the removal of the second fusible portion 13, a hole 19 including a portion of the main surface 2a of the semiconductor substrate 2 as a bottom wall is formed between the first contact electrode 11 and the second contact electrode 12. The bottom wall of the hole 19 is defined by the portion of the main surface 2a of the semiconductor substrate 2. As a result, the electrical conduction between the first contact electrode 11 and the second contact electrode 12 and the electrical conduction between the semiconductor substrate 2 located in the opening 6 and the connection portion 10 are disconnected. Therefore, as illustrated in [Fig.26], the processing target substrate 1 has a state E6 in which the electrical conduction by the second fusible portion 13 and the electrical conduction by the third fusible portion 18 are disconnected.

[0127] Examples of a wet etchant may include an aqueous solution containing HF and an aqueous solution containing a mixed acid (e.g., containing acetic acid, phosphoric acid, and nitric acid). In the case where the first pad electrode 15, the second pad electrode 16, and the third conductive material portion 18 are formed from aluminum, an aqueous solution containing a mixed acid may be used as a wet etchant. In the case where the barrier layer is present, an aqueous solution containing HF may be used as a wet etchant.

[0128] For easy understanding, [Fig.25] illustrates that there is a boundary between the first contact electrode 11 and the first pad electrode 15 and between the second contact electrode 12 and the second pad electrode 16, but there is not necessarily a boundary (interface). (Eleventh step)

[0129] The eleventh step includes providing an insulating layer (second insulating layer) and providing a mask layer. The eleventh step will hereinafter be described with reference to [Fig.27]. [Fig.27] is a cross-sectional view of the processing target substrate taken along the x-axis direction.

[0130] The entire upper surface of the processing target substrate 1 along the xy plane is covered with a second insulating layer 20. Therefore, the second insulating layer 20 is embedded in the hole 19 formed after removing the second fusible portion 13 and the opening 6 from which the third fusible portion 18 has been removed. The connection portion 10 is also covered with the second insulating layer 20. The second insulating layer 20 is formed of an insulating material such as tetraethoxysilane (TEOS) or polyethyleneimine (PI).

[0131] A mask layer 21 is provided on the second insulating layer 20. The mask layer 21 has a pattern shape having an opening 22. The pattern shape is not particularly limited as long as it has a target shape, and it may for example be provided so that the first pad electrode 15 and the second pad electrode 16 are located on the upper surface along the xy plane of the capacitor. The mask layer 21 may be formed, for example, of an organic material such as a polyimide, a fluorine resin, a phenolic resin, an acrylic resin, or a novolac resin, or of an inorganic material such as silicon oxide or silicon nitride. The mask layer 21 may be formed, for example, by an existing semiconductor process.

[0132] For easy understanding, [Fig.27] illustrates that there is a boundary between the first insulating layer 14 and the second insulating layer 20, but there is not necessarily a boundary (interface). (Twelfth step)

[0133] The twelfth step comprises forming a pattern on the second insulating layer in the form of a target. The twelfth step will hereinafter be described with reference to Figures 28 and 29. [Fig.28] is a top view of a capacitor. [Fig.29] is a cross-sectional view of the capacitor shown in [Fig.28], taken along line XXVIIII-XXVIIII.

[0134] The second insulating layer 20 is provided with a pattern in the form of a target. The patterning may be performed, for example, by wet etching, patterning by exposure and development, or the like. As a result of the patterning, as illustrated in [Fig. 29], the first pad electrode 15 and the second pad electrode 16 are located in an opening 23 of the second insulating layer 20 on the upper surface along the xy plane of the capacitor 31. The first pad electrode 15 and the second pad electrode 16 are electrically insulated by the second insulating layer 20 interposed therebetween. The second insulating layer 20 also surrounds an outer wall of the second pad electrode 16.

[0135] For easy understanding, [Fig.29] illustrates that there is a boundary between the first insulating layer 14 and the second insulating layer 20, but there is not necessarily a boundary (interface).

[0136] The capacitor 31 illustrated in Figures 28 and 29 is obtained by the method comprising the first to twelfth steps above. The capacitor 31 illustrated in Figures 28 and 29 comprises a semiconductor substrate 2 comprising a main surface 2a having one or more recesses 5, conductive layers 4 and 7 disposed in each recess 5 and on the main surface 2a of the semiconductor substrate, a dielectric layer 3 disposed between the conductive layers 4 and 7 and the semiconductor substrate 2, a connection portion 10 extending directly from one or more portions of the conductive layers 4 and 7, and an opening 6 connected to the connection portion 10 and comprising a bottom wall located in the main surface 2a of the semiconductor substrate 2. The capacitor 31 has a hole 19 formed by removing the second fusible portion 13. An insulating layer 20 (insulating material) may be embedded in the opening 6 and the hole 19.

[0137] An operation of detaching the processing target substrate 1 from an electrostatic chuck after processing the pattern shape in the conductive layer by reactive ion etching in a state where the processing target substrate 1, on which the first fusible portion 8 was formed, was clamped to the electrostatic chuck, was repeated 10 times. The processing target substrate 1 could be detached from the electrostatic chuck each time without causing damage, such as cracks, to the processing target substrate 1. In addition, an operation of detaching the processing target substrate 1 from an electrostatic chuck after removing the first fusible portion 8 by reactive ion etching was repeated 10 times. The processing target substrate 1 could be detached from the electrostatic chuck each time without causing damage, such as cracks, to the processing target substrate 1.

[0138] It is noted that the embodiment may include all of the first step through the twelfth step, but some steps may be omitted. In addition, other steps, such as forming a mask layer, forming a barrier layer, and washing, may be performed between any of the first step through the twelfth step.

[0139] The method and capacitor of the embodiments can be applied, for example, to a capacitor comprising a Si wafer having a diameter of 20.32 cm (8 inches) or more as a semiconductor substrate, examples of such a capacitor including a capacitor used in a memory such as a DRAM.

[0140] According to the etching method of at least one embodiment described above, after processing the pattern shape in the conductive layer using dry etching, the semiconductor substrate is brought into electrical conduction with the conductive layer by the first conductive material portion and the connection portion. Therefore, after the dry etching, the processing target substrate can be detached from the electrostatic chuck without causing damage, such as cracks, to the processed substrate. In addition, removing the first conductive material portion by dry etching disconnects the electrical connection between the conductive layer and the semiconductor substrate by the first conductive material portion.Then, since the electrical connection between the conductive layer and the semiconductor substrate is provided by the second conductive material portion, the processing target substrate can be detached from the electrostatic chuck without causing damage, such as cracks, to the processing target substrate after the removal of the first conductive material portion removed by dry etching. Therefore, the method and capacitor of the embodiments can reduce damage such as cracks to the processing target substrate.

[0141] Although certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Moreover, the novel embodiments described herein may be embodied in various other forms; further, various changes, substitutions, and omissions in the form of the embodiments described herein may be made without departing from the spirit of the invention. The accompanying drawings and their equivalents are intended to cover such forms or modifications within the scope and spirit of the invention.

Claims

Claims

1. A method of manufacturing a capacitor, the method comprising: providing a substrate (1) to be processed, the substrate comprising: a semiconductor substrate (2) comprising a main surface having one or more recesses (5); a conductive layer (4) disposed on the main surface and in the one or more recesses of the semiconductor substrate; and a dielectric layer (3) disposed between the conductive layer (4) and the semiconductor substrate (2), an opening (6) penetrating the dielectric layer and the conductive layer which are located on the main surface of the semiconductor substrate; providing a first conductive material portion (8) on the main surface (2a) of the semiconductor substrate (2) located in the opening;processing the conductive layer (4) into a pattern by dry etching, the pattern shape comprising a connection portion (10) extending from the conductive layer and connected to the opening; providing a first contact electrode (11) electrically connected to the conductive layer, a second contact electrode (12) electrically connected to the semiconductor substrate, and a second conductive material portion (13) electrically connecting the first contact electrode and the second contact electrode; performing dry etching of the first conductive material portion (8) to disconnect the electrical connection between the connection portion (10) and the semiconductor substrate (2); and performing wet etching of the second conductive material portion (13) to disconnect the electrical connection between the first contact electrode (11) and the second contact electrode (12).;

2. A method of manufacturing a capacitor according to claim 1, wherein the semiconductor substrate (2) is a Si-containing substrate, and each of the conductive layer (4) and the first conductive material portion (8) contains poly-Si.

3. A method of manufacturing a capacitor according to claim 1 or claim 2, wherein each of the first contact electrode (11), the second contact electrode (12), and the second conductive material portion (13) contains Ai.

4. A method of manufacturing a capacitor according to any one of claims 1 to 3, wherein the dry etching is carried out in a state where the substrate is held by an electrostatic chuck.

5. A method of manufacturing a capacitor according to any one of claims 1 to 4, further comprising: after dry etching the first conductive material portion (8), providing a first pad electrode (15) electrically connected to the first contact electrode (11), a second pad electrode (16) electrically connected to the second contact electrode (12), and a third conductive material portion (18) for electrically connecting the main surface (2a) of the semiconductor substrate (2) located in the opening (6) and the connection portion.

6. A capacitor comprising: a semiconductor substrate (2) including a main surface (2a) having one or more recesses (5); a conductive layer (4) disposed in the one or more recesses (5) and on the main surface (2a) of the semiconductor substrate (2); a dielectric layer (3) disposed between the conductive layer (4) and the semiconductor substrate (2); a connection portion (10) from which the conductive layer located on the main surface of the semiconductor substrate extends; an opening (6) connected to the connection portion (10) and including a bottom wall located in the main surface of the semiconductor substrate; a first contact electrode (11) electrically connected to the conductive layer; a second contact electrode (12) electrically connected to the semiconductor substrate;a hole (19) located between the first contact electrode and the second contact electrode and comprising a bottom wall located in the main surface of the semiconductor substrate; and an insulating layer disposed in the opening and the hole.;

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